diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
| commit | f71fa1715793c764ffa95411e87b73179a7c7b3f (patch) | |
| tree | b4095efe0bda4413326c5860754921b7d8ae78e3 /tests/long/se/60.bzip2/ref/arm/linux | |
| parent | 42fe2df35495685e616f74ad3342953714c7dcc1 (diff) | |
| download | gem5-f71fa1715793c764ffa95411e87b73179a7c7b3f.tar.xz | |
stats: arm: updates
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux')
4 files changed, 1350 insertions, 1349 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index a72b0bcd6..abad5bc99 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.121241 # Number of seconds simulated -sim_ticks 1121241432500 # Number of ticks simulated -final_tick 1121241432500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.121265 # Number of seconds simulated +sim_ticks 1121265462500 # Number of ticks simulated +final_tick 1121265462500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170583 # Simulator instruction rate (inst/s) -host_op_rate 183778 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 123831111 # Simulator tick rate (ticks/s) -host_mem_usage 241824 # Number of bytes of host memory used -host_seconds 9054.60 # Real time elapsed on the host -sim_insts 1544563087 # Number of instructions simulated -sim_ops 1664032480 # Number of ops (including micro ops) simulated +host_inst_rate 175724 # Simulator instruction rate (inst/s) +host_op_rate 189316 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 127565822 # Simulator tick rate (ticks/s) +host_mem_usage 306448 # Number of bytes of host memory used +host_seconds 8789.70 # Real time elapsed on the host +sim_insts 1544563088 # Number of instructions simulated +sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 50560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 131525952 # Number of bytes read from this memory -system.physmem.bytes_read::total 131576512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66977984 # Number of bytes written to this memory -system.physmem.bytes_written::total 66977984 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 790 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2055093 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2055883 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046531 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046531 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 45093 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117303864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 117348956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45093 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45093 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 59735559 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 59735559 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 59735559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 45093 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117303864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 177084516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2055883 # Number of read requests accepted -system.physmem.writeReqs 1046531 # Number of write requests accepted -system.physmem.readBursts 2055883 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046531 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131490688 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 85824 # Total number of bytes read from write queue -system.physmem.bytesWritten 66976384 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131576512 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66977984 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1341 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 50816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 131531264 # Number of bytes read from this memory +system.physmem.bytes_read::total 131582080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66976320 # Number of bytes written to this memory +system.physmem.bytes_written::total 66976320 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 794 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2055176 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2055970 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046505 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046505 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 45320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117306087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117351407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45320 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45320 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 59732795 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 59732795 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 59732795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117306087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177084202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2055970 # Number of read requests accepted +system.physmem.writeReqs 1046505 # Number of write requests accepted +system.physmem.readBursts 2055970 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046505 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131497344 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 84736 # Total number of bytes read from write queue +system.physmem.bytesWritten 66974720 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131582080 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66976320 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1324 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127988 # Per bank write bursts -system.physmem.perBankRdBursts::1 125250 # Per bank write bursts -system.physmem.perBankRdBursts::2 122092 # Per bank write bursts -system.physmem.perBankRdBursts::3 124158 # Per bank write bursts -system.physmem.perBankRdBursts::4 123330 # Per bank write bursts -system.physmem.perBankRdBursts::5 123315 # Per bank write bursts -system.physmem.perBankRdBursts::6 123951 # Per bank write bursts -system.physmem.perBankRdBursts::7 124319 # Per bank write bursts -system.physmem.perBankRdBursts::8 132052 # Per bank write bursts -system.physmem.perBankRdBursts::9 134015 # Per bank write bursts -system.physmem.perBankRdBursts::10 132327 # Per bank write bursts -system.physmem.perBankRdBursts::11 133706 # Per bank write bursts -system.physmem.perBankRdBursts::12 133817 # Per bank write bursts -system.physmem.perBankRdBursts::13 133969 # Per bank write bursts -system.physmem.perBankRdBursts::14 129938 # Per bank write bursts -system.physmem.perBankRdBursts::15 130315 # Per bank write bursts -system.physmem.perBankWrBursts::0 65788 # Per bank write bursts +system.physmem.perBankRdBursts::0 128088 # Per bank write bursts +system.physmem.perBankRdBursts::1 125235 # Per bank write bursts +system.physmem.perBankRdBursts::2 122283 # Per bank write bursts +system.physmem.perBankRdBursts::3 124122 # Per bank write bursts +system.physmem.perBankRdBursts::4 123237 # Per bank write bursts +system.physmem.perBankRdBursts::5 123404 # Per bank write bursts +system.physmem.perBankRdBursts::6 123754 # Per bank write bursts +system.physmem.perBankRdBursts::7 124260 # Per bank write bursts +system.physmem.perBankRdBursts::8 132002 # Per bank write bursts +system.physmem.perBankRdBursts::9 134077 # Per bank write bursts +system.physmem.perBankRdBursts::10 132455 # Per bank write bursts +system.physmem.perBankRdBursts::11 133729 # Per bank write bursts +system.physmem.perBankRdBursts::12 133726 # Per bank write bursts +system.physmem.perBankRdBursts::13 133924 # Per bank write bursts +system.physmem.perBankRdBursts::14 129890 # Per bank write bursts +system.physmem.perBankRdBursts::15 130460 # Per bank write bursts +system.physmem.perBankWrBursts::0 65849 # Per bank write bursts system.physmem.perBankWrBursts::1 64148 # Per bank write bursts -system.physmem.perBankWrBursts::2 62323 # Per bank write bursts -system.physmem.perBankWrBursts::3 62858 # Per bank write bursts -system.physmem.perBankWrBursts::4 62842 # Per bank write bursts -system.physmem.perBankWrBursts::5 62926 # Per bank write bursts -system.physmem.perBankWrBursts::6 64344 # Per bank write bursts -system.physmem.perBankWrBursts::7 65270 # Per bank write bursts -system.physmem.perBankWrBursts::8 67114 # Per bank write bursts -system.physmem.perBankWrBursts::9 67597 # Per bank write bursts -system.physmem.perBankWrBursts::10 67253 # Per bank write bursts -system.physmem.perBankWrBursts::11 67655 # Per bank write bursts -system.physmem.perBankWrBursts::12 67032 # Per bank write bursts -system.physmem.perBankWrBursts::13 67505 # Per bank write bursts -system.physmem.perBankWrBursts::14 66189 # Per bank write bursts -system.physmem.perBankWrBursts::15 65662 # Per bank write bursts +system.physmem.perBankWrBursts::2 62390 # Per bank write bursts +system.physmem.perBankWrBursts::3 62849 # Per bank write bursts +system.physmem.perBankWrBursts::4 62818 # Per bank write bursts +system.physmem.perBankWrBursts::5 62997 # Per bank write bursts +system.physmem.perBankWrBursts::6 64238 # Per bank write bursts +system.physmem.perBankWrBursts::7 65252 # Per bank write bursts +system.physmem.perBankWrBursts::8 67098 # Per bank write bursts +system.physmem.perBankWrBursts::9 67598 # Per bank write bursts +system.physmem.perBankWrBursts::10 67270 # Per bank write bursts +system.physmem.perBankWrBursts::11 67670 # Per bank write bursts +system.physmem.perBankWrBursts::12 67009 # Per bank write bursts +system.physmem.perBankWrBursts::13 67470 # Per bank write bursts +system.physmem.perBankWrBursts::14 66159 # Per bank write bursts +system.physmem.perBankWrBursts::15 65665 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1121241338000 # Total gap between requests +system.physmem.totGap 1121265368000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2055883 # Read request sizes (log2) +system.physmem.readPktSize::6 2055970 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046531 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1926751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127772 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046505 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1926795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127832 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,28 +144,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -193,105 +193,105 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1919691 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.383938 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.729389 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 124.654868 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1494811 77.87% 77.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305161 15.90% 93.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53151 2.77% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21323 1.11% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13050 0.68% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7398 0.39% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5428 0.28% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5020 0.26% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14349 0.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1919691 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60985 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.641650 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.664141 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60945 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1920747 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.329698 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.701744 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 124.647307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1495902 77.88% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305625 15.91% 93.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52698 2.74% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21305 1.11% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13173 0.69% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7131 0.37% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5450 0.28% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5094 0.27% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14369 0.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1920747 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60965 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.654375 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.846066 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60925 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 15 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60985 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60985 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.160056 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.125150 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.096252 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27287 44.74% 44.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1323 2.17% 46.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28176 46.20% 93.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3806 6.24% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 330 0.54% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 51 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60965 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60965 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.165259 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.130353 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.096188 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27136 44.51% 44.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1324 2.17% 46.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28285 46.40% 93.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3807 6.24% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 355 0.58% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 47 0.08% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60985 # Writes before turning the bus around for reads -system.physmem.totQLat 38434561000 # Total ticks spent queuing -system.physmem.totMemAccLat 76957223500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10272710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18707.12 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60965 # Writes before turning the bus around for reads +system.physmem.totQLat 38466601000 # Total ticks spent queuing +system.physmem.totMemAccLat 76991213500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10273230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18721.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37457.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 117.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 37471.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 117.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 59.73 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 117.35 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 59.74 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 59.73 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.38 # Data bus utilization in percentage system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing -system.physmem.readRowHits 774810 # Number of row buffer hits during reads -system.physmem.writeRowHits 406537 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes -system.physmem.avgGap 361409.32 # Average gap between requests -system.physmem.pageHitRate 38.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7080832080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3863549250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7756031400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3308033520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 73233657120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 422818284195 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 301848259500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 819908647065 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.254419 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 499427924250 # Time in different power states -system.physmem_0.memoryStateTime::REF 37440520000 # Time in different power states +system.physmem.avgWrQLen 24.95 # Average write queue length when enqueuing +system.physmem.readRowHits 774547 # Number of row buffer hits during reads +system.physmem.writeRowHits 405822 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.70 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.78 # Row buffer hit rate for writes +system.physmem.avgGap 361409.96 # Average gap between requests +system.physmem.pageHitRate 38.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7084922040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3865780875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7755875400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3308305680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 73235182800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 422966689965 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301732094250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 819948851010 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.275041 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 499232206000 # Time in different power states +system.physmem_0.memoryStateTime::REF 37441300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 584369735750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 584588629000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7432016760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4055167875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8269029600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3473325360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 73233657120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 431345081205 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 294368613000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 822176890920 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.277404 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 486933261750 # Time in different power states -system.physmem_1.memoryStateTime::REF 37440520000 # Time in different power states +system.physmem_1.actEnergy 7435910160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4057292250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8269996800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3472884720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 73235182800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 431711081055 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 294061575750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 822243923535 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.321912 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 486423236500 # Time in different power states +system.physmem_1.memoryStateTime::REF 37441300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 596864300250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 597397500000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 240141357 # Number of BP lookups -system.cpu.branchPred.condPredicted 186745174 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14595264 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132286195 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122283419 # Number of BTB hits +system.cpu.branchPred.lookups 240144458 # Number of BP lookups +system.cpu.branchPred.condPredicted 186748856 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14594265 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132793559 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122289853 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.438534 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15659523 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.090199 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15658823 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -411,68 +411,68 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2242482865 # number of cpu cycles simulated +system.cpu.numCycles 2242530925 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1544563087 # Number of instructions committed -system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed -system.cpu.discardedOps 40063388 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 1544563088 # Number of instructions committed +system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed +system.cpu.discardedOps 40067412 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.451856 # CPI: cycles per instruction -system.cpu.ipc 0.688774 # IPC: instructions per cycle -system.cpu.tickCycles 1838984644 # Number of cycles that the object actually ticked -system.cpu.idleCycles 403498221 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9223361 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.642531 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624067002 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9227457 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.631526 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9813070000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642531 # Average occupied blocks per requestor +system.cpu.cpi 1.451887 # CPI: cycles per instruction +system.cpu.ipc 0.688759 # IPC: instructions per cycle +system.cpu.tickCycles 1838970368 # Number of cycles that the object actually ticked +system.cpu.idleCycles 403560557 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9223420 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.640559 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624065637 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9227516 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.630946 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9814734000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.640559 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997471 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997471 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1217 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1219 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276544027 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276544027 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453735352 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453735352 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331527 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331527 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276541490 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276541490 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453733959 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453733959 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331555 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331555 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624066879 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624066879 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624066880 # number of overall hits -system.cpu.dcache.overall_hits::total 624066880 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7336761 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7336761 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254520 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254520 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624065514 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624065514 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624065515 # number of overall hits +system.cpu.dcache.overall_hits::total 624065515 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7336856 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7336856 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254492 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254492 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9591281 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9591281 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9591283 # number of overall misses -system.cpu.dcache.overall_misses::total 9591283 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442274246 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 192442274246 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711140250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109711140250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 302153414496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 302153414496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 302153414496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 302153414496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461072113 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461072113 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9591348 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9591348 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9591350 # number of overall misses +system.cpu.dcache.overall_misses::total 9591350 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 192473949996 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 192473949996 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109728776250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109728776250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 302202726246 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 302202726246 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 302202726246 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 302202726246 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461070815 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461070815 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -481,28 +481,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633658160 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633658160 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633658163 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633658163 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015912 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015912 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 633656862 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633656862 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633656865 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633656865 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015913 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013063 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013063 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015136 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015136 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015136 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015136 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.868227 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.868227 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48662.748723 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48662.748723 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31502.925886 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31502.925886 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31502.919317 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31502.919317 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.015137 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015137 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015137 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015137 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26233.845941 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26233.845941 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48671.175702 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48671.175702 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31507.847098 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31507.847098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31507.840528 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31507.840528 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,36 +511,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3701040 # number of writebacks -system.cpu.dcache.writebacks::total 3701040 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 208 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363617 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 363617 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 363825 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 363825 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 363825 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 363825 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336553 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7336553 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890903 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890903 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3700612 # number of writebacks +system.cpu.dcache.writebacks::total 3700612 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 212 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 212 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363621 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 363621 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 363833 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 363833 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 363833 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 363833 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336644 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7336644 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890871 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890871 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9227456 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9227456 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9227457 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9227457 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181020814754 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 181020814754 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83976850000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83976850000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9227515 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9227515 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9227516 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9227516 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181052332504 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 181052332504 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83984263000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83984263000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 73750 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 73750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264997664754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 264997664754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264997738504 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 264997738504 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265036595504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 265036595504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265036669254 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 265036669254 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015912 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015912 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -551,69 +551,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014562 system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24673.823627 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24673.823627 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44410.977189 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44410.977189 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24677.813521 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24677.813521 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44415.649190 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44415.649190 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73750 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73750 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28718.388335 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28718.388335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28718.393215 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28718.393215 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28722.423697 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28722.423697 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28722.428577 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28722.428577 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 32 # number of replacements -system.cpu.icache.tags.tagsinuse 661.433391 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466139348 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 566390.459295 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 35 # number of replacements +system.cpu.icache.tags.tagsinuse 662.614734 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466141021 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 828 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 562972.247585 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.433391 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322966 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322966 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 662.614734 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.323542 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.323542 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 793 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932281165 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932281165 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 466139348 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466139348 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466139348 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466139348 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466139348 # number of overall hits -system.cpu.icache.overall_hits::total 466139348 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses -system.cpu.icache.overall_misses::total 823 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 63711749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 63711749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 63711749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 63711749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 63711749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 63711749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466140171 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466140171 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466140171 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466140171 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466140171 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466140171 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.387207 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 932284526 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932284526 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 466141021 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466141021 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466141021 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466141021 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466141021 # number of overall hits +system.cpu.icache.overall_hits::total 466141021 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 828 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 828 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 828 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 828 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 828 # number of overall misses +system.cpu.icache.overall_misses::total 828 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 63773749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 63773749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 63773749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 63773749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 63773749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 63773749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 466141849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466141849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466141849 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466141849 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466141849 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466141849 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77414.032807 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77414.032807 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77414.032807 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77414.032807 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77414.032807 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77414.032807 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77021.435990 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77021.435990 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77021.435990 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77021.435990 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77021.435990 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77021.435990 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -622,123 +622,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 823 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62143751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 62143751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62143751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 62143751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62143751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 62143751 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 828 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 828 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 828 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 828 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 828 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 828 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62196251 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 62196251 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62196251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 62196251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62196251 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 62196251 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75508.810450 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75508.810450 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75508.810450 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75508.810450 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75508.810450 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75508.810450 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75116.245169 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75116.245169 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75116.245169 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75116.245169 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75116.245169 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75116.245169 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2023178 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31261.935104 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8984732 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2052953 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.376492 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2023265 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31261.991003 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8984313 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2053040 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.376102 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 59841737750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14973.678994 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.751537 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16261.504573 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.456960 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000816 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.496262 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.954039 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14971.940870 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.910061 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16263.140072 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.456907 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000821 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.496312 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.954040 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12852 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15555 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15554 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107378416 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107378416 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6081604 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6081636 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3701040 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3701040 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1090756 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1090756 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7172360 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7172392 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7172360 # number of overall hits -system.cpu.l2cache.overall_hits::total 7172392 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 791 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1254950 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1255741 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 800147 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 800147 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 791 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2055097 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2055888 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 791 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2055097 # number of overall misses -system.cpu.l2cache.overall_misses::total 2055888 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60983250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109821544000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 109882527250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70568052000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 70568052000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 60983250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 180389596000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 180450579250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 60983250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 180389596000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 180450579250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 823 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7336554 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7337377 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3701040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3701040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890903 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1890903 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 823 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9227457 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9228280 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 823 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9227457 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9228280 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961118 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.171054 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.171143 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423156 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.423156 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961118 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.222715 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.222781 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961118 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.222715 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.222781 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77096.396966 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87510.692856 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 87504.132819 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88193.859378 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88193.859378 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77096.396966 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87776.682074 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87772.572849 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77096.396966 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87776.682074 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87772.572849 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 107375559 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 107375559 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 33 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6081577 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6081610 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3700612 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700612 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1090759 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1090759 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 33 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7172336 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7172369 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 33 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7172336 # number of overall hits +system.cpu.l2cache.overall_hits::total 7172369 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1255068 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1255863 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 800112 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 800112 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 795 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2055180 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2055975 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 795 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2055180 # number of overall misses +system.cpu.l2cache.overall_misses::total 2055975 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 61020250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109853349250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 109914369500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70575135000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 70575135000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 61020250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 180428484250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 180489504500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 61020250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 180428484250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 180489504500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 828 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7336645 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7337473 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3700612 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3700612 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890871 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1890871 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 828 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9227516 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9228344 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 828 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9227516 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9228344 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960145 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.171068 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.171157 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423145 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.423145 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960145 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.222723 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.222789 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960145 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.222723 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.222789 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76755.031447 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87527.806661 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 87520.987162 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88206.569830 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88206.569830 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76755.031447 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87792.059211 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87787.791437 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76755.031447 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87792.059211 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87787.791437 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -747,8 +747,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1046531 # number of writebacks -system.cpu.l2cache.writebacks::total 1046531 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1046505 # number of writebacks +system.cpu.l2cache.writebacks::total 1046505 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits @@ -758,105 +758,105 @@ system.cpu.l2cache.demand_mshr_hits::total 5 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 790 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254946 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1255736 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 800147 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 800147 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 790 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2055093 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2055883 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 790 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2055093 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2055883 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51082250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93955002000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006084250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459126500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459126500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51082250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414128500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 154465210750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51082250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414128500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 154465210750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171054 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171142 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423156 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423156 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.222781 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.222781 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64661.075949 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74867.764828 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.343666 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.023971 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.023971 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64661.075949 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294760 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.269135 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64661.075949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294760 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.269135 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 794 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1255064 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1255858 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 800112 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 800112 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 794 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2055176 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2055970 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 794 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2055176 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2055970 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51069250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93985038750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94036108000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60466755500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60466755500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51069250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154451794250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 154502863500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51069250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154451794250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 154502863500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958937 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171068 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171157 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423145 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423145 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958937 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222723 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222789 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958937 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222723 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222789 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64318.954660 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74884.658272 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74877.978243 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75572.864174 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75572.864174 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64318.954660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75152.587540 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75148.403673 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64318.954660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75152.587540 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75148.403673 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7337377 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7337377 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3701040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890903 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890903 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1646 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22155954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22157600 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827423808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827476480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7337473 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7337473 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890871 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890871 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1656 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22155644 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22157300 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827400192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827453184 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12929320 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12928956 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 12929320 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 12928956 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12929320 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10165700000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12928956 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10165090000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1401249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1409749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14190167496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14190252246 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1255736 # Transaction distribution -system.membus.trans_dist::ReadResp 1255736 # Transaction distribution -system.membus.trans_dist::Writeback 1046531 # Transaction distribution -system.membus.trans_dist::ReadExReq 800147 # Transaction distribution -system.membus.trans_dist::ReadExResp 800147 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158297 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5158297 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198554496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198554496 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1255858 # Transaction distribution +system.membus.trans_dist::ReadResp 1255858 # Transaction distribution +system.membus.trans_dist::Writeback 1046505 # Transaction distribution +system.membus.trans_dist::ReadExReq 800112 # Transaction distribution +system.membus.trans_dist::ReadExResp 800112 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158445 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5158445 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198558400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198558400 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3102414 # Request fanout histogram +system.membus.snoop_fanout::samples 3102475 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3102414 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3102475 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3102414 # Request fanout histogram -system.membus.reqLayer0.occupancy 7944829000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3102475 # Request fanout histogram +system.membus.reqLayer0.occupancy 7945005500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 11243795750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11244435500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index b2838e173..ddc6d4e58 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.771783 # Number of seconds simulated -sim_ticks 771782683000 # Number of ticks simulated -final_tick 771782683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.771725 # Number of seconds simulated +sim_ticks 771725169000 # Number of ticks simulated +final_tick 771725169000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140791 # Simulator instruction rate (inst/s) -host_op_rate 151681 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70349895 # Simulator tick rate (ticks/s) -host_mem_usage 240068 # Number of bytes of host memory used -host_seconds 10970.63 # Real time elapsed on the host -sim_insts 1544563023 # Number of instructions simulated -sim_ops 1664032415 # Number of ops (including micro ops) simulated +host_inst_rate 109963 # Simulator instruction rate (inst/s) +host_op_rate 118469 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54942138 # Simulator tick rate (ticks/s) +host_mem_usage 305172 # Number of bytes of host memory used +host_seconds 14046.14 # Real time elapsed on the host +sim_insts 1544563024 # Number of instructions simulated +sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 66112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 238756480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63336128 # Number of bytes read from this memory -system.physmem.bytes_read::total 302158720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 66112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 66112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104900608 # Number of bytes written to this memory -system.physmem.bytes_written::total 104900608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1033 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3730570 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 989627 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4721230 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1639072 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1639072 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 85661 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309357135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82064718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 391507515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 85661 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85661 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 135919878 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 135919878 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 135919878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 85661 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309357135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82064718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 527427392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4721230 # Number of read requests accepted -system.physmem.writeReqs 1639072 # Number of write requests accepted -system.physmem.readBursts 4721230 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1639072 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 301708544 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 450176 # Total number of bytes read from write queue -system.physmem.bytesWritten 104898432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 302158720 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104900608 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7034 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 238609216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63286144 # Number of bytes read from this memory +system.physmem.bytes_read::total 301961664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104822848 # Number of bytes written to this memory +system.physmem.bytes_written::total 104822848 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3728269 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 988846 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4718151 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1637857 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1637857 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 85917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309189366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82006065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 391281347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 85917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 135829246 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 135829246 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 135829246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 85917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309189366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82006065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 527110594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4718151 # Number of read requests accepted +system.physmem.writeReqs 1637857 # Number of write requests accepted +system.physmem.readBursts 4718151 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1637857 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 301519872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 441792 # Total number of bytes read from write queue +system.physmem.bytesWritten 104820544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 301961664 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104822848 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6903 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 19 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 296496 # Per bank write bursts -system.physmem.perBankRdBursts::1 294922 # Per bank write bursts -system.physmem.perBankRdBursts::2 288553 # Per bank write bursts -system.physmem.perBankRdBursts::3 293200 # Per bank write bursts -system.physmem.perBankRdBursts::4 290519 # Per bank write bursts -system.physmem.perBankRdBursts::5 289057 # Per bank write bursts -system.physmem.perBankRdBursts::6 284695 # Per bank write bursts -system.physmem.perBankRdBursts::7 280747 # Per bank write bursts -system.physmem.perBankRdBursts::8 297891 # Per bank write bursts -system.physmem.perBankRdBursts::9 303659 # Per bank write bursts -system.physmem.perBankRdBursts::10 295750 # Per bank write bursts -system.physmem.perBankRdBursts::11 302488 # Per bank write bursts -system.physmem.perBankRdBursts::12 303486 # Per bank write bursts -system.physmem.perBankRdBursts::13 302338 # Per bank write bursts -system.physmem.perBankRdBursts::14 297681 # Per bank write bursts -system.physmem.perBankRdBursts::15 292714 # Per bank write bursts -system.physmem.perBankWrBursts::0 104090 # Per bank write bursts -system.physmem.perBankWrBursts::1 102136 # Per bank write bursts -system.physmem.perBankWrBursts::2 99204 # Per bank write bursts -system.physmem.perBankWrBursts::3 100079 # Per bank write bursts -system.physmem.perBankWrBursts::4 99319 # Per bank write bursts -system.physmem.perBankWrBursts::5 99058 # Per bank write bursts -system.physmem.perBankWrBursts::6 102867 # Per bank write bursts -system.physmem.perBankWrBursts::7 104266 # Per bank write bursts -system.physmem.perBankWrBursts::8 105488 # Per bank write bursts -system.physmem.perBankWrBursts::9 104503 # Per bank write bursts -system.physmem.perBankWrBursts::10 102301 # Per bank write bursts -system.physmem.perBankWrBursts::11 102956 # Per bank write bursts -system.physmem.perBankWrBursts::12 103260 # Per bank write bursts -system.physmem.perBankWrBursts::13 102520 # Per bank write bursts -system.physmem.perBankWrBursts::14 104484 # Per bank write bursts -system.physmem.perBankWrBursts::15 102507 # Per bank write bursts +system.physmem.perBankRdBursts::0 296668 # Per bank write bursts +system.physmem.perBankRdBursts::1 294562 # Per bank write bursts +system.physmem.perBankRdBursts::2 288307 # Per bank write bursts +system.physmem.perBankRdBursts::3 292737 # Per bank write bursts +system.physmem.perBankRdBursts::4 290232 # Per bank write bursts +system.physmem.perBankRdBursts::5 289394 # Per bank write bursts +system.physmem.perBankRdBursts::6 285167 # Per bank write bursts +system.physmem.perBankRdBursts::7 280683 # Per bank write bursts +system.physmem.perBankRdBursts::8 297292 # Per bank write bursts +system.physmem.perBankRdBursts::9 302920 # Per bank write bursts +system.physmem.perBankRdBursts::10 295430 # Per bank write bursts +system.physmem.perBankRdBursts::11 301815 # Per bank write bursts +system.physmem.perBankRdBursts::12 303322 # Per bank write bursts +system.physmem.perBankRdBursts::13 302849 # Per bank write bursts +system.physmem.perBankRdBursts::14 297025 # Per bank write bursts +system.physmem.perBankRdBursts::15 292845 # Per bank write bursts +system.physmem.perBankWrBursts::0 103942 # Per bank write bursts +system.physmem.perBankWrBursts::1 102053 # Per bank write bursts +system.physmem.perBankWrBursts::2 99317 # Per bank write bursts +system.physmem.perBankWrBursts::3 99871 # Per bank write bursts +system.physmem.perBankWrBursts::4 99169 # Per bank write bursts +system.physmem.perBankWrBursts::5 98963 # Per bank write bursts +system.physmem.perBankWrBursts::6 102735 # Per bank write bursts +system.physmem.perBankWrBursts::7 104389 # Per bank write bursts +system.physmem.perBankWrBursts::8 105226 # Per bank write bursts +system.physmem.perBankWrBursts::9 104532 # Per bank write bursts +system.physmem.perBankWrBursts::10 102159 # Per bank write bursts +system.physmem.perBankWrBursts::11 102806 # Per bank write bursts +system.physmem.perBankWrBursts::12 103028 # Per bank write bursts +system.physmem.perBankWrBursts::13 102702 # Per bank write bursts +system.physmem.perBankWrBursts::14 104263 # Per bank write bursts +system.physmem.perBankWrBursts::15 102666 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 771782536000 # Total gap between requests +system.physmem.totGap 771725022000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4721230 # Read request sizes (log2) +system.physmem.readPktSize::6 4718151 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1639072 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2775597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1044443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 331745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 234202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 153941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 85295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 39428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1637857 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2774626 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1044189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 331696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 233512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 153773 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 84990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 39149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 411 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,37 +148,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 60114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 75847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 110847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 113228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 106323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 103422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 22760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 59860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 75448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 110632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 113547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 106733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 103419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -197,120 +197,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4289012 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.801701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.923105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 101.558340 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3414847 79.62% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 675748 15.76% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96615 2.25% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35482 0.83% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22807 0.53% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12154 0.28% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7173 0.17% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5164 0.12% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19022 0.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4289012 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98837 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.696531 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 32.309771 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 98.301255 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-127 95044 96.16% 96.16% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-255 1344 1.36% 97.52% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4287400 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.775232 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.917076 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 101.448471 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3413764 79.62% 79.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 675374 15.75% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96809 2.26% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35249 0.82% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22885 0.53% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12087 0.28% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7187 0.17% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5043 0.12% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19002 0.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4287400 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.700609 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 32.313411 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 98.282358 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 94950 96.14% 96.14% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1367 1.38% 97.52% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::256-383 770 0.78% 98.30% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-511 419 0.42% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-639 374 0.38% 99.10% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-767 356 0.36% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-895 254 0.26% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::896-1023 146 0.15% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1151 62 0.06% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1152-1279 41 0.04% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1407 8 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1408-1535 7 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1663 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 428 0.43% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 356 0.36% 99.09% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 374 0.38% 99.47% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 247 0.25% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 145 0.15% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 66 0.07% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 31 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 13 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 9 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1663 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1920-2047 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2687 3 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3200-3327 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98837 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98837 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.583243 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.550199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.089458 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 73410 74.27% 74.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1674 1.69% 75.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18461 18.68% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3603 3.65% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 928 0.94% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 388 0.39% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 174 0.18% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 100 0.10% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 61 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 27 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 7 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98837 # Writes before turning the bus around for reads -system.physmem.totQLat 132409571838 # Total ticks spent queuing -system.physmem.totMemAccLat 220800746838 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23570980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28087.41 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::1920-2047 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2688-2815 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2944-3071 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3199 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3200-3327 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3328-3455 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 98767 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98767 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.582674 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.549780 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.086524 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 73305 74.22% 74.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1806 1.83% 76.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18343 18.57% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3630 3.68% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 937 0.95% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 387 0.39% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 162 0.16% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 107 0.11% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 60 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 22 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 98767 # Writes before turning the bus around for reads +system.physmem.totQLat 132285118194 # Total ticks spent queuing +system.physmem.totMemAccLat 220621018194 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23556240000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28078.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46837.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 390.92 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 135.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 391.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 135.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46828.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 390.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 135.83 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 391.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 135.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.12 # Data bus utilization in percentage +system.physmem.busUtil 4.11 # Data bus utilization in percentage system.physmem.busUtilRead 3.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing -system.physmem.readRowHits 1710867 # Number of row buffer hits during reads -system.physmem.writeRowHits 353347 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.56 # Row buffer hit rate for writes -system.physmem.avgGap 121343.69 # Average gap between requests -system.physmem.pageHitRate 32.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16078381200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8772926250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18081671400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5255351280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 410988240855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 102552687000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 612138233745 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.150023 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 168058001250 # Time in different power states -system.physmem_0.memoryStateTime::REF 25771460000 # Time in different power states +system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing +system.physmem.readRowHits 1709073 # Number of row buffer hits during reads +system.physmem.writeRowHits 352585 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.53 # Row buffer hit rate for writes +system.physmem.avgGap 121416.62 # Average gap between requests +system.physmem.pageHitRate 32.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16073195040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8770096500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18077007000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5251294800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50404907280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 410674128390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 102790850250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 612041479260 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.088667 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 168453702129 # Time in different power states +system.physmem_0.memoryStateTime::REF 25769380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 577951698750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 577496605871 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16346489040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8919215250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18688846800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5365504800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 412404849315 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 101310048000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 613443928965 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.841817 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165993972457 # Time in different power states -system.physmem_1.memoryStateTime::REF 25771460000 # Time in different power states +system.physmem_1.actEnergy 16339027320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8915143875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18669222000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5361163200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50404907280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 412008151545 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 101620654500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 613318269720 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.743144 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 166509885283 # Time in different power states +system.physmem_1.memoryStateTime::REF 25769380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 580015821043 # Time in different power states +system.physmem_1.memoryStateTime::ACT 579440435717 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286268512 # Number of BP lookups -system.cpu.branchPred.condPredicted 223399208 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14631885 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157652290 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150341382 # Number of BTB hits +system.cpu.branchPred.lookups 286277860 # Number of BP lookups +system.cpu.branchPred.condPredicted 223409255 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14633591 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157407621 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150346120 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.362638 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16641174 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 95.513876 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16641206 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -430,94 +431,94 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1543565367 # number of cpu cycles simulated +system.cpu.numCycles 1543450339 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13925779 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067423618 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286268512 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166982556 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1514915602 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29288421 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 919 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656914213 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 942 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1543486763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.434983 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229356 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13927699 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067517377 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286277860 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166987326 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1514795150 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29291799 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 907 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656942032 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 957 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1543369835 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.435149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229340 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 461116597 29.87% 29.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465422138 30.15% 60.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101389056 6.57% 66.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515558972 33.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 460957271 29.87% 29.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465455811 30.16% 60.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101360614 6.57% 66.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515596139 33.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1543486763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185459 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.339382 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74615169 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 546131714 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 850052649 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58043724 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14643507 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42202613 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037139109 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52472329 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14643507 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139680975 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 464946049 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14177 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837873228 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86328827 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976320354 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26732336 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45128593 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125639 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1500891 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25518898 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985788047 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9127865226 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432787425 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 124 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1543369835 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185479 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.339543 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74619350 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 545977788 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 850086533 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58040967 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14645197 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42200501 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 754 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037190940 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52475133 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14645197 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139685845 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 464851768 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13523 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837895691 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86277811 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976364426 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26735694 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45105241 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125505 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1481556 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25500508 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985835865 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128071192 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432849079 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 136 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310889102 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 151 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 141 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111344488 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542536301 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199301557 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26908887 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29198248 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947883742 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 210 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857409514 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13500100 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283851537 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 646881302 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1543486763 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.203385 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.151093 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 310936920 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 149 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 140 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111342876 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542549398 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199301403 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26926926 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29153523 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947926711 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 208 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857446823 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13498178 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283894503 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 646939215 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1543369835 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.203501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151095 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 590762659 38.27% 38.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325764931 21.11% 59.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378272466 24.51% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219653351 14.23% 98.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29027182 1.88% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6174 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 590630846 38.27% 38.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325771475 21.11% 59.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378267234 24.51% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219666416 14.23% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29027688 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6176 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1543486763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1543369835 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166053840 40.99% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1992 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166059149 40.99% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1996 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available @@ -545,13 +546,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191416352 47.25% 88.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47630536 11.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191393147 47.24% 88.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47682914 11.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138248479 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801009 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138268714 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801071 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -573,102 +574,102 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 26 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 28 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532044411 28.64% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186315567 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532058987 28.64% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186318001 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857409514 # Type of FU issued -system.cpu.iq.rate 1.203324 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405102720 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218101 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5676908390 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231748222 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805707256 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 208 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262512110 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 124 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17814082 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857446823 # Type of FU issued +system.cpu.iq.rate 1.203438 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405137206 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5676898637 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231834122 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805736851 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 228 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 232 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262583902 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 127 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17817639 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84229967 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66402 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 84243064 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66651 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 13168 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24454512 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 24454358 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4520775 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4802645 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4525889 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4805394 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14643507 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25316113 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1330365 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947884031 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14645197 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25323327 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1332663 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947926995 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542536301 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199301557 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 148 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 158933 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1170467 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 542549398 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199301403 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 146 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 158839 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1172731 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 13168 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7700956 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8705023 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16405979 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827745758 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516865735 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29663756 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 7701738 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8706499 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16408237 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827783249 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516881888 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29663574 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 79 # number of nop insts executed -system.cpu.iew.exec_refs 698617938 # number of memory reference insts executed -system.cpu.iew.exec_branches 229554698 # Number of branches executed -system.cpu.iew.exec_stores 181752203 # Number of stores executed -system.cpu.iew.exec_rate 1.184106 # Inst execution rate -system.cpu.iew.wb_sent 1808737138 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805707322 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169287953 # num instructions producing a value -system.cpu.iew.wb_consumers 1689671414 # num instructions consuming a value +system.cpu.iew.exec_nop 76 # number of nop insts executed +system.cpu.iew.exec_refs 698636146 # number of memory reference insts executed +system.cpu.iew.exec_branches 229555717 # Number of branches executed +system.cpu.iew.exec_stores 181754258 # Number of stores executed +system.cpu.iew.exec_rate 1.184219 # Inst execution rate +system.cpu.iew.wb_sent 1808767141 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805736919 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169322951 # num instructions producing a value +system.cpu.iew.wb_consumers 1689713401 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.169829 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692021 # average fanout of values written-back +system.cpu.iew.wb_rate 1.169935 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692024 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 257958644 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 258002520 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14631182 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1504006174 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.106400 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.024308 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14632889 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1503882923 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.106491 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.024391 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 923727407 61.42% 61.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250637926 16.66% 78.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110048306 7.32% 85.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55269063 3.67% 89.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29308073 1.95% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34102690 2.27% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24713726 1.64% 94.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18129256 1.21% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58069727 3.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 923604765 61.41% 61.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250635322 16.67% 78.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110056363 7.32% 85.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55280526 3.68% 89.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29292132 1.95% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34092515 2.27% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24716046 1.64% 94.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18126603 1.21% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58078651 3.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1504006174 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563041 # Number of instructions committed -system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1503882923 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563042 # Number of instructions committed +system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 633153379 # Number of memory references committed system.cpu.commit.loads 458306334 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462426 # Number of branches committed +system.cpu.commit.branches 213462427 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1030178729 61.91% 61.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction @@ -701,77 +702,77 @@ system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Cl system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction -system.cpu.commit.bw_lim_events 58069727 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3367926925 # The number of ROB reads -system.cpu.rob.rob_writes 3883468057 # The number of ROB writes -system.cpu.timesIdled 846 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 78604 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563023 # Number of Instructions Simulated -system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.999354 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.999354 # CPI: Total CPI of All Threads -system.cpu.ipc 1.000646 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.000646 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175695472 # number of integer regfile reads -system.cpu.int_regfile_writes 1261559121 # number of integer regfile writes +system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction +system.cpu.commit.bw_lim_events 58078651 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3367838627 # The number of ROB reads +system.cpu.rob.rob_writes 3883562090 # The number of ROB writes +system.cpu.timesIdled 851 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 80504 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563024 # Number of Instructions Simulated +system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.999280 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.999280 # CPI: Total CPI of All Threads +system.cpu.ipc 1.000721 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.000721 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175739809 # number of integer regfile reads +system.cpu.int_regfile_writes 1261583749 # number of integer regfile writes system.cpu.fp_regfile_reads 38 # number of floating regfile reads -system.cpu.fp_regfile_writes 48 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965502930 # number of cc regfile reads -system.cpu.cc_regfile_writes 551873305 # number of cc regfile writes -system.cpu.misc_regfile_reads 675842878 # number of misc regfile reads +system.cpu.fp_regfile_writes 50 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965641029 # number of cc regfile reads +system.cpu.cc_regfile_writes 551880821 # number of cc regfile writes +system.cpu.misc_regfile_reads 675853491 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17005493 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964646 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638183172 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17006005 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.526931 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 79063000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964646 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 17005885 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964949 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638186886 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17006397 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.526284 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 78340000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964949 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 392 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 423 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335677307 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335677307 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469397613 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469397613 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168785441 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168785441 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335687679 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335687679 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469400845 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469400845 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168785923 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168785923 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638183054 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638183054 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638183054 # number of overall hits -system.cpu.dcache.overall_hits::total 638183054 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17351867 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17351867 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3800606 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3800606 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638186768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638186768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638186768 # number of overall hits +system.cpu.dcache.overall_hits::total 638186768 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17353625 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17353625 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3800124 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3800124 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21152473 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21152473 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21152475 # number of overall misses -system.cpu.dcache.overall_misses::total 21152475 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 417182903209 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 417182903209 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149917932873 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149917932873 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 358750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 567100836082 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 567100836082 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 567100836082 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 567100836082 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486749480 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486749480 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21153749 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21153749 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21153751 # number of overall misses +system.cpu.dcache.overall_misses::total 21153751 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 417050356298 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 417050356298 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149886013526 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149886013526 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 204500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 566936369824 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 566936369824 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 566936369824 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 566936369824 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486754470 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486754470 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -780,72 +781,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659335527 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659335527 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659335529 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659335529 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035648 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035648 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022022 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022022 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659340517 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659340517 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659340519 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659340519 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035652 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035652 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022019 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022019 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032082 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032082 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032082 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032082 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24042.536933 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24042.536933 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39445.797032 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39445.797032 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 89687.500000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 89687.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26810.143480 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26810.143480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26810.140945 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26810.140945 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20723795 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3315809 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 944207 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67033 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.948360 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49.465323 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.032083 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032083 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032083 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032083 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24032.463321 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24032.463321 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39442.400702 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39442.400702 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51125 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51125 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26800.751480 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26800.751480 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26800.748946 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26800.748946 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20736521 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3309459 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 945396 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67047 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.934217 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49.360285 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4835251 # number of writebacks -system.cpu.dcache.writebacks::total 4835251 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3083373 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3083373 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1063096 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1063096 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 4830628 # number of writebacks +system.cpu.dcache.writebacks::total 4830628 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3084713 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3084713 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1062640 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1062640 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4146469 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4146469 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4146469 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4146469 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268494 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14268494 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737510 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737510 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4147353 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4147353 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4147353 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4147353 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268912 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14268912 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737484 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737484 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17006004 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17006004 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17006005 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17006005 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 329072767985 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 329072767985 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115107857313 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 115107857313 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17006396 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17006396 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17006397 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17006397 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 328919129806 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 328919129806 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115124697729 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 115124697729 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 67750 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 67750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444180625298 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 444180625298 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444180693048 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 444180693048 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444043827535 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 444043827535 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444043895285 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 444043895285 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029314 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029314 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses @@ -856,343 +857,343 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025793 system.cpu.dcache.demand_mshr_miss_rate::total 0.025793 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025793 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23062.894233 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23062.894233 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42048.378750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42048.378750 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23051.451281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23051.451281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42054.929902 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42054.929902 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67750 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67750 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26119.047443 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26119.047443 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26119.049891 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26119.049891 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.401495 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.401495 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.403943 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.403943 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 588 # number of replacements -system.cpu.icache.tags.tagsinuse 446.068543 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656912599 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 610513.567844 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 589 # number of replacements +system.cpu.icache.tags.tagsinuse 446.078018 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656940406 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1077 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 609972.521820 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 446.068543 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.871228 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.871228 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 446.078018 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.871246 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.871246 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313829498 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313829498 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656912599 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656912599 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656912599 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656912599 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656912599 # number of overall hits -system.cpu.icache.overall_hits::total 656912599 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1612 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1612 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1612 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1612 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1612 # number of overall misses -system.cpu.icache.overall_misses::total 1612 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 102924516 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 102924516 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 102924516 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 102924516 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 102924516 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 102924516 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656914211 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656914211 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656914211 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656914211 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656914211 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656914211 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313885139 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313885139 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656940406 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656940406 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656940406 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656940406 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656940406 # number of overall hits +system.cpu.icache.overall_hits::total 656940406 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1625 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1625 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1625 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1625 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1625 # number of overall misses +system.cpu.icache.overall_misses::total 1625 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 105016775 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 105016775 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 105016775 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 105016775 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 105016775 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 105016775 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656942031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656942031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656942031 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656942031 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656942031 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656942031 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63848.955335 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63848.955335 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63848.955335 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63848.955335 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17306 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 93.043011 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 38.375000 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64625.707692 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64625.707692 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64625.707692 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64625.707692 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64625.707692 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64625.707692 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17596 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 547 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 191 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 92.125654 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 60.777778 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 536 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 536 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 536 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76203217 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 76203217 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76203217 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 76203217 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76203217 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 76203217 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 548 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 548 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 548 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 548 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 548 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 548 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76192959 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 76192959 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76192959 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 76192959 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76192959 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 76192959 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70820.833643 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70820.833643 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70745.551532 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70745.551532 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70745.551532 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70745.551532 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70745.551532 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70745.551532 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 10941726 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11630409 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 431114 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 10938258 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11626730 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 430783 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4654951 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 4713207 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16130.406064 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 15325447 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4729134 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.240646 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 29468558500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5233.732135 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.908605 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7574.796716 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3302.968608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.319442 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001154 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.462329 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.201597 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.984522 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 731 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15196 # Occupied blocks per task id +system.cpu.l2cache.prefetcher.pfRemovedFull 3 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 4654278 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 4710195 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16130.419578 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 15323813 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4726123 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.242364 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 29466216500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 5234.041152 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.862974 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7585.301260 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3292.214193 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.319461 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001151 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.462970 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.200941 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.984523 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 739 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15189 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 525 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 201 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2455 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1253 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9206 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1816 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.044617 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927490 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 356943997 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 356943997 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 43 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 11484174 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11484217 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 4835251 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 4835251 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1752141 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1752141 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 43 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13236315 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13236358 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 43 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13236315 # number of overall hits -system.cpu.l2cache.overall_hits::total 13236358 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1033 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 2784280 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2785313 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 985410 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 985410 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1033 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3769690 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3770723 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1033 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3769690 # number of overall misses -system.cpu.l2cache.overall_misses::total 3770723 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 75372729 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 239047213138 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 239122585867 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100142345987 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 100142345987 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 75372729 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 339189559125 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 339264931854 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 75372729 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 339189559125 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 339264931854 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 14268454 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 14269530 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 4835251 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 4835251 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737551 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2737551 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 17006005 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17007081 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17006005 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17007081 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960037 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.195135 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.195193 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359960 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.359960 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960037 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.221668 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.221715 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960037 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.221668 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.221715 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72964.887706 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85856.024946 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 85851.243960 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101625.055547 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101625.055547 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72964.887706 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89978.104068 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89973.443251 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72964.887706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89978.104068 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89973.443251 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 846 # number of cycles access was blocked +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 553 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 181 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 505 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2391 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1230 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9214 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1849 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.045105 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927063 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 356873283 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 356873283 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 41 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 11486555 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 11486596 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 4830628 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 4830628 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1752756 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1752756 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 41 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 13239311 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13239352 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 41 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 13239311 # number of overall hits +system.cpu.l2cache.overall_hits::total 13239352 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1036 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 2782314 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2783350 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 984772 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 984772 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1036 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3767086 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3768122 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1036 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3767086 # number of overall misses +system.cpu.l2cache.overall_misses::total 3768122 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 75378470 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 238879414609 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 238954793079 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100155661373 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 100155661373 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 75378470 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 339035075982 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 339110454452 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 75378470 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 339035075982 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 339110454452 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1077 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 14268869 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 14269946 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 4830628 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 4830628 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737528 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2737528 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1077 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 17006397 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17007474 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1077 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 17006397 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 17007474 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961931 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.194992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.195050 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359730 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.359730 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961931 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.221510 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.221557 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961931 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.221510 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.221557 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72759.140927 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85856.382353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 85851.507385 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101704.416223 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101704.416223 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72759.140927 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89999.292817 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89994.552844 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72759.140927 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89999.292817 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89994.552844 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 211.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1639072 # number of writebacks -system.cpu.l2cache.writebacks::total 1639072 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 36084 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 36084 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3647 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3647 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 39731 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 39731 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 39731 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 39731 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1033 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2748196 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2749229 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993723 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 993723 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981763 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 981763 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1033 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3729959 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3730992 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1033 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3729959 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993723 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4724715 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66585771 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 212846915589 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212913501360 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 71046693133 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 91372170669 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 91372170669 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66585771 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304219086258 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 304285672029 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66585771 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304219086258 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 375332365162 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192606 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192664 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 1637857 # number of writebacks +system.cpu.l2cache.writebacks::total 1637857 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 35708 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 35708 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3730 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3730 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 39438 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 39438 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 39438 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 39438 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1036 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2746606 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2747642 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 992835 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 992835 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981042 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 981042 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1036 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3727648 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3728684 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1036 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3727648 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 992835 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4721519 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66562530 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 212706720467 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212773282997 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 70893901794 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70893901794 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 91380975745 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 91380975745 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66562530 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304087696212 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 304154258742 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66562530 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304087696212 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70893901794 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 375048160536 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192489 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192547 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358628 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358628 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.219379 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358368 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358368 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219191 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.219238 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219191 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.277809 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64458.636012 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77449.685390 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77444.804111 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71495.470199 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93069.478753 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93069.478753 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81556.238134 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79440.212830 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.277614 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64249.546332 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77443.477684 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77438.502904 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71405.522362 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93146.853799 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93146.853799 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64249.546332 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81576.290522 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81571.476355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64249.546332 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81576.290522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79433.792501 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 14269530 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 14269530 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4835251 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1300143 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737551 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737551 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2152 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38847261 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 38849413 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397840384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1397909248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1300143 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23142477 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.056180 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.230269 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 14269946 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 14269946 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4830628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1298291 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737528 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737528 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2154 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38843422 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 38845576 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397569600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1397638528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1298291 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 23136394 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.056115 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.230143 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 21842334 94.38% 94.38% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 1300143 5.62% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 21838103 94.39% 94.39% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 1298291 5.61% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23142477 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15756418748 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23136394 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15749679999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1812271 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1817030 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 26100835834 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 26101043977 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3739202 # Transaction distribution -system.membus.trans_dist::ReadResp 3739202 # Transaction distribution -system.membus.trans_dist::Writeback 1639072 # Transaction distribution -system.membus.trans_dist::ReadExReq 982028 # Transaction distribution -system.membus.trans_dist::ReadExResp 982028 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11081532 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11081532 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407059328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 407059328 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3736842 # Transaction distribution +system.membus.trans_dist::ReadResp 3736842 # Transaction distribution +system.membus.trans_dist::Writeback 1637857 # Transaction distribution +system.membus.trans_dist::ReadExReq 981309 # Transaction distribution +system.membus.trans_dist::ReadExResp 981309 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11074159 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11074159 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406784512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 406784512 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6360302 # Request fanout histogram +system.membus.snoop_fanout::samples 6356008 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6360302 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6356008 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6360302 # Request fanout histogram -system.membus.reqLayer0.occupancy 14493239223 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 6356008 # Request fanout histogram +system.membus.reqLayer0.occupancy 14483850639 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 25671846860 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25655332661 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index a5246083c..93ba57c1e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.832017 # Number of seconds simulated -sim_ticks 832017490000 # Number of ticks simulated -final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 832017490500 # Number of ticks simulated +final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1937211 # Simulator instruction rate (inst/s) -host_op_rate 2087051 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1043527090 # Simulator tick rate (ticks/s) -host_mem_usage 301332 # Number of bytes of host memory used -host_seconds 797.31 # Real time elapsed on the host -sim_insts 1544563041 # Number of instructions simulated -sim_ops 1664032433 # Number of ops (including micro ops) simulated +host_inst_rate 1379227 # Simulator instruction rate (inst/s) +host_op_rate 1485908 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 742955189 # Simulator tick rate (ticks/s) +host_mem_usage 295688 # Number of bytes of host memory used +host_seconds 1119.88 # Real time elapsed on the host +sim_insts 1544563042 # Number of instructions simulated +sim_ops 1664032434 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory -system.physmem.bytes_read::total 7759650027 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6178262356 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6178262356 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6178262360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6178262360 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1544565589 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1544565590 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1999474786 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1999474787 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1900666380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9326306382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1900666379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9326306381 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1664034981 # number of cpu cycles simulated +system.cpu.numCycles 1664034982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1544563041 # Number of instructions committed -system.cpu.committedOps 1664032433 # Number of ops (including micro ops) committed +system.cpu.committedInsts 1544563042 # Number of instructions committed +system.cpu.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330256 # number of times a function call or return occured @@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 2605402942 # nu system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_cc_register_reads 4992096236 # number of times the CC registers were read +system.cpu.num_cc_register_reads 4992096239 # number of times the CC registers were read system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written system.cpu.num_mem_refs 633153380 # number of memory refs system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1664034980.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1664034981.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 213462426 # Number of branches fetched +system.cpu.Branches 213462427 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction +system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction @@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Cl system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1664032480 # Class of executed instruction -system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution -system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution +system.cpu.op_class::total 1664032481 # Class of executed instruction +system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution +system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution system.membus.trans_dist::WriteReq 172586047 # Transaction distribution system.membus.trans_dist::WriteResp 172586047 # Transaction distribution system.membus.trans_dist::SoftPFReq 1 # Transaction distribution @@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp 1 # Tr system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution system.membus.trans_dist::StoreCondReq 61 # Transaction distribution system.membus.trans_dist::StoreCondResp 61 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131180 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 4344121790 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262360 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram +system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram system.membus.snoop_fanout::mean 2.711106 # Request fanout histogram system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::2 627495305 28.89% 28.89% # Request fanout histogram -system.membus.snoop_fanout::3 1544565589 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::3 1544565590 71.11% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 2172060894 # Request fanout histogram +system.membus.snoop_fanout::total 2172060895 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 893b8aa6f..15b1ad4ad 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.363663 # Number of seconds simulated -sim_ticks 2363662966500 # Number of ticks simulated -final_tick 2363662966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2363662967500 # Number of ticks simulated +final_tick 2363662967500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1021163 # Simulator instruction rate (inst/s) -host_op_rate 1100446 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1568591191 # Simulator tick rate (ticks/s) -host_mem_usage 309800 # Number of bytes of host memory used -host_seconds 1506.87 # Real time elapsed on the host -sim_insts 1538759601 # Number of instructions simulated -sim_ops 1658228914 # Number of ops (including micro ops) simulated +host_inst_rate 734295 # Simulator instruction rate (inst/s) +host_op_rate 791306 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1127938114 # Simulator tick rate (ticks/s) +host_mem_usage 305424 # Number of bytes of host memory used +host_seconds 2095.56 # Real time elapsed on the host +sim_insts 1538759602 # Number of instructions simulated +sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory @@ -154,11 +154,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4727325933 # number of cpu cycles simulated +system.cpu.numCycles 4727325935 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1538759601 # Number of instructions committed -system.cpu.committedOps 1658228914 # Number of ops (including micro ops) committed +system.cpu.committedInsts 1538759602 # Number of instructions committed +system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330256 # number of times a function call or return occured @@ -169,18 +169,18 @@ system.cpu.num_int_register_reads 2601860372 # nu system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6356387675 # number of times the CC registers were read +system.cpu.num_cc_register_reads 6356387678 # number of times the CC registers were read system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written system.cpu.num_mem_refs 633153380 # number of memory refs system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4727325932.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4727325934.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 213462426 # Number of branches fetched +system.cpu.Branches 213462427 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction +system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction @@ -213,14 +213,14 @@ system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Cl system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1664032480 # Class of executed instruction +system.cpu.op_class::total 1664032481 # Class of executed instruction system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.733675 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.733673 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164658000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733675 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 25164659000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733673 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -347,9 +347,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 20524.282476 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements system.cpu.icache.tags.tagsinuse 515.012767 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 515.012767 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy @@ -359,14 +359,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 24 system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses -system.cpu.icache.tags.data_accesses 3089131818 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits -system.cpu.icache.overall_hits::total 1544564952 # number of overall hits +system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses +system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1544564953 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1544564953 # number of overall hits +system.cpu.icache.overall_hits::total 1544564953 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses @@ -379,12 +379,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 34207000 system.cpu.icache.demand_miss_latency::total 34207000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 34207000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 34207000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1544565591 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1544565591 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1544565591 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses @@ -431,14 +431,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52115.987461 system.cpu.icache.overall_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1926075 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31008.535045 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31008.535032 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 150067842000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 150067843000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160482 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876098 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498459 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498452 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.477849 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.467728 # Average percentage of cache occupancy |