diff options
| author | Steve Reinhardt <stever@gmail.com> | 2015-03-19 08:41:32 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2015-03-19 08:41:32 -0400 |
| commit | 1483496803f8a8618f62adc5439ce435359b36fe (patch) | |
| tree | a6134ff85d7e6e07e6d34293513f91b16ff94515 /tests/long/se/60.bzip2/ref/arm/linux | |
| parent | f1c3fda965dd4b28ab6b2e99f5f3210fa2089a17 (diff) | |
| download | gem5-1483496803f8a8618f62adc5439ce435359b36fe.tar.xz | |
stats: update Minor stats due to PF bug fix
A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5)
inadvertently fixed a bug in the Minor CPU model which caused it to treat
software prefetches as regular loads. Prior to this changeset, Minor
did an ad-hoc generation of memory commands that left out the PF check;
because it now uses the common code that the other CPU models use,
it generates prefetches properly. These stat changes reflect the fact
that the Minor model now issues SoftPFReqs.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini | 30 | ||||
| -rwxr-xr-x[-rw-r--r--] | tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr | 1 | ||||
| -rwxr-xr-x[-rw-r--r--] | tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout | 14 | ||||
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt | 320 |
4 files changed, 197 insertions, 168 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini index 55081d3ef..634fc5445 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -132,6 +133,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -166,6 +168,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -183,7 +186,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -591,6 +593,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -651,6 +654,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -658,6 +662,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -675,7 +680,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -700,6 +704,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -733,13 +738,16 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -749,14 +757,16 @@ eventq_index=0 type=LiveProcess cmd=bzip2 input.source 1 cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing +drivers= egid=100 env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -786,11 +796,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -821,7 +834,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 @@ -830,6 +843,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr index 5d8946ede..be90b0340 100644..100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr @@ -1,2 +1,3 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout index 903745948..b4e05a41a 100644..100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:57:46 -gem5 started May 7 2014 11:11:49 -gem5 executing on cz3211bhr8 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x1f2b7940 + 0: system.cpu.isa: ISA system set to: 0 0x2c50960 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data @@ -27,4 +25,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1135900642500 because target called exit() +Exiting @ tick 1121241432500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 0b1bb03bc..a72b0bcd6 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.121241 # Nu sim_ticks 1121241432500 # Number of ticks simulated final_tick 1121241432500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243175 # Simulator instruction rate (inst/s) -host_op_rate 261985 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 176527853 # Simulator tick rate (ticks/s) -host_mem_usage 312356 # Number of bytes of host memory used -host_seconds 6351.64 # Real time elapsed on the host +host_inst_rate 170583 # Simulator instruction rate (inst/s) +host_op_rate 183778 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 123831111 # Simulator tick rate (ticks/s) +host_mem_usage 241824 # Number of bytes of host memory used +host_seconds 9054.60 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -234,8 +234,8 @@ system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Wr system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 60985 # Writes before turning the bus around for reads -system.physmem.totQLat 38434565750 # Total ticks spent queuing -system.physmem.totMemAccLat 76957228250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 38434561000 # Total ticks spent queuing +system.physmem.totMemAccLat 76957223500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 10272710000 # Total ticks spent in databus transfers system.physmem.avgQLat 18707.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst @@ -284,13 +284,13 @@ system.physmem_1.memoryStateTime::REF 37440520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 596864300250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 240141363 # Number of BP lookups -system.cpu.branchPred.condPredicted 186745178 # Number of conditional branches predicted +system.cpu.branchPred.lookups 240141357 # Number of BP lookups +system.cpu.branchPred.condPredicted 186745174 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14595264 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132286201 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 132286195 # Number of BTB lookups system.cpu.branchPred.BTBHits 122283419 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.438530 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 92.438534 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15659523 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -416,19 +416,19 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563087 # Number of instructions committed system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed -system.cpu.discardedOps 40063389 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 40063388 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.451856 # CPI: cycles per instruction system.cpu.ipc 0.688774 # IPC: instructions per cycle -system.cpu.tickCycles 1838984641 # Number of cycles that the object actually ticked -system.cpu.idleCycles 403498224 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 1838984644 # Number of cycles that the object actually ticked +system.cpu.idleCycles 403498221 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 9223361 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.642530 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624067003 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4085.642531 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624067002 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9227457 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.631527 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.631526 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9813070000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642530 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642531 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997471 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997471 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -439,62 +439,70 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1276544027 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1276544027 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453735354 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453735354 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 453735352 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453735352 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170331527 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 170331527 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624066881 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624066881 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624066881 # number of overall hits -system.cpu.dcache.overall_hits::total 624066881 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7336762 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7336762 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 624066879 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624066879 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624066880 # number of overall hits +system.cpu.dcache.overall_hits::total 624066880 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7336761 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7336761 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2254520 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2254520 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9591282 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9591282 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9591282 # number of overall misses -system.cpu.dcache.overall_misses::total 9591282 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442349996 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 192442349996 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711138250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109711138250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 302153488246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 302153488246 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 302153488246 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 302153488246 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461072116 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461072116 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 9591281 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9591281 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9591283 # number of overall misses +system.cpu.dcache.overall_misses::total 9591283 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442274246 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 192442274246 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711140250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109711140250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 302153414496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 302153414496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 302153414496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 302153414496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461072113 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461072113 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633658163 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633658163 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 633658160 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633658160 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 633658163 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 633658163 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015912 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015912 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013063 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013063 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.015136 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015136 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015136 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015136 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.874977 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.874977 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48662.747835 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48662.747835 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31502.930291 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31502.930291 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.868227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.868227 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48662.748723 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48662.748723 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31502.925886 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31502.925886 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31502.919317 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31502.919317 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,44 +521,52 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 363825 system.cpu.dcache.demand_mshr_hits::total 363825 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 363825 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 363825 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336554 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7336554 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336553 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7336553 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890903 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1890903 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9227457 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9227457 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9227456 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9227456 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9227457 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9227457 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181020888504 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 181020888504 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83976849000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83976849000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264997737504 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 264997737504 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264997737504 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 264997737504 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181020814754 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 181020814754 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83976850000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83976850000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 73750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 73750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264997664754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 264997664754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264997738504 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 264997738504 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015912 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015912 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24673.830317 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24673.830317 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44410.976660 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44410.976660 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24673.823627 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24673.823627 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44410.977189 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44410.977189 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73750 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73750 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28718.388335 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28718.388335 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28718.393215 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28718.393215 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 32 # number of replacements system.cpu.icache.tags.tagsinuse 661.433391 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466139352 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 466139348 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 566390.464156 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 566390.459295 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 661.433391 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.322966 # Average percentage of cache occupancy @@ -560,44 +576,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 32 system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932281173 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932281173 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 466139352 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466139352 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466139352 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466139352 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466139352 # number of overall hits -system.cpu.icache.overall_hits::total 466139352 # number of overall hits +system.cpu.icache.tags.tag_accesses 932281165 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932281165 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 466139348 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466139348 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466139348 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466139348 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466139348 # number of overall hits +system.cpu.icache.overall_hits::total 466139348 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses system.cpu.icache.overall_misses::total 823 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 63715999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 63715999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 63715999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 63715999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 63715999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 63715999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466140175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466140175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466140175 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466140175 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466140175 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466140175 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 63711749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 63711749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 63711749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 63711749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 63711749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 63711749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 466140171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466140171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466140171 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466140171 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466140171 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466140171 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77419.196841 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77419.196841 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77419.196841 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77419.196841 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77414.032807 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77414.032807 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77414.032807 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77414.032807 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77414.032807 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77414.032807 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -612,24 +628,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 823 system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62148501 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 62148501 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62148501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 62148501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62148501 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 62148501 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62143751 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 62143751 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62143751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 62143751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62143751 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 62143751 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75514.582017 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75514.582017 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75508.810450 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75508.810450 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75508.810450 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75508.810450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75508.810450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75508.810450 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 2023178 # number of replacements system.cpu.l2cache.tags.tagsinuse 31261.935104 # Cycle average of tags in use @@ -677,17 +693,17 @@ system.cpu.l2cache.demand_misses::total 2055888 # nu system.cpu.l2cache.overall_misses::cpu.inst 791 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2055097 # number of overall misses system.cpu.l2cache.overall_misses::total 2055888 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60988000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60983250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109821544000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 109882532000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70568051000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 70568051000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 60988000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 180389595000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 180450583000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 60988000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 180389595000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 180450583000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 109882527250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70568052000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 70568052000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 60983250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 180389596000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 180450579250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 60983250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 180389596000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 180450579250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 823 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7336554 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7337377 # number of ReadReq accesses(hits+misses) @@ -712,17 +728,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.222781 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961118 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.222715 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.222781 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77102.402023 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77096.396966 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87510.692856 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 87504.136601 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88193.858129 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88193.858129 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87772.574673 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87772.574673 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 87504.132819 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88193.859378 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88193.859378 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77096.396966 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87776.682074 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87772.572849 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77096.396966 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87776.682074 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87772.572849 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -753,17 +769,17 @@ system.cpu.l2cache.demand_mshr_misses::total 2055883 system.cpu.l2cache.overall_mshr_misses::cpu.inst 790 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2055093 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2055883 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51087500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51082250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93955002000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006089500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459125500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459125500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51087500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414127500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 154465215000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51087500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414127500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 154465215000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006084250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459126500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459126500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51082250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414128500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 154465210750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51082250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414128500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 154465210750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171054 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171142 # mshr miss rate for ReadReq accesses @@ -775,17 +791,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.222781 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.222781 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64667.721519 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64661.075949 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74867.764828 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.347847 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.022721 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.022721 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.343666 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.023971 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.023971 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64661.075949 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294760 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.269135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64661.075949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294760 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.269135 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7337377 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7337377 # Transaction distribution @@ -814,7 +830,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 3 # system.cpu.toL2Bus.snoop_fanout::total 12929320 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10165700000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1400999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1401249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 14190167496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) @@ -840,7 +856,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 3102414 # Request fanout histogram system.membus.reqLayer0.occupancy 7944829000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 11243795500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11243795750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |