diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
| commit | f2e2410a505ef48516f121ce1b2232ba7aa389af (patch) | |
| tree | dbe4c8482b37e854302410318fc474f507310724 /tests/long/se/60.bzip2/ref/arm/linux | |
| parent | 184c6d7ebd7faa0869f294526a54a239a216b7c8 (diff) | |
| download | gem5-f2e2410a505ef48516f121ce1b2232ba7aa389af.tar.xz | |
stats: Get all stats updated to reflect current behaviour
Line everything up again.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt | 974 | ||||
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 1746 |
2 files changed, 1361 insertions, 1359 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index c13f099b6..fe9262960 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.150228 # Number of seconds simulated -sim_ticks 1150227786500 # Number of ticks simulated -final_tick 1150227786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.150356 # Number of seconds simulated +sim_ticks 1150356296500 # Number of ticks simulated +final_tick 1150356296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 394229 # Simulator instruction rate (inst/s) -host_op_rate 424722 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 293579950 # Simulator tick rate (ticks/s) -host_mem_usage 273524 # Number of bytes of host memory used -host_seconds 3917.94 # Real time elapsed on the host +host_inst_rate 374766 # Simulator instruction rate (inst/s) +host_op_rate 403753 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 279117141 # Simulator tick rate (ticks/s) +host_mem_usage 273688 # Number of bytes of host memory used +host_seconds 4121.41 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132094848 # Number of bytes read from this memory -system.physmem.bytes_read::total 132145088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132097728 # Number of bytes read from this memory +system.physmem.bytes_read::total 132147968 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67849984 # Number of bytes written to this memory -system.physmem.bytes_written::total 67849984 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67851072 # Number of bytes written to this memory +system.physmem.bytes_written::total 67851072 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2063982 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2064767 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1060156 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1060156 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 43678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 114842338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 114886016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 43678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 43678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 58988302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 58988302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 58988302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 43678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 114842338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 173874318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2064767 # Number of read requests accepted -system.physmem.writeReqs 1060156 # Number of write requests accepted -system.physmem.readBursts 2064767 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1060156 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 132061888 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83200 # Total number of bytes read from write queue -system.physmem.bytesWritten 67848256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132145088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67849984 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1300 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 2064027 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2064812 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1060173 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1060173 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 43673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 114832012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 114875685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 43673 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 43673 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 58982658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 58982658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 58982658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 43673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 114832012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 173858343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2064812 # Number of read requests accepted +system.physmem.writeReqs 1060173 # Number of write requests accepted +system.physmem.readBursts 2064812 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1060173 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 132064448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83520 # Total number of bytes read from write queue +system.physmem.bytesWritten 67849344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132147968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67851072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1305 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 128524 # Per bank write bursts -system.physmem.perBankRdBursts::1 125801 # Per bank write bursts -system.physmem.perBankRdBursts::2 122666 # Per bank write bursts -system.physmem.perBankRdBursts::3 124575 # Per bank write bursts -system.physmem.perBankRdBursts::4 123572 # Per bank write bursts -system.physmem.perBankRdBursts::5 123680 # Per bank write bursts -system.physmem.perBankRdBursts::6 124357 # Per bank write bursts +system.physmem.perBankRdBursts::0 128530 # Per bank write bursts +system.physmem.perBankRdBursts::1 125798 # Per bank write bursts +system.physmem.perBankRdBursts::2 122667 # Per bank write bursts +system.physmem.perBankRdBursts::3 124564 # Per bank write bursts +system.physmem.perBankRdBursts::4 123583 # Per bank write bursts +system.physmem.perBankRdBursts::5 123689 # Per bank write bursts +system.physmem.perBankRdBursts::6 124368 # Per bank write bursts system.physmem.perBankRdBursts::7 124965 # Per bank write bursts -system.physmem.perBankRdBursts::8 132488 # Per bank write bursts -system.physmem.perBankRdBursts::9 134781 # Per bank write bursts -system.physmem.perBankRdBursts::10 133246 # Per bank write bursts +system.physmem.perBankRdBursts::8 132503 # Per bank write bursts +system.physmem.perBankRdBursts::9 134776 # Per bank write bursts +system.physmem.perBankRdBursts::10 133237 # Per bank write bursts system.physmem.perBankRdBursts::11 134508 # Per bank write bursts -system.physmem.perBankRdBursts::12 134523 # Per bank write bursts -system.physmem.perBankRdBursts::13 134597 # Per bank write bursts -system.physmem.perBankRdBursts::14 130537 # Per bank write bursts -system.physmem.perBankRdBursts::15 130647 # Per bank write bursts -system.physmem.perBankWrBursts::0 66781 # Per bank write bursts -system.physmem.perBankWrBursts::1 64940 # Per bank write bursts -system.physmem.perBankWrBursts::2 63173 # Per bank write bursts -system.physmem.perBankWrBursts::3 63584 # Per bank write bursts -system.physmem.perBankWrBursts::4 63558 # Per bank write bursts -system.physmem.perBankWrBursts::5 63644 # Per bank write bursts -system.physmem.perBankWrBursts::6 65047 # Per bank write bursts -system.physmem.perBankWrBursts::7 66059 # Per bank write bursts -system.physmem.perBankWrBursts::8 67975 # Per bank write bursts -system.physmem.perBankWrBursts::9 68435 # Per bank write bursts -system.physmem.perBankWrBursts::10 68155 # Per bank write bursts -system.physmem.perBankWrBursts::11 68585 # Per bank write bursts -system.physmem.perBankWrBursts::12 68036 # Per bank write bursts -system.physmem.perBankWrBursts::13 68532 # Per bank write bursts -system.physmem.perBankWrBursts::14 67159 # Per bank write bursts +system.physmem.perBankRdBursts::12 134521 # Per bank write bursts +system.physmem.perBankRdBursts::13 134606 # Per bank write bursts +system.physmem.perBankRdBursts::14 130538 # Per bank write bursts +system.physmem.perBankRdBursts::15 130654 # Per bank write bursts +system.physmem.perBankWrBursts::0 66782 # Per bank write bursts +system.physmem.perBankWrBursts::1 64941 # Per bank write bursts +system.physmem.perBankWrBursts::2 63176 # Per bank write bursts +system.physmem.perBankWrBursts::3 63581 # Per bank write bursts +system.physmem.perBankWrBursts::4 63564 # Per bank write bursts +system.physmem.perBankWrBursts::5 63647 # Per bank write bursts +system.physmem.perBankWrBursts::6 65050 # Per bank write bursts +system.physmem.perBankWrBursts::7 66062 # Per bank write bursts +system.physmem.perBankWrBursts::8 67977 # Per bank write bursts +system.physmem.perBankWrBursts::9 68434 # Per bank write bursts +system.physmem.perBankWrBursts::10 68153 # Per bank write bursts +system.physmem.perBankWrBursts::11 68587 # Per bank write bursts +system.physmem.perBankWrBursts::12 68034 # Per bank write bursts +system.physmem.perBankWrBursts::13 68534 # Per bank write bursts +system.physmem.perBankWrBursts::14 67158 # Per bank write bursts system.physmem.perBankWrBursts::15 66466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1150227685500 # Total gap between requests +system.physmem.totGap 1150356195500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2064767 # Read request sizes (log2) +system.physmem.readPktSize::6 2064812 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1060156 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1919511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 143942 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1060173 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1919552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 143941 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 62501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 62688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 62496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62667 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 62593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 62501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 62570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 62618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 62416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 62637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,122 +194,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1927678 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.704158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.827351 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.878363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1497959 77.71% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 310183 16.09% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52221 2.71% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20819 1.08% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1927714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.704114 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.833686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.867792 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1497696 77.69% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 310699 16.12% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52184 2.71% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20631 1.07% 97.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 13074 0.68% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7800 0.40% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5214 0.27% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5117 0.27% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15291 0.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1927678 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 62183 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.137240 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.854238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 150.737609 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 62144 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::640-767 7807 0.40% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5185 0.27% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5186 0.27% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15252 0.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1927714 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62200 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.128826 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.842942 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 148.982645 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 62161 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 62183 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 62183 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.048534 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.017369 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.031425 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29894 48.07% 48.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1086 1.75% 49.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 29528 47.49% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1644 2.64% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 28 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 62183 # Writes before turning the bus around for reads -system.physmem.totQLat 59946131250 # Total ticks spent queuing -system.physmem.totMemAccLat 98636137500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10317335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29051.17 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 62200 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62200 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.044148 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.013066 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.029999 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29988 48.21% 48.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1141 1.83% 50.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29436 47.32% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1609 2.59% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 24 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 62200 # Writes before turning the bus around for reads +system.physmem.totQLat 60011294750 # Total ticks spent queuing +system.physmem.totMemAccLat 98702051000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10317535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29082.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47801.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 114.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 58.99 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 114.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 58.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47832.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 114.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 58.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 114.88 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 58.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.36 # Data bus utilization in percentage system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing -system.physmem.readRowHits 775435 # Number of row buffer hits during reads -system.physmem.writeRowHits 420473 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.66 # Row buffer hit rate for writes -system.physmem.avgGap 368081.93 # Average gap between requests +system.physmem.avgWrQLen 24.14 # Average write queue length when enqueuing +system.physmem.readRowHits 775182 # Number of row buffer hits during reads +system.physmem.writeRowHits 420747 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.69 # Row buffer hit rate for writes +system.physmem.avgGap 368115.75 # Average gap between requests system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6703938780 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3563201400 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7126719600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2697622920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 71587735440.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47610368340 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2598027360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 242891748180 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 71936235360 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 82347779655 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 539087705175 # Total energy per rank (pJ) -system.physmem_0.averagePower 468.679083 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1039000185750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3501543500 # Time in different power states -system.physmem_0.memoryStateTime::REF 30348316000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 319007908000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 187335147250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77377438000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 532657433750 # Time in different power states -system.physmem_1.actEnergy 7059753540 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3752336610 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7606434780 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 6705024060 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3563778240 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7126890960 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2697711660 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 71598184320.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47589199680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2602904160 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 242927855970 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 71960703840 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 82354339920 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 539151608970 # Total energy per rank (pJ) +system.physmem_0.averagePower 468.682274 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1039160467250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3513710000 # Time in different power states +system.physmem_0.memoryStateTime::REF 30352766000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 319025802500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 187397997250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77329050000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 532736970750 # Time in different power states +system.physmem_1.actEnergy 7058925300 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3751896390 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7606549020 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 71062832880.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47583848520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2430369600 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 248599905450 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 68453747040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 80907358950 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 540315522360 # Total energy per rank (pJ) -system.physmem_1.averagePower 469.746535 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1039499383250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3059154750 # Time in different power states -system.physmem_1.memoryStateTime::REF 30118266000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 316057409750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 178263690250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77550921750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 545178344000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240019900 # Number of BP lookups -system.cpu.branchPred.condPredicted 186610401 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131646658 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122324616 # Number of BTB hits +system.physmem_1.refreshEnergy 71153184960.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47703954360 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2452947360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 248582355720 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 68636874240 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 80784488595 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 540590019675 # Total energy per rank (pJ) +system.physmem_1.averagePower 469.932679 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1039304472000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3115835000 # Time in different power states +system.physmem_1.memoryStateTime::REF 30156708000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 315425606000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 178743425250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77779220750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 545135501500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240030332 # Number of BP lookups +system.cpu.branchPred.condPredicted 186613747 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14536765 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132238924 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122337864 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.918892 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.512749 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15662658 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 538 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 232 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 306 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -339,7 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -369,7 +369,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,7 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -430,16 +430,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2300455573 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2300712593 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41363694 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41389188 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.489389 # CPI: cycles per instruction -system.cpu.ipc 0.671416 # IPC: instructions per cycle +system.cpu.cpi 1.489556 # CPI: cycles per instruction +system.cpu.ipc 0.671341 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -479,16 +479,16 @@ system.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1845015660 # Number of cycles that the object actually ticked -system.cpu.idleCycles 455439913 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9220107 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.805308 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624493167 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9224203 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.701585 # Average number of references to valid blocks. +system.cpu.tickCycles 1845105384 # Number of cycles that the object actually ticked +system.cpu.idleCycles 455607209 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9220185 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.806447 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624504262 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9224281 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.702216 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805308 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.806447 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -497,43 +497,43 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277391153 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277391153 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454163886 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454163886 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170329158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170329158 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277413521 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277413521 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454174952 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454174952 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170329187 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170329187 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624493044 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624493044 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624493045 # number of overall hits -system.cpu.dcache.overall_hits::total 624493045 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7333417 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7333417 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2256889 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2256889 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624504139 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624504139 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624504140 # number of overall hits +system.cpu.dcache.overall_hits::total 624504140 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7333496 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7333496 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2256860 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2256860 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9590306 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9590306 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9590308 # number of overall misses -system.cpu.dcache.overall_misses::total 9590308 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 208196327000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 208196327000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 119903341000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 119903341000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 328099668000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 328099668000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 328099668000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 328099668000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461497303 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461497303 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9590356 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9590356 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9590358 # number of overall misses +system.cpu.dcache.overall_misses::total 9590358 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 208281810000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 208281810000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119887020500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119887020500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 328168830500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 328168830500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 328168830500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 328168830500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461508448 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461508448 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -542,64 +542,64 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634083350 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634083350 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634083353 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634083353 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 634094495 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634094495 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634094498 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634094498 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013077 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015125 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015125 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015125 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28390.084322 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28390.084322 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.708540 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.708540 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.595334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34211.595334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.588199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34211.588199 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.015124 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015124 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015124 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015124 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28401.435005 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28401.435005 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53121.159709 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53121.159709 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34218.628641 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34218.628641 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34218.621505 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34218.621505 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3670055 # number of writebacks -system.cpu.dcache.writebacks::total 3670055 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3670078 # number of writebacks +system.cpu.dcache.writebacks::total 3670078 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366055 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 366055 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 366104 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 366104 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 366104 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 366104 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333368 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7333368 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890834 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890834 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366027 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 366027 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366076 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366076 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366076 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366076 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333447 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333447 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890833 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890833 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9224202 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9224202 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9224203 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9224203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200858538000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 200858538000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92467008500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92467008500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9224280 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9224280 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9224281 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9224281 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200943921500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 200943921500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92449770000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92449770000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293325546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 293325546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293325627500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 293325627500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293393691500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 293393691500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293393772500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 293393772500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -610,70 +610,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.671158 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.671158 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.763807 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.763807 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27401.019125 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27401.019125 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48893.672789 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48893.672789 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.558000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.558000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.563334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.563334 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31806.676673 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31806.676673 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31806.682006 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31806.682006 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 33 # number of replacements -system.cpu.icache.tags.tagsinuse 660.477823 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466274758 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 660.481453 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466324528 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567244.231144 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567304.778589 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.477823 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322499 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 660.481453 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322501 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322501 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932551982 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932551982 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 466274758 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466274758 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466274758 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466274758 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466274758 # number of overall hits -system.cpu.icache.overall_hits::total 466274758 # number of overall hits +system.cpu.icache.tags.tag_accesses 932651522 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932651522 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 466324528 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466324528 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466324528 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466324528 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466324528 # number of overall hits +system.cpu.icache.overall_hits::total 466324528 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses system.cpu.icache.overall_misses::total 822 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 74803000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 74803000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 74803000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 74803000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 74803000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 74803000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466275580 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466275580 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466275580 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466275580 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466275580 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466275580 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 75338000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 75338000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 75338000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 75338000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 75338000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 75338000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 466325350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466325350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466325350 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466325350 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466325350 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466325350 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91001.216545 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 91001.216545 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 91001.216545 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 91001.216545 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91652.068127 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 91652.068127 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 91652.068127 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 91652.068127 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -688,38 +688,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 822 system.cpu.icache.demand_mshr_misses::total 822 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 822 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 822 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73981000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 73981000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73981000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 73981000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73981000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 73981000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 74516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 74516000 # 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number of writebacks +system.cpu.l2cache.writebacks::total 1060173 # number of writebacks +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 7 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 7 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 215 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 215 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812323 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 812323 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812338 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 812338 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 785 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 785 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251659 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251659 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251689 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251689 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2063982 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2064767 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2064027 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2064812 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2063982 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2064767 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159698500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159698500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64478000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64478000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113480200500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113480200500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64478000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183639899000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 183704377000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64478000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183639899000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 183704377000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 2064027 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2064812 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70142301500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70142301500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65013000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65013000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113564745500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113564745500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65013000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183707047000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 183772060000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65013000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183707047000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 183772060000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429619 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429619 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170682 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170682 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.223822 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.223825 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.223822 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86369.213355 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86369.213355 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.831363 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.831363 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18445165 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220152 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.223825 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86346.202566 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86346.202566 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82819.108280 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82819.108280 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90729.203101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90729.203101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18445321 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220230 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7334191 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4730211 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7334270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4730251 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6522313 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890833 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890833 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333448 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668513 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27670190 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668747 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27670424 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825232512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 825287232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2032334 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 67849984 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11257359 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825238976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 825293696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2032379 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 67851072 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11257482 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000271 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.016506 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11254309 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11254432 99.97% 99.97% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 3044 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11257359 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12892670500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11257482 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12892771500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13836307494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13836424993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 4095872 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2031262 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 4095962 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2031307 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1252444 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1060156 # Transaction distribution -system.membus.trans_dist::CleanEvict 970949 # Transaction distribution -system.membus.trans_dist::ReadExReq 812323 # Transaction distribution -system.membus.trans_dist::ReadExResp 812323 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1252444 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160639 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6160639 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 199995072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1252474 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1060173 # Transaction distribution +system.membus.trans_dist::CleanEvict 970977 # Transaction distribution +system.membus.trans_dist::ReadExReq 812338 # Transaction distribution +system.membus.trans_dist::ReadExResp 812338 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1252474 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160774 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6160774 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199999040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 199999040 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2064767 # Request fanout histogram +system.membus.snoop_fanout::samples 2064812 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2064767 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2064812 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2064767 # Request fanout histogram -system.membus.reqLayer0.occupancy 8804919500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2064812 # Request fanout histogram +system.membus.reqLayer0.occupancy 8805297000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11285149250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11285202500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 413bb751f..2fc5a813e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.787540 # Number of seconds simulated -sim_ticks 787540181500 # Number of ticks simulated -final_tick 787540181500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.787836 # Number of seconds simulated +sim_ticks 787835965500 # Number of ticks simulated +final_tick 787835965500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 265954 # Simulator instruction rate (inst/s) -host_op_rate 286525 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 135604104 # Simulator tick rate (ticks/s) -host_mem_usage 328428 # Number of bytes of host memory used -host_seconds 5807.64 # Real time elapsed on the host +host_inst_rate 263266 # Simulator instruction rate (inst/s) +host_op_rate 283629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 134283963 # Simulator tick rate (ticks/s) +host_mem_usage 329624 # Number of bytes of host memory used +host_seconds 5866.94 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 236130432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63765312 # Number of bytes read from this memory -system.physmem.bytes_read::total 299960832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104600704 # Number of bytes written to this memory -system.physmem.bytes_written::total 104600704 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3689538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 996333 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4686888 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1634386 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1634386 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 82647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 299832869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 80967693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380883210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 82647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 82647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 132819514 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 132819514 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 132819514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 82647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 299832869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 80967693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 513702723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4686888 # Number of read requests accepted -system.physmem.writeReqs 1634386 # Number of write requests accepted -system.physmem.readBursts 4686888 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1634386 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 299458048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 502784 # Total number of bytes read from write queue -system.physmem.bytesWritten 104597376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299960832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104600704 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7856 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 236015808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63804544 # Number of bytes read from this memory +system.physmem.bytes_read::total 299885696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104593152 # Number of bytes written to this memory +system.physmem.bytes_written::total 104593152 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1021 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3687747 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 996946 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4685714 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1634268 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1634268 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 82941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 299574808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 80987092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 380644841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 82941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 82941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 132760062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 132760062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 132760062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 82941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 299574808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 80987092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 513404904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4685714 # Number of read requests accepted +system.physmem.writeReqs 1634268 # Number of write requests accepted +system.physmem.readBursts 4685714 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1634268 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 299374336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 511360 # Total number of bytes read from write queue +system.physmem.bytesWritten 104589440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299885696 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104593152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7990 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 28 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 302302 # Per bank write bursts -system.physmem.perBankRdBursts::1 301952 # Per bank write bursts -system.physmem.perBankRdBursts::2 285792 # Per bank write bursts -system.physmem.perBankRdBursts::3 288384 # Per bank write bursts -system.physmem.perBankRdBursts::4 288196 # Per bank write bursts -system.physmem.perBankRdBursts::5 285903 # Per bank write bursts -system.physmem.perBankRdBursts::6 281854 # Per bank write bursts -system.physmem.perBankRdBursts::7 277846 # Per bank write bursts -system.physmem.perBankRdBursts::8 294690 # Per bank write bursts -system.physmem.perBankRdBursts::9 300083 # Per bank write bursts -system.physmem.perBankRdBursts::10 291836 # Per bank write bursts -system.physmem.perBankRdBursts::11 298648 # Per bank write bursts -system.physmem.perBankRdBursts::12 299589 # Per bank write bursts -system.physmem.perBankRdBursts::13 298339 # Per bank write bursts -system.physmem.perBankRdBursts::14 293778 # Per bank write bursts -system.physmem.perBankRdBursts::15 289840 # Per bank write bursts -system.physmem.perBankWrBursts::0 103932 # Per bank write bursts -system.physmem.perBankWrBursts::1 101641 # Per bank write bursts -system.physmem.perBankWrBursts::2 99135 # Per bank write bursts -system.physmem.perBankWrBursts::3 99721 # Per bank write bursts -system.physmem.perBankWrBursts::4 98850 # Per bank write bursts -system.physmem.perBankWrBursts::5 98703 # Per bank write bursts -system.physmem.perBankWrBursts::6 102612 # Per bank write bursts -system.physmem.perBankWrBursts::7 104045 # Per bank write bursts -system.physmem.perBankWrBursts::8 105476 # Per bank write bursts -system.physmem.perBankWrBursts::9 104249 # Per bank write bursts -system.physmem.perBankWrBursts::10 101862 # Per bank write bursts -system.physmem.perBankWrBursts::11 102612 # Per bank write bursts -system.physmem.perBankWrBursts::12 102593 # Per bank write bursts -system.physmem.perBankWrBursts::13 102283 # Per bank write bursts -system.physmem.perBankWrBursts::14 104155 # Per bank write bursts -system.physmem.perBankWrBursts::15 102465 # Per bank write bursts +system.physmem.perBankRdBursts::0 301500 # Per bank write bursts +system.physmem.perBankRdBursts::1 301960 # Per bank write bursts +system.physmem.perBankRdBursts::2 285447 # Per bank write bursts +system.physmem.perBankRdBursts::3 288137 # Per bank write bursts +system.physmem.perBankRdBursts::4 288946 # Per bank write bursts +system.physmem.perBankRdBursts::5 285921 # Per bank write bursts +system.physmem.perBankRdBursts::6 281288 # Per bank write bursts +system.physmem.perBankRdBursts::7 278400 # Per bank write bursts +system.physmem.perBankRdBursts::8 294011 # Per bank write bursts +system.physmem.perBankRdBursts::9 300115 # Per bank write bursts +system.physmem.perBankRdBursts::10 292046 # Per bank write bursts +system.physmem.perBankRdBursts::11 297684 # Per bank write bursts +system.physmem.perBankRdBursts::12 299531 # Per bank write bursts +system.physmem.perBankRdBursts::13 298464 # Per bank write bursts +system.physmem.perBankRdBursts::14 294115 # Per bank write bursts +system.physmem.perBankRdBursts::15 290159 # Per bank write bursts +system.physmem.perBankWrBursts::0 103775 # Per bank write bursts +system.physmem.perBankWrBursts::1 101738 # Per bank write bursts +system.physmem.perBankWrBursts::2 99347 # Per bank write bursts +system.physmem.perBankWrBursts::3 99748 # Per bank write bursts +system.physmem.perBankWrBursts::4 99113 # Per bank write bursts +system.physmem.perBankWrBursts::5 98946 # Per bank write bursts +system.physmem.perBankWrBursts::6 102275 # Per bank write bursts +system.physmem.perBankWrBursts::7 103989 # Per bank write bursts +system.physmem.perBankWrBursts::8 105110 # Per bank write bursts +system.physmem.perBankWrBursts::9 104316 # Per bank write bursts +system.physmem.perBankWrBursts::10 101973 # Per bank write bursts +system.physmem.perBankWrBursts::11 102390 # Per bank write bursts +system.physmem.perBankWrBursts::12 102662 # Per bank write bursts +system.physmem.perBankWrBursts::13 102242 # Per bank write bursts +system.physmem.perBankWrBursts::14 104082 # Per bank write bursts +system.physmem.perBankWrBursts::15 102504 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 787540140500 # Total gap between requests +system.physmem.totGap 787835924500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4686888 # Read request sizes (log2) +system.physmem.readPktSize::6 4685714 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1634386 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2728191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1051856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 328268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 233236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 157524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 89904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 39917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1634268 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2727826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1050681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 326941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 233426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 158423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 90275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 39813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -149,42 +149,42 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 105756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 109650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 110259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 109107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 24253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 72860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 104977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 109635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 109963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 109142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see @@ -198,132 +198,134 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4260550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.836056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.812158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.756680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3400540 79.81% 79.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 663329 15.57% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94665 2.22% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34624 0.81% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22478 0.53% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12365 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7339 0.17% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5272 0.12% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19938 0.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4260550 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97975 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.757050 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.440701 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95549 97.52% 97.52% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1198 1.22% 98.75% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 700 0.71% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 381 0.39% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 109 0.11% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 28 0.03% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3328-3583 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4259361 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.841028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.814946 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.698820 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3400000 79.82% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 662329 15.55% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94740 2.22% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35136 0.82% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22172 0.52% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12513 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7488 0.18% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5149 0.12% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19834 0.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4259361 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98005 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.729004 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.044358 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95588 97.53% 97.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1180 1.20% 98.74% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 706 0.72% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 397 0.41% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 101 0.10% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97975 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97975 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.681133 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.640632 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.211305 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 70258 71.71% 71.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1952 1.99% 73.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 17579 17.94% 91.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5262 5.37% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1746 1.78% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 657 0.67% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 283 0.29% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 119 0.12% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 69 0.07% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 29 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 11 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97975 # Writes before turning the bus around for reads -system.physmem.totQLat 162188930459 # Total ticks spent queuing -system.physmem.totMemAccLat 249920780459 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23395160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34662.92 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 98005 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98005 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.674761 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.634865 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.202481 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 70360 71.79% 71.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1982 2.02% 73.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 17660 18.02% 91.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5209 5.32% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1729 1.76% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 596 0.61% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 225 0.23% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 114 0.12% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 71 0.07% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 31 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 17 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 98005 # Writes before turning the bus around for reads +system.physmem.totQLat 162836208305 # Total ticks spent queuing +system.physmem.totMemAccLat 250543533305 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23388620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34810.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53412.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 132.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 380.88 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 132.82 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53560.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 132.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 380.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 132.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.01 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.99 # Average write queue length when enqueuing -system.physmem.readRowHits 1713351 # Number of row buffer hits during reads -system.physmem.writeRowHits 339452 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 20.77 # Row buffer hit rate for writes -system.physmem.avgGap 124585.67 # Average gap between requests +system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing +system.physmem.readRowHits 1712017 # Number of row buffer hits during reads +system.physmem.writeRowHits 340548 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 20.84 # Row buffer hit rate for writes +system.physmem.avgGap 124657.94 # Average gap between requests system.physmem.pageHitRate 32.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15118214580 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8035491255 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16509315060 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4221095580 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 59433229440.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64449448560 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1619596800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 222781261830 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 36127794240 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 16128721335 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 444435904680 # Total energy per rank (pJ) -system.physmem_0.averagePower 564.334256 # Core power per rank (mW) -system.physmem_0.totalIdleTime 641954026654 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1425644900 # Time in different power states -system.physmem_0.memoryStateTime::REF 25162536000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 59321643250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 94080310817 # Time in different power states -system.physmem_0.memoryStateTime::ACT 118997964696 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 488552081837 # Time in different power states -system.physmem_1.actEnergy 15302205240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8133295995 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 16898973420 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4310127900 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 58889273040.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 64896379290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1612760640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 219232237770 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 35640720960 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18160779360 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 443087552175 # Total energy per rank (pJ) -system.physmem_1.averagePower 562.622143 # Core power per rank (mW) -system.physmem_1.totalIdleTime 640996653350 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1453270191 # Time in different power states -system.physmem_1.memoryStateTime::REF 24933432000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67412776000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 92813399032 # Time in different power states -system.physmem_1.memoryStateTime::ACT 120155386459 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 480771917818 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 286296319 # Number of BP lookups -system.cpu.branchPred.condPredicted 223413056 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14631953 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158681776 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150365310 # Number of BTB hits +system.physmem_0.actEnergy 15118935720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8035889730 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16504816860 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4222619820 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 59457815040.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64415436660 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1624122240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 222796740750 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 36224267040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 16152645360 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 444563646270 # Total energy per rank (pJ) +system.physmem_0.averagePower 564.284526 # Core power per rank (mW) +system.physmem_0.totalIdleTime 642315388170 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1436139102 # Time in different power states +system.physmem_0.memoryStateTime::REF 25173062000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 59398115500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 94331998561 # Time in different power states +system.physmem_0.memoryStateTime::ACT 118911366978 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 488585283359 # Time in different power states +system.physmem_1.actEnergy 15292958940 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8128385265 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 16894132500 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4307956380 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 58918161120.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 64834688190 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1616111040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 219342669570 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 35641510560 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18222503400 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 443208649005 # Total energy per rank (pJ) +system.physmem_1.averagePower 562.564626 # Core power per rank (mW) +system.physmem_1.totalIdleTime 641423107931 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1455389769 # Time in different power states +system.physmem_1.memoryStateTime::REF 24945910000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 67593570250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 92814429154 # Time in different power states +system.physmem_1.memoryStateTime::ACT 120009883050 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 481016783277 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 286288991 # Number of BP lookups +system.cpu.branchPred.condPredicted 223379889 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14638803 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157014468 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150316303 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.759029 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16643535 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3038 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1928 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1110 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 135 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.734046 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16636731 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3547 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2042 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1505 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -353,7 +355,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,7 +385,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -413,7 +415,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -444,133 +446,133 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1575080364 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1575671932 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13929690 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067600144 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286296319 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 167010773 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1546402654 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29288795 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 390 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 943 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656982335 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 916 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1574978074 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.406414 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.233446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13942337 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067450540 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286288991 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166955076 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1546978368 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29302455 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 311 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1029 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656906223 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 925 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1575573272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.405744 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.233501 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 492512848 31.27% 31.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465448024 29.55% 60.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101428874 6.44% 67.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515588328 32.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 493163312 31.30% 31.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465492881 29.54% 60.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101391668 6.44% 67.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515525411 32.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1574978074 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.181766 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.312695 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74681637 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 577546655 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849949420 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58156641 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14643721 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42204470 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 713 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037236907 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52506596 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14643721 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139754890 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 492363005 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15806 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837855661 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 90344991 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976429927 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26743123 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45374465 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126519 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1703162 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 29238118 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985901380 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128373257 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432925820 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 137 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1575573272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.181693 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.312107 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74679257 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 578142352 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849952798 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58148325 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14650540 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 135611620 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 746 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037153887 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52516232 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14650540 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139761664 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 493000122 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16309 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837842196 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 90302441 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976324662 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26749907 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45308958 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126668 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1624936 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 29276583 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985726338 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9127758695 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432766069 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 161 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 311002435 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 176 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 310827393 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 177 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 174 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111413296 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542580071 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199306810 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26873371 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29046971 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1948011764 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857503284 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13502415 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283979579 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647409512 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1574978074 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.179384 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.151840 # Number of insts issued each cycle +system.cpu.rename.skidInsts 111376144 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542477238 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199268014 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26870545 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28963209 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947887828 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 229 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857408251 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13517769 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283855641 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647022412 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 59 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1575573272 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.178878 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151815 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 622116780 39.50% 39.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325952300 20.70% 60.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378187133 24.01% 84.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219716912 13.95% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28998763 1.84% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6186 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 622703787 39.52% 39.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326030740 20.69% 60.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378156304 24.00% 84.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219671219 13.94% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29004864 1.84% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6358 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1574978074 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1575573272 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166073423 40.98% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2008 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191445503 47.24% 88.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47741848 11.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166096777 40.98% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2401 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191354081 47.22% 88.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47812478 11.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 31 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 28 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138255860 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800923 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138249696 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 803001 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -594,90 +596,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 34 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532128426 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186317966 10.03% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 33 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532063614 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186291823 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 37 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857503284 # Type of FU issued -system.cpu.iq.rate 1.179307 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405262832 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218176 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5708749627 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2232004447 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805721857 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 262 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 240 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262765960 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 156 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17817152 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857408251 # Type of FU issued +system.cpu.iq.rate 1.178804 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405265784 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218189 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5709173052 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231756417 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805664221 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 275 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 288 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 75 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262673874 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17815816 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84273737 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66671 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13339 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24459765 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84170904 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66799 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13274 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24420969 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4534666 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4848313 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4535474 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4852528 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14643721 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25440287 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1476217 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1948012141 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14650540 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25426885 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1470128 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947888203 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542580071 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199306810 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159536 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1315183 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13339 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7701795 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8704622 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16406417 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827836046 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516947496 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29667238 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542477238 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199268014 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 167 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159099 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1309527 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13274 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7696809 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8718333 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16415142 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827780120 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516898840 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29628131 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 146 # number of nop insts executed -system.cpu.iew.exec_refs 698700973 # number of memory reference insts executed -system.cpu.iew.exec_branches 229547821 # Number of branches executed -system.cpu.iew.exec_stores 181753477 # Number of stores executed -system.cpu.iew.exec_rate 1.160472 # Inst execution rate -system.cpu.iew.wb_sent 1808752239 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805721927 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169243033 # num instructions producing a value -system.cpu.iew.wb_consumers 1689661119 # num instructions consuming a value -system.cpu.iew.wb_rate 1.146432 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691999 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258080144 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 698650840 # number of memory reference insts executed +system.cpu.iew.exec_branches 229565077 # Number of branches executed +system.cpu.iew.exec_stores 181752000 # Number of stores executed +system.cpu.iew.exec_rate 1.160000 # Inst execution rate +system.cpu.iew.wb_sent 1808693799 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805664296 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169145221 # num instructions producing a value +system.cpu.iew.wb_consumers 1689395973 # num instructions consuming a value +system.cpu.iew.wb_rate 1.145965 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692049 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 257953466 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14631277 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1535484809 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.083718 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.009601 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14638116 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1536081048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.083297 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.009309 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 955186516 62.21% 62.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250636789 16.32% 78.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110101292 7.17% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55286350 3.60% 89.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29268667 1.91% 91.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34069623 2.22% 93.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24728092 1.61% 95.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18117164 1.18% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58090316 3.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 955788021 62.22% 62.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250630730 16.32% 78.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110093475 7.17% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55285008 3.60% 89.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29278263 1.91% 91.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34064309 2.22% 93.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24750177 1.61% 95.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18104449 1.18% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58086616 3.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1535484809 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1536081048 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -727,78 +729,78 @@ system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58090316 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3399506472 # The number of ROB reads -system.cpu.rob.rob_writes 3883723576 # The number of ROB writes -system.cpu.timesIdled 829 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 102290 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58086616 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3399979733 # The number of ROB reads +system.cpu.rob.rob_writes 3883469027 # The number of ROB writes +system.cpu.timesIdled 836 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 98660 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.019758 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.019758 # CPI: Total CPI of All Threads -system.cpu.ipc 0.980625 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.980625 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175817673 # number of integer regfile reads -system.cpu.int_regfile_writes 1261583983 # number of integer regfile writes -system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 52 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965793426 # number of cc regfile reads -system.cpu.cc_regfile_writes 551861251 # number of cc regfile writes -system.cpu.misc_regfile_reads 675850688 # number of misc regfile reads +system.cpu.cpi 1.020141 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.020141 # CPI: Total CPI of All Threads +system.cpu.ipc 0.980257 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.980257 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175723378 # number of integer regfile reads +system.cpu.int_regfile_writes 1261531313 # number of integer regfile writes +system.cpu.fp_regfile_reads 42 # number of floating regfile reads +system.cpu.fp_regfile_writes 57 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965468307 # number of cc regfile reads +system.cpu.cc_regfile_writes 551796531 # number of cc regfile writes +system.cpu.misc_regfile_reads 675796862 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 17003339 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.963435 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638067140 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17003851 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.524861 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 82999500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.963435 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 17001793 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.963908 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638014747 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17002305 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 81846500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.963908 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335713311 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335713311 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 469350712 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469350712 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168716268 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168716268 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335598455 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335598455 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 469297691 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469297691 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168716899 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168716899 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638066980 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638066980 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638066980 # number of overall hits -system.cpu.dcache.overall_hits::total 638066980 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17417847 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17417847 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3869779 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3869779 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638014590 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638014590 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638014590 # number of overall hits +system.cpu.dcache.overall_hits::total 638014590 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17414213 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17414213 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3869148 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3869148 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21287626 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21287626 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21287628 # number of overall misses -system.cpu.dcache.overall_misses::total 21287628 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 440481080000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 440481080000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157197656848 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157197656848 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 597678736848 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 597678736848 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 597678736848 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 597678736848 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486768559 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486768559 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21283361 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21283361 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21283363 # number of overall misses +system.cpu.dcache.overall_misses::total 21283363 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 440649629000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 440649629000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157410000348 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157410000348 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 389500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 389500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 598059629348 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 598059629348 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 598059629348 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 598059629348 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486711904 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486711904 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -807,70 +809,70 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659354606 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659354606 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659354608 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659354608 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022422 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022422 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659297951 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659297951 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659297953 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659297953 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035779 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035779 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022419 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022419 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25289.065864 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25289.065864 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40621.869323 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40621.869323 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54375 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54375 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28076.345237 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28076.345237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28076.342599 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28076.342599 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21218402 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3791861 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 939506 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67507 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.584637 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56.169893 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17003339 # number of writebacks -system.cpu.dcache.writebacks::total 17003339 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151564 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3151564 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1132202 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1132202 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25304.022008 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25304.022008 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40683.375345 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40683.375345 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 97375 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 97375 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28099.867749 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28099.867749 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28099.865108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28099.865108 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21246265 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3823077 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 940794 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67416 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.583334 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335691273000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 335773539500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 82266500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335691273000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84363300436 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 420136839936 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82803.834808 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82803.834808 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87483.716582 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87483.716582 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 90923.968355 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90921.729885 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 90923.968355 # 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average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70358.802876 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100568.350629 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100568.350629 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80574.436827 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80574.436827 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.283974 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.283974 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91058.589213 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85979.286956 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 34005774 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17002402 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21251 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 202098 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 202097 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 14267297 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6463501 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12174811 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3014367 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1493474 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266223 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2736 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011077 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51013813 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176461184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176567488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 6142243 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 104601728 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 23147163 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009565 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.097331 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 14265775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6471532 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12165120 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3013301 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1495847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737605 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737605 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14264700 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2742 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51006435 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51009177 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176263168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176369792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 6143430 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 104594048 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 23146806 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009650 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.097758 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22925769 99.04% 99.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 221393 0.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22923448 99.04% 99.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 223357 0.96% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23147163 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34008359033 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23146806 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34005271029 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 24049 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 21045 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1612497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25505785487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25503465992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 9335651 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 4669993 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 9333292 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 4668829 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3710005 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1634386 # Transaction distribution -system.membus.trans_dist::CleanEvict 3014367 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10 # Transaction distribution -system.membus.trans_dist::ReadExReq 976882 # Transaction distribution -system.membus.trans_dist::ReadExResp 976882 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3710006 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14022538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14022538 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404561472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 404561472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 3708542 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1634268 # Transaction distribution +system.membus.trans_dist::CleanEvict 3013301 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 977171 # Transaction distribution +system.membus.trans_dist::ReadExResp 977171 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3708543 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14019005 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14019005 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404478784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 404478784 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4686898 # Request fanout histogram +system.membus.snoop_fanout::samples 4685723 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4686898 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4685723 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4686898 # Request fanout histogram -system.membus.reqLayer0.occupancy 17643111757 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4685723 # Request fanout histogram +system.membus.reqLayer0.occupancy 17639856241 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25454576781 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25447920698 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |