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authorAndreas Sandberg <andreas.sandberg@arm.com>2016-06-02 14:14:36 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2016-06-02 14:14:36 +0100
commit1d933447fc62de67db938970a8308ac47189fd96 (patch)
treedf7f389eeae7916c3a58082644d6929bf0e94280 /tests/long/se/60.bzip2/ref/arm
parent660fbd543f7c84dec81cd17bdb4ff08f954aec77 (diff)
downloadgem5-1d933447fc62de67db938970a8308ac47189fd96.tar.xz
stats: Update to match ARM ISA changes
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm')
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini9
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr1
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout2
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt16
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini6
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout3
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt12
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini26
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout5
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt12
10 files changed, 63 insertions, 29 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 6544ce244..540dec5ab 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -147,8 +149,15 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
index eeb19437b..be90b0340 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index dc097b928..77417a942 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -27,4 +27,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 767851412000 because target called exit()
+Exiting @ tick 767803843500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 94c50de3e..d2e653fdf 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.767804 # Nu
sim_ticks 767803843500 # Number of ticks simulated
final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 196848 # Simulator instruction rate (inst/s)
-host_op_rate 212074 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 97853290 # Simulator tick rate (ticks/s)
-host_mem_usage 309012 # Number of bytes of host memory used
-host_seconds 7846.48 # Real time elapsed on the host
+host_inst_rate 232866 # Simulator instruction rate (inst/s)
+host_op_rate 250878 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 115757951 # Simulator tick rate (ticks/s)
+host_mem_usage 355612 # Number of bytes of host memory used
+host_seconds 6632.84 # Real time elapsed on the host
sim_insts 1544563024 # Number of instructions simulated
sim_ops 1664032416 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -478,7 +478,7 @@ system.cpu.rename.IQFullEvents 126625 # Nu
system.cpu.rename.LQFullEvents 1588286 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 25069373 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 1985943496 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 9128568325 # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups 9128568020 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2432995559 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 145 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
@@ -495,7 +495,7 @@ system.cpu.iq.iqNonSpecInstsAdded 231 # Nu
system.cpu.iq.iqInstsIssued 1857492479 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 13497229 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 284014957 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 647584155 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 647584065 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1535531474 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.209674 # Number of insts issued each cycle
@@ -716,7 +716,7 @@ system.cpu.fp_regfile_reads 42 # nu
system.cpu.fp_regfile_writes 54 # number of floating regfile writes
system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads
system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes
-system.cpu.misc_regfile_reads 675853693 # number of misc regfile reads
+system.cpu.misc_regfile_reads 675853616 # number of misc regfile reads
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
system.cpu.dcache.tags.replacements 17003710 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index dce12b6b3..1b535494d 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -15,6 +15,7 @@ boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@@ -24,9 +25,12 @@ mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -130,6 +134,7 @@ eventq_index=0
[system.cpu.isa]
type=ArmISA
+decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
@@ -248,6 +253,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
index e972d8df4..6fb821b07 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -6,7 +6,6 @@ gem5 started Jan 23 2014 18:13:20
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x571a380
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
@@ -25,4 +24,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 861538200000 because target called exit()
+Exiting @ tick 832017490500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index f7caf50c2..cac059bf6 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu
sim_ticks 832017490500 # Number of ticks simulated
final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1043463 # Simulator instruction rate (inst/s)
-host_op_rate 1124173 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 562087533 # Simulator tick rate (ticks/s)
-host_mem_usage 256656 # Number of bytes of host memory used
-host_seconds 1480.23 # Real time elapsed on the host
+host_inst_rate 2181717 # Simulator instruction rate (inst/s)
+host_op_rate 2350469 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1175236125 # Simulator tick rate (ticks/s)
+host_mem_usage 301652 # Number of bytes of host memory used
+host_seconds 707.96 # Real time elapsed on the host
sim_insts 1544563042 # Number of instructions simulated
sim_ops 1664032434 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -164,7 +164,7 @@ system.cpu.num_func_calls 27330256 # nu
system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
system.cpu.num_int_insts 1477900422 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
-system.cpu.num_int_register_reads 2605402942 # number of times the integer registers were read
+system.cpu.num_int_register_reads 2605402867 # number of times the integer registers were read
system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 8ed495e8c..d42bc7142 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -15,6 +15,7 @@ boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@@ -24,9 +25,12 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -85,9 +89,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -101,6 +105,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -161,9 +166,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -177,6 +182,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -196,6 +202,7 @@ eventq_index=0
[system.cpu.isa]
type=ArmISA
+decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
@@ -271,9 +278,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -287,6 +294,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -302,12 +310,14 @@ size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@@ -315,6 +325,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@@ -364,6 +381,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
index 4d71ca666..8064c269e 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
@@ -6,7 +8,6 @@ gem5 started Jan 23 2014 18:15:41
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x5333d00
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
@@ -25,4 +26,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2391205115000 because target called exit()
+Exiting @ tick 2377029670500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 6f79ed44a..e1d79bb9d 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 2.377030 # Nu
sim_ticks 2377029670500 # Number of ticks simulated
final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 651336 # Simulator instruction rate (inst/s)
-host_op_rate 701905 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1006163929 # Simulator tick rate (ticks/s)
-host_mem_usage 265624 # Number of bytes of host memory used
-host_seconds 2362.47 # Real time elapsed on the host
+host_inst_rate 1359798 # Simulator instruction rate (inst/s)
+host_op_rate 1465373 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2100575394 # Simulator tick rate (ticks/s)
+host_mem_usage 311664 # Number of bytes of host memory used
+host_seconds 1131.61 # Real time elapsed on the host
sim_insts 1538759602 # Number of instructions simulated
sim_ops 1658228915 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -165,7 +165,7 @@ system.cpu.num_func_calls 27330256 # nu
system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
system.cpu.num_int_insts 1477900422 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
-system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read
+system.cpu.num_int_register_reads 2601860297 # number of times the integer registers were read
system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written