diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/se/60.bzip2/ref/arm | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm')
9 files changed, 819 insertions, 819 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 48015577c..c94040a4a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 2f52f2c05..1148e0586 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:36:31 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:20:26 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 463993693500 because target called exit() +Exiting @ tick 458035985000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 7863d76cc..f8f6b4a6a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.463994 # Number of seconds simulated -sim_ticks 463993693500 # Number of ticks simulated -final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.458036 # Number of seconds simulated +sim_ticks 458035985000 # Number of ticks simulated +final_tick 458035985000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128371 # Simulator instruction rate (inst/s) -host_op_rate 143208 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38563333 # Simulator tick rate (ticks/s) -host_mem_usage 232076 # Number of bytes of host memory used -host_seconds 12031.99 # Real time elapsed on the host -sim_insts 1544563066 # Number of instructions simulated -sim_ops 1723073879 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 49344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 189746304 # Number of bytes read from this memory -system.physmem.bytes_read::total 189795648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 49344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 49344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78222144 # Number of bytes written to this memory -system.physmem.bytes_written::total 78222144 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2964786 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2965557 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1222221 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1222221 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 408941558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 409047904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 106346 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 106346 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 168584498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 168584498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 168584498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 408941558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 577632403 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 197390 # Simulator instruction rate (inst/s) +host_op_rate 220203 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58535443 # Simulator tick rate (ticks/s) +host_mem_usage 234800 # Number of bytes of host memory used +host_seconds 7824.93 # Real time elapsed on the host +sim_insts 1544563073 # Number of instructions simulated +sim_ops 1723073885 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156358784 # Number of bytes read from this memory +system.physmem.bytes_read::total 156407104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71946432 # Number of bytes written to this memory +system.physmem.bytes_written::total 71946432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2443106 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2443861 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1124163 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1124163 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 105494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 341367904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 341473398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 105494 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 105494 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 157075938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 157075938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 157075938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 105494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 341367904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 498549336 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,322 +77,322 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 927987388 # number of cpu cycles simulated +system.cpu.numCycles 916071971 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 300553850 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 246366147 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16098585 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 170916236 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 156311774 # Number of BTB hits +system.cpu.BPredUnit.lookups 300386365 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 246254548 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16072669 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 170403157 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 156239351 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18335288 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 425 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 292740519 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2158326699 # Number of instructions fetch has processed -system.cpu.fetch.Branches 300553850 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174647062 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 429206926 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83759589 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 129259054 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 200 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 283730265 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5372560 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 918446800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.613763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.238744 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18292614 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 292465712 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2157283635 # Number of instructions fetch has processed +system.cpu.fetch.Branches 300386365 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174531965 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 428963032 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83531263 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119911343 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 109 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 283465873 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5375761 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 908345220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.641582 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.245010 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 489239924 53.27% 53.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23020148 2.51% 55.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38764254 4.22% 60.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47809734 5.21% 65.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40766066 4.44% 69.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46976906 5.11% 74.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39072572 4.25% 79.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18137057 1.97% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174660139 19.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 479382246 52.78% 52.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23075019 2.54% 55.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38696357 4.26% 59.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47758356 5.26% 64.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40740735 4.49% 69.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46836926 5.16% 74.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39064245 4.30% 78.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18137906 2.00% 80.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174653430 19.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 918446800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.323877 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.325815 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 322039794 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 109288431 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403236235 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16643003 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 67239337 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46165390 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 810 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2346870217 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2646 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 67239337 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 343676895 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50827249 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9551 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 397069716 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 59624052 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2289998307 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23088 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4666333 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 46320806 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2264655243 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10570139009 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10570134861 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4148 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319999 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 558335244 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4462 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4454 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 136929133 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624839821 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 218742392 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85961960 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66558298 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2190567677 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 692 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2016055896 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4892741 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462785080 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1074735939 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 918446800 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.195071 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.923309 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 908345220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.327907 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.354928 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 321276302 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100437637 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403614016 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16012907 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 67004358 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46143588 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 709 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2345766913 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2404 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 67004358 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 342772787 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 44470406 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13938 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 396994343 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 57089388 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2288809868 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21597 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4587251 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 43867874 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2263371035 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10565210641 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10565207285 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3356 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706320010 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 557051025 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5363 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5361 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 133306732 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624412648 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 218802984 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85974356 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 66146404 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2189209490 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1708 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2014638202 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4851094 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 461527844 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1075835396 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1528 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 908345220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.217921 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.925838 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 251194344 27.35% 27.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 138877340 15.12% 42.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158309179 17.24% 59.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 116273452 12.66% 72.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125754756 13.69% 86.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75525220 8.22% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39163504 4.26% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10678346 1.16% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2670659 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 244431658 26.91% 26.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 136114338 14.98% 41.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 157116427 17.30% 59.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 116129005 12.78% 71.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125782921 13.85% 85.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75959694 8.36% 94.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39392857 4.34% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10729861 1.18% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2688459 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 918446800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 908345220 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 824240 3.28% 3.28% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4827 0.02% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19025079 75.82% 79.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5238831 20.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 792596 3.16% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4903 0.02% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19003801 75.87% 79.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5245876 20.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234276939 61.22% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 932607 0.05% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 29 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587048024 29.12% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193798201 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1233307061 61.22% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 930228 0.05% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 49 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 28 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 10 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 586604414 29.12% 90.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193796407 9.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2016055896 # Type of FU issued -system.cpu.iq.rate 2.172504 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25092977 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012447 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4980543862 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2653539100 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1958126109 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 448 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 790 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2041148646 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 227 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63700277 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2014638202 # Type of FU issued +system.cpu.iq.rate 2.199214 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25047176 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012433 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4967519524 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2650923657 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1956580647 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 370 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2039685190 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 188 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63569960 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138913044 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 284373 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189336 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 43895340 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138485869 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 280074 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 188083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 43955929 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 451092 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 515490 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 67239337 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23164250 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1316440 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2190576494 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5585867 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624839821 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 218742392 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 626 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 207277 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 49894 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189336 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8626288 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10208500 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18834788 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1986583692 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 572477440 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29472204 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 67004358 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 19766452 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1127497 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2189219165 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5544678 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624412648 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 218802984 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1639 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 172089 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 43011 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 188083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8607625 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10203792 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18811417 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1985083877 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 571977023 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29554325 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 8125 # number of nop insts executed -system.cpu.iew.exec_refs 763312359 # number of memory reference insts executed -system.cpu.iew.exec_branches 238194699 # Number of branches executed -system.cpu.iew.exec_stores 190834919 # Number of stores executed -system.cpu.iew.exec_rate 2.140744 # Inst execution rate -system.cpu.iew.wb_sent 1967109112 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1958126281 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296093484 # num instructions producing a value -system.cpu.iew.wb_consumers 2068479796 # num instructions consuming a value +system.cpu.iew.exec_nop 7967 # number of nop insts executed +system.cpu.iew.exec_refs 762799722 # number of memory reference insts executed +system.cpu.iew.exec_branches 238022734 # Number of branches executed +system.cpu.iew.exec_stores 190822699 # Number of stores executed +system.cpu.iew.exec_rate 2.166952 # Inst execution rate +system.cpu.iew.wb_sent 1965575614 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1956580779 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296425776 # num instructions producing a value +system.cpu.iew.wb_consumers 2069436870 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.110079 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626592 # average fanout of values written-back +system.cpu.iew.wb_rate 2.135837 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626463 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1544563084 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1723073897 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 467569115 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 177 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16098007 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 851207464 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.024270 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.756192 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1544563091 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1723073903 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 466205393 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 180 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16072230 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 841340863 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.048009 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.762269 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 362905349 42.63% 42.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192760849 22.65% 65.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73571189 8.64% 73.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35131293 4.13% 78.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18689200 2.20% 80.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30622248 3.60% 83.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19666355 2.31% 86.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10977227 1.29% 87.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106883754 12.56% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 352627350 41.91% 41.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193034897 22.94% 64.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73667996 8.76% 73.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35236864 4.19% 77.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18719576 2.22% 80.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30675778 3.65% 83.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19663987 2.34% 86.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10964014 1.30% 87.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106750401 12.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 851207464 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563084 # Number of instructions committed -system.cpu.commit.committedOps 1723073897 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 841340863 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563091 # Number of instructions committed +system.cpu.commit.committedOps 1723073903 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773829 # Number of memory references committed -system.cpu.commit.loads 485926777 # Number of loads committed +system.cpu.commit.refs 660773834 # Number of memory references committed +system.cpu.commit.loads 485926779 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462371 # Number of branches committed +system.cpu.commit.branches 213462373 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941877 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941881 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106883754 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106750401 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2934966123 # The number of ROB reads -system.cpu.rob.rob_writes 4448699546 # The number of ROB writes -system.cpu.timesIdled 899596 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9540588 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563066 # Number of Instructions Simulated -system.cpu.committedOps 1723073879 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563066 # Number of Instructions Simulated -system.cpu.cpi 0.600809 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.600809 # CPI: Total CPI of All Threads -system.cpu.ipc 1.664422 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.664422 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9951953141 # number of integer regfile reads -system.cpu.int_regfile_writes 1938266429 # number of integer regfile writes -system.cpu.fp_regfile_reads 186 # number of floating regfile reads -system.cpu.fp_regfile_writes 205 # number of floating regfile writes -system.cpu.misc_regfile_reads 2897977277 # number of misc regfile reads -system.cpu.misc_regfile_writes 138 # number of misc regfile writes -system.cpu.icache.replacements 28 # number of replacements -system.cpu.icache.tagsinuse 641.389873 # Cycle average of tags in use -system.cpu.icache.total_refs 283729068 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 801 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 354218.561798 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2923869159 # The number of ROB reads +system.cpu.rob.rob_writes 4445740607 # The number of ROB writes +system.cpu.timesIdled 753914 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7726751 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563073 # Number of Instructions Simulated +system.cpu.committedOps 1723073885 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563073 # Number of Instructions Simulated +system.cpu.cpi 0.593095 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.593095 # CPI: Total CPI of All Threads +system.cpu.ipc 1.686072 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.686072 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9944305109 # number of integer regfile reads +system.cpu.int_regfile_writes 1936656463 # number of integer regfile writes +system.cpu.fp_regfile_reads 139 # number of floating regfile reads +system.cpu.fp_regfile_writes 147 # number of floating regfile writes +system.cpu.misc_regfile_reads 2896410924 # number of misc regfile reads +system.cpu.misc_regfile_writes 144 # number of misc regfile writes +system.cpu.icache.replacements 25 # number of replacements +system.cpu.icache.tagsinuse 627.053723 # Cycle average of tags in use +system.cpu.icache.total_refs 283464725 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 785 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 361101.560510 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 641.389873 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.313179 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.313179 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 283729068 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 283729068 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 283729068 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 283729068 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 283729068 # number of overall hits -system.cpu.icache.overall_hits::total 283729068 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1197 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1197 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1197 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1197 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1197 # number of overall misses -system.cpu.icache.overall_misses::total 1197 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39840000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39840000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39840000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39840000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39840000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39840000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 283730265 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 283730265 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 283730265 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 283730265 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 283730265 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 283730265 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 627.053723 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.306179 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.306179 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 283464725 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 283464725 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 283464725 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 283464725 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 283464725 # number of overall hits +system.cpu.icache.overall_hits::total 283464725 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1148 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1148 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1148 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1148 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1148 # number of overall misses +system.cpu.icache.overall_misses::total 1148 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38598000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38598000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38598000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38598000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38598000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38598000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 283465873 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 283465873 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 283465873 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 283465873 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 283465873 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 283465873 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 33283.208020 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 33283.208020 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 33283.208020 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33621.951220 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33621.951220 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33621.951220 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33621.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33621.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33621.951220 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,309 +401,309 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 396 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 396 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 396 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 396 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 396 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27579500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27579500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27579500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27579500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27579500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27579500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 363 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 363 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 363 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 363 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 363 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 785 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 785 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 785 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 785 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27001000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27001000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27001000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27001000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27001000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27001000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34431.335830 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34431.335830 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34396.178344 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34396.178344 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34396.178344 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34396.178344 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34396.178344 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34396.178344 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9619302 # number of replacements -system.cpu.dcache.tagsinuse 4087.756066 # Cycle average of tags in use -system.cpu.dcache.total_refs 660726669 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9623398 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.658354 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3346373000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.756066 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997987 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 493348220 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 493348220 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167378287 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167378287 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 94 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 68 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 68 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 660726507 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 660726507 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 660726507 # number of overall hits -system.cpu.dcache.overall_hits::total 660726507 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10693817 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10693817 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5207760 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5207760 # number of WriteReq misses +system.cpu.dcache.replacements 9618836 # number of replacements +system.cpu.dcache.tagsinuse 4087.631943 # Cycle average of tags in use +system.cpu.dcache.total_refs 660703184 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9622932 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.659239 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3346369000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.631943 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997957 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997957 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 493290864 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 493290864 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167412157 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167412157 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 92 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 92 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 71 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 71 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 660703021 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 660703021 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 660703021 # number of overall hits +system.cpu.dcache.overall_hits::total 660703021 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10330521 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10330521 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5173890 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5173890 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15901577 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15901577 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15901577 # number of overall misses -system.cpu.dcache.overall_misses::total 15901577 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 189065481500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 189065481500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129319032251 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129319032251 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 15504411 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15504411 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15504411 # number of overall misses +system.cpu.dcache.overall_misses::total 15504411 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 163224239500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 163224239500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 124852568337 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 124852568337 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 318384513751 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 318384513751 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 318384513751 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 318384513751 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 504042037 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 504042037 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 288076807837 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 288076807837 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 288076807837 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 288076807837 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 503621385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 503621385 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 68 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 68 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 676628084 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 676628084 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 676628084 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 676628084 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021216 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021216 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.030175 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023501 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023501 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023501 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023501 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17679.887499 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17679.887499 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24831.987697 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24831.987697 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 95 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 95 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 71 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 71 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 676207432 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 676207432 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 676207432 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 676207432 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020512 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020512 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029979 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029979 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.031579 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.031579 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.022928 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022928 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022928 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022928 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15800.194346 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15800.194346 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24131.276146 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24131.276146 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20022.197405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20022.197405 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 271440605 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 164500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 91957 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2951.821014 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16450 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18580.312908 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18580.312908 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18580.312908 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18580.312908 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 200292336 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 119500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73738 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2716.270254 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14937.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3133684 # number of writebacks -system.cpu.dcache.writebacks::total 3133684 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2964371 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2964371 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313808 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3313808 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3473805 # number of writebacks +system.cpu.dcache.writebacks::total 3473805 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2601467 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2601467 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3280012 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3280012 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6278179 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6278179 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6278179 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6278179 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729446 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7729446 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893952 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893952 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9623398 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9623398 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9623398 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9623398 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93061119500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 93061119500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45369971960 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 45369971960 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138431091460 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 138431091460 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138431091460 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 138431091460 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015335 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015335 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 5881479 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5881479 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5881479 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5881479 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729054 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7729054 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893878 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893878 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9622932 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9622932 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9622932 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9622932 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78985396500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 78985396500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 42766465749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 42766465749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 121751862249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 121751862249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 121751862249 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 121751862249 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015347 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015347 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014223 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.817537 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.817537 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23955.185749 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23955.185749 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014231 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014231 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014231 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014231 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10219.283822 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10219.283822 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22581.425915 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22581.425915 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12652.262559 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12652.262559 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12652.262559 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12652.262559 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2953110 # number of replacements -system.cpu.l2cache.tagsinuse 26875.343151 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7878336 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2980430 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.643355 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 100989511500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10758.137226 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 11.396468 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16105.809458 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.328312 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000348 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.491510 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.820170 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 2428308 # number of replacements +system.cpu.l2cache.tagsinuse 31141.553043 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8745111 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2458022 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.557784 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 77921850000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14050.890908 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 15.916061 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 17074.746074 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.428799 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000486 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.521080 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.950365 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 5680299 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5680328 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3133684 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3133684 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 978305 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 978305 # 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number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208586 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208662 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438747 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438747 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253884 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.253941 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253884 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.253941 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31186.754967 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31191.078868 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31191.076844 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31459.860230 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31459.860230 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31186.754967 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31282.495111 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31282.465533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31186.754967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31282.495111 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31282.465533 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index b103ca45f..e60a29e1d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index 4559b3892..5ff891bb9 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:41:45 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:21:22 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 861538205000 because target called exit() +Exiting @ tick 861538200000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 6c3e8b909..9f9278806 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.861538 # Number of seconds simulated -sim_ticks 861538205000 # Number of ticks simulated -final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 861538200000 # Number of ticks simulated +final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2187855 # Simulator instruction rate (inst/s) -host_op_rate 2440714 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1220358665 # Simulator tick rate (ticks/s) -host_mem_usage 221416 # Number of bytes of host memory used -host_seconds 705.97 # Real time elapsed on the host -sim_insts 1544563049 # Number of instructions simulated -sim_ops 1723073862 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 6178262392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1581387672 # Number of bytes read from this memory -system.physmem.bytes_read::total 7759650064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6178262392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6178262392 # Number of instructions bytes read from this memory +host_inst_rate 3167213 # Simulator instruction rate (inst/s) +host_op_rate 3533259 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1766632085 # Simulator tick rate (ticks/s) +host_mem_usage 225200 # Number of bytes of host memory used +host_seconds 487.67 # Real time elapsed on the host +sim_insts 1544563041 # Number of instructions simulated +sim_ops 1723073853 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory +system.physmem.bytes_read::total 7759650027 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6178262356 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6178262356 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1544565598 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 482384188 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2026949786 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1544565589 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 482384187 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2026949776 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7171199555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1835539809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9006739363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7171199555 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7171199555 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 724469778 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 724469778 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7171199555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2560009587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9731209141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7171199554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1835539818 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9006739373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7171199554 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7171199554 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 724469782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 724469782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7171199554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2560009600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9731209155 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1723076411 # number of cpu cycles simulated +system.cpu.numCycles 1723076401 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1544563049 # Number of instructions committed -system.cpu.committedOps 1723073862 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses +system.cpu.committedInsts 1544563041 # Number of instructions committed +system.cpu.committedOps 1723073853 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses -system.cpu.num_func_calls 27330134 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls -system.cpu.num_int_insts 1536941850 # number of integer instructions +system.cpu.num_func_calls 27330256 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 177498327 # number of instructions that are conditional controls +system.cpu.num_int_insts 1536941842 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 7861284536 # number of times the integer registers were read -system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written +system.cpu.num_int_register_reads 7861284498 # number of times the integer registers were read +system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 660773816 # number of memory refs -system.cpu.num_load_insts 485926770 # Number of load instructions +system.cpu.num_mem_refs 660773815 # number of memory refs +system.cpu.num_load_insts 485926769 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1723076411 # Number of busy cycles +system.cpu.num_busy_cycles 1723076401 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 88ea9515a..e66f558e0 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index d07a6ceff..4ec39cba0 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:44:07 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:25:17 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2431419954000 because target called exit() +Exiting @ tick 2408512388000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index db0ae235a..c9d66243a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.431420 # Number of seconds simulated -sim_ticks 2431419954000 # Number of ticks simulated -final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.408512 # Number of seconds simulated +sim_ticks 2408512388000 # Number of ticks simulated +final_tick 2408512388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1031283 # Simulator instruction rate (inst/s) -host_op_rate 1150922 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1629547552 # Simulator tick rate (ticks/s) -host_mem_usage 230584 # Number of bytes of host memory used -host_seconds 1492.08 # Real time elapsed on the host -sim_insts 1538759609 # Number of instructions simulated -sim_ops 1717270343 # Number of ops (including micro ops) simulated +host_inst_rate 1431405 # Simulator instruction rate (inst/s) +host_op_rate 1597462 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2240478292 # Simulator tick rate (ticks/s) +host_mem_usage 233776 # Number of bytes of host memory used +host_seconds 1075.00 # Real time elapsed on the host +sim_insts 1538759601 # Number of instructions simulated +sim_ops 1717270334 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 172726592 # Number of bytes read from this memory -system.physmem.bytes_read::total 172766016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137819840 # Number of bytes read from this memory +system.physmem.bytes_read::total 137859264 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75006720 # Number of bytes written to this memory -system.physmem.bytes_written::total 75006720 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67221184 # Number of bytes written to this memory +system.physmem.bytes_written::total 67221184 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2698853 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2699469 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1171980 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1171980 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 71039391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 71055605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30848937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30848937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30848937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 71039391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 101904542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 2153435 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2154051 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050331 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050331 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 16369 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 57221977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 57238345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16369 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16369 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27909835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27909835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27909835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 57221977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 85148181 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,43 +77,43 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4862839908 # number of cpu cycles simulated +system.cpu.numCycles 4817024776 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1538759609 # Number of instructions committed -system.cpu.committedOps 1717270343 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses +system.cpu.committedInsts 1538759601 # Number of instructions committed +system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses -system.cpu.num_func_calls 27330134 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls -system.cpu.num_int_insts 1536941850 # number of integer instructions +system.cpu.num_func_calls 27330256 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 177498327 # number of instructions that are conditional controls +system.cpu.num_int_insts 1536941842 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read -system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written +system.cpu.num_int_register_reads 9304894672 # number of times the integer registers were read +system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 660773816 # number of memory refs -system.cpu.num_load_insts 485926770 # Number of load instructions +system.cpu.num_mem_refs 660773815 # number of memory refs +system.cpu.num_load_insts 485926769 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4862839908 # Number of busy cycles +system.cpu.num_busy_cycles 4817024776 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 7 # number of replacements -system.cpu.icache.tagsinuse 514.872896 # Cycle average of tags in use -system.cpu.icache.total_refs 1544564961 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 515.022606 # Cycle average of tags in use +system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 514.872896 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.251403 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.251403 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1544564961 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1544564961 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1544564961 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1544564961 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1544564961 # number of overall hits -system.cpu.icache.overall_hits::total 1544564961 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 515.022606 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.251476 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.251476 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits +system.cpu.icache.overall_hits::total 1544564952 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses @@ -126,12 +126,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 34804000 system.cpu.icache.demand_miss_latency::total 34804000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 34804000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 34804000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1544565599 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1544565599 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1544565599 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1544565599 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1544565599 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1544565599 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses @@ -178,26 +178,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138 system.cpu.icache.overall_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9111140 # number of replacements -system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use -system.cpu.dcache.total_refs 645855060 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4083.603265 # Cycle average of tags in use +system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25923025000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4083.719979 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997002 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997002 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 475158040 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 475158040 # number of ReadReq hits +system.cpu.dcache.warmup_cycle 25922973000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4083.603265 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996973 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996973 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 645854938 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 645854938 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 645854938 # number of overall hits -system.cpu.dcache.overall_hits::total 645854938 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits +system.cpu.dcache.overall_hits::total 645854937 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 9115236 # n system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 177140908000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177140908000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 63824222000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 63824222000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 240965130000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 240965130000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 240965130000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 240965130000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 482384127 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 482384127 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 158470312000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 158470312000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59587262000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59587262000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 218057574000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 218057574000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 218057574000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 218057574000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 654970174 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 654970174 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 654970174 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 654970174 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24514.084594 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33784.641656 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26435.424162 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26435.424162 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21930.307786 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21930.307786 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31541.854031 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31541.854031 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23922.317974 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23922.317974 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23922.317974 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23922.317974 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3061985 # number of writebacks -system.cpu.dcache.writebacks::total 3061985 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3385547 # number of writebacks +system.cpu.dcache.writebacks::total 3385547 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155462647000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 155462647000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58156775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 58156775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213619422000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 213619422000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213619422000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 213619422000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136792051000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 136792051000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53919815000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53919815000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190711866000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 190711866000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190711866000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 190711866000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21514.084594 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21514.084594 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30784.641656 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30784.641656 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18930.307786 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18930.307786 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28541.854031 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28541.854031 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20922.317974 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20922.317974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20922.317974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20922.317974 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2687066 # number of replacements -system.cpu.l2cache.tagsinuse 26134.517233 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7569171 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2714383 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.788542 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 538044123000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 11106.896016 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 11.181020 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15016.440197 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.338956 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000341 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.458265 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.797562 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 2138446 # number of replacements +system.cpu.l2cache.tagsinuse 30628.680390 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8443619 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2168151 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.894387 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 437045285000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14782.399882 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 15.716042 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15830.564466 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.451123 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000480 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.483110 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.934713 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 5417142 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5417164 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3061985 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3061985 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 999241 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 999241 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5861680 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5861702 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3385547 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3385547 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1100121 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1100121 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 6416383 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6416405 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 6961801 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6961823 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 6416383 # 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number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3385547 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses @@ -347,16 +347,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 638 system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250335 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.250398 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471063 # 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