stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

4 files changed, 74 insertions, 20 deletions

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
index 836b1fb8a..d91451297 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  1.116866                       # Nu
 sim_ticks                                1116865668500                       # Number of ticks simulated
 final_tick                               1116865668500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 243832                       # Simulator instruction rate (inst/s)
-host_op_rate                                   262692                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              176313668                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 266900                       # Number of bytes of host memory used
-host_seconds                                  6334.54                       # Real time elapsed on the host
+host_inst_rate                                 380135                       # Simulator instruction rate (inst/s)
+host_op_rate                                   409538                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              274873670                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 314372                       # Number of bytes of host memory used
+host_seconds                                  4063.20                       # Real time elapsed on the host
 sim_insts                                  1544563088                       # Number of instructions simulated
 sim_ops                                    1664032481                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             50112                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         130931712                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            130981824                       # Number of bytes read from this memory
@@ -284,6 +285,7 @@ system.physmem_1.memoryStateTime::REF     37294400000                       # Ti
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT    593987729250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.cpu.branchPred.lookups               239639355                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         186342486                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          14526193                       # Number of conditional branches incorrect
@@ -298,6 +300,7 @@ system.cpu.branchPred.indirectHits                230                       # Nu
 system.cpu.branchPred.indirectMisses              307                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted          164                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -327,6 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -356,6 +360,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -385,6 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -415,6 +421,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON    1116865668500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                       2233731337                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -461,6 +468,7 @@ system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Cl
 system.cpu.op_class_0::total               1664032481                       # Class of committed instruction
 system.cpu.tickCycles                      1834123667                       # Number of cycles that the object actually ticked
 system.cpu.idleCycles                       399607670                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements           9221041                       # number of replacements
 system.cpu.dcache.tags.tagsinuse          4085.616095                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           624218928                       # Total number of references to valid blocks.
@@ -478,6 +486,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3           61
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses        1276841941                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses       1276841941                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data    453887732                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       453887732                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    170331073                       # number of WriteReq hits
@@ -598,6 +607,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                29                       # number of replacements
 system.cpu.icache.tags.tagsinuse           660.385482                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           465281510                       # Total number of references to valid blocks.
@@ -614,6 +624,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4          753
 system.cpu.icache.tags.occ_task_id_percent::1024     0.385742                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses         930565477                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses        930565477                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst    465281510                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       465281510                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     465281510                       # number of demand (read+write) hits
@@ -682,6 +693,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694
 system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements          2013919                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        31258.258362                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           14509191                       # Total number of references to valid blocks.
@@ -704,6 +716,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15553
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908691                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses        151498004                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses       151498004                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks      3684567                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total      3684567                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks           29                       # number of WritebackClean hits
@@ -856,6 +869,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1594
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1286                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1280                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp       7335103                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty      4734690                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean           29                       # Transaction distribution
@@ -888,6 +902,7 @@ system.cpu.toL2Bus.respLayer0.occupancy       1228500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy   13837707995                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 1116865668500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp            1245432                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty      1050123                       # Transaction distribution
 system.membus.trans_dist::CleanEvict           962724                       # Transaction distribution
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index d2e653fdf..bd5e79823 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.767804                       # Nu
 sim_ticks                                767803843500                       # Number of ticks simulated
 final_tick                               767803843500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 232866                       # Simulator instruction rate (inst/s)
-host_op_rate                                   250878                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              115757951                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 355612                       # Number of bytes of host memory used
-host_seconds                                  6632.84                       # Real time elapsed on the host
+host_inst_rate                                 232978                       # Simulator instruction rate (inst/s)
+host_op_rate                                   250999                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              115813638                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 356264                       # Number of bytes of host memory used
+host_seconds                                  6629.65                       # Real time elapsed on the host
 sim_insts                                  1544563024                       # Number of instructions simulated
 sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             65216                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         235320384                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.l2cache.prefetcher     63711040                       # Number of bytes read from this memory
@@ -298,6 +299,7 @@ system.physmem_1.memoryStateTime::REF     25638600000                       # Ti
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT    576690946995                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.branchPred.lookups               286292198                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         223415085                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          14631198                       # Number of conditional branches incorrect
@@ -312,6 +314,7 @@ system.cpu.branchPred.indirectHits               1888                       # Nu
 system.cpu.branchPred.indirectMisses             1139                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted          136                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -341,6 +344,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -370,6 +374,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -399,6 +404,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -429,6 +435,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON    767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                       1535607688                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -718,6 +725,7 @@ system.cpu.cc_regfile_reads                6965778765                       # nu
 system.cpu.cc_regfile_writes                551854660                       # number of cc regfile writes
 system.cpu.misc_regfile_reads               675853616                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements          17003710                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.964650                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           638076364                       # Total number of references to valid blocks.
@@ -733,6 +741,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1          117
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses        1335728390                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses       1335728390                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data    469357603                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       469357603                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    168718615                       # number of WriteReq hits
@@ -861,6 +870,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements               589                       # number of replacements
 system.cpu.icache.tags.tagsinuse           444.836642                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           656966815                       # Total number of references to valid blocks.
@@ -877,6 +887,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4          441
 system.cpu.icache.tags.occ_task_id_percent::1024     0.949219                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses        1313937945                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses       1313937945                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst    656966815                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       656966815                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     656966815                       # number of demand (read+write) hits
@@ -951,12 +962,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825
 system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825                       # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.prefetcher.num_hwpf_issued     11611376                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified     11640224                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit        19566                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu.l2cache.prefetcher.pfSpanPage      4656640                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements          4706089                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        16099.754607                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           22829126                       # Total number of references to valid blocks.
@@ -984,6 +997,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022     0.050598
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.921448                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses        552242422                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses       552242422                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks      4833112                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total      4833112                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks     12149903                       # number of WritebackClean hits
@@ -1169,6 +1183,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21284
 system.cpu.toL2Bus.snoop_filter.tot_snoops      2918086                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops      2899299                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        18787                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp      14267664                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty      6469008                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean     12171187                       # Transaction distribution
@@ -1207,6 +1222,7 @@ system.cpu.toL2Bus.respLayer0.occupancy       1613498                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy   25506339992                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          3.3                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 767803843500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp            3696594                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty      1635896                       # Transaction distribution
 system.membus.trans_dist::CleanEvict          3001813                       # Transaction distribution
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index cac059bf6..9d26db066 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.832017                       # Nu
 sim_ticks                                832017490500                       # Number of ticks simulated
 final_tick                               832017490500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2181717                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2350469                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1175236125                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301652                       # Number of bytes of host memory used
-host_seconds                                   707.96                       # Real time elapsed on the host
+host_inst_rate                                2178318                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2346807                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1173405208                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 302320                       # Number of bytes of host memory used
+host_seconds                                   709.06                       # Real time elapsed on the host
 sim_insts                                  1544563042                       # Number of instructions simulated
 sim_ops                                    1664032434                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst        6178262360                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        1581387671                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           7759650031                       # Number of bytes read from this memory
@@ -35,7 +36,9 @@ system.physmem.bw_write::total              750174605                       # Wr
 system.physmem.bw_total::cpu.inst          7425640002                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          2650840984                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total            10076480986                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 832017490500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -153,6 +159,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON    832017490500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                       1664034982                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite               174847046     10.51%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1664032481                       # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq          1999474725                       # Transaction distribution
 system.membus.trans_dist::ReadResp         1999474786                       # Transaction distribution
 system.membus.trans_dist::WriteReq          172586047                       # Transaction distribution
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index e1d79bb9d..59601069e 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  2.377030                       # Nu
 sim_ticks                                2377029670500                       # Number of ticks simulated
 final_tick                               2377029670500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1359798                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1465373                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2100575394                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 311664                       # Number of bytes of host memory used
-host_seconds                                  1131.61                       # Real time elapsed on the host
+host_inst_rate                                1373046                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1479650                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2121040557                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 312336                       # Number of bytes of host memory used
+host_seconds                                  1120.69                       # Real time elapsed on the host
 sim_insts                                  1538759602                       # Number of instructions simulated
 sim_ops                                    1658228915                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             39424                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         124870272                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            124909696                       # Number of bytes read from this memory
@@ -36,7 +37,9 @@ system.physmem.bw_total::writebacks          27493190                       # To
 system.physmem.bw_total::cpu.inst               16585                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            52532063                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               80041838                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -66,6 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -95,6 +99,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -124,6 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -154,6 +160,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON    2377029670500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                       4754059341                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -214,6 +221,7 @@ system.cpu.op_class::MemWrite               174847046     10.51%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1664032481                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements           9111140                       # number of replacements
 system.cpu.dcache.tags.tagsinuse          4083.741120                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           618380069                       # Total number of references to valid blocks.
@@ -232,6 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4            1
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses        1264105846                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses       1264105846                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data    447683049                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       447683049                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    170696898                       # number of WriteReq hits
@@ -342,6 +351,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 7                       # number of replacements
 system.cpu.icache.tags.tagsinuse           515.144337                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1544564953                       # Total number of references to valid blocks.
@@ -358,6 +368,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4          606
 system.cpu.icache.tags.occ_task_id_percent::1024     0.308105                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses        3089131820                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses       3089131820                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst   1544564953                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1544564953                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1544564953                       # number of demand (read+write) hits
@@ -426,6 +437,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511
 system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements          1919027                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        31012.105366                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           14386231                       # Total number of references to valid blocks.
@@ -448,6 +460,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26842
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908447                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses        149644904                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses       149644904                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks      3681379                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total      3681379                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks            7                       # number of WritebackClean hits
@@ -594,6 +607,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1151
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1063                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1063                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp       7226725                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty      4702506                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            7                       # Transaction distribution
@@ -626,6 +640,7 @@ system.cpu.toL2Bus.respLayer0.occupancy        957000                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy   13672854000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 2377029670500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp            1169580                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty      1021127                       # Transaction distribution
 system.membus.trans_dist::CleanEvict           897056                       # Transaction distribution