diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/60.bzip2/ref/arm | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm')
4 files changed, 1510 insertions, 1519 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 1df40303a..0b1bb03bc 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.108725 # Number of seconds simulated -sim_ticks 1108725388000 # Number of ticks simulated -final_tick 1108725388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.121241 # Number of seconds simulated +sim_ticks 1121241432500 # Number of ticks simulated +final_tick 1121241432500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160331 # Simulator instruction rate (inst/s) -host_op_rate 172733 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115089854 # Simulator tick rate (ticks/s) -host_mem_usage 301444 # Number of bytes of host memory used -host_seconds 9633.56 # Real time elapsed on the host +host_inst_rate 243175 # Simulator instruction rate (inst/s) +host_op_rate 261985 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 176527853 # Simulator tick rate (ticks/s) +host_mem_usage 312356 # Number of bytes of host memory used +host_seconds 6351.64 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 131507968 # Number of bytes read from this memory -system.physmem.bytes_read::total 131558336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66970688 # Number of bytes written to this memory -system.physmem.bytes_written::total 66970688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2054812 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2055599 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046417 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046417 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 45429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 118611849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 118657277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60403314 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60403314 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60403314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 45429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 118611849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 179060592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2055599 # Number of read requests accepted -system.physmem.writeReqs 1046417 # Number of write requests accepted -system.physmem.readBursts 2055599 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046417 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131472320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue -system.physmem.bytesWritten 66969088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131558336 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66970688 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 50560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 131525952 # Number of bytes read from this memory +system.physmem.bytes_read::total 131576512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66977984 # Number of bytes written to this memory +system.physmem.bytes_written::total 66977984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 790 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2055093 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2055883 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046531 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046531 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 45093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117303864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117348956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45093 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45093 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 59735559 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 59735559 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 59735559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117303864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177084516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2055883 # Number of read requests accepted +system.physmem.writeReqs 1046531 # Number of write requests accepted +system.physmem.readBursts 2055883 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046531 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131490688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 85824 # Total number of bytes read from write queue +system.physmem.bytesWritten 66976384 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131576512 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66977984 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1341 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127971 # Per bank write bursts -system.physmem.perBankRdBursts::1 125115 # Per bank write bursts -system.physmem.perBankRdBursts::2 122192 # Per bank write bursts -system.physmem.perBankRdBursts::3 124223 # Per bank write bursts -system.physmem.perBankRdBursts::4 123351 # Per bank write bursts -system.physmem.perBankRdBursts::5 123340 # Per bank write bursts -system.physmem.perBankRdBursts::6 123758 # Per bank write bursts -system.physmem.perBankRdBursts::7 124120 # Per bank write bursts -system.physmem.perBankRdBursts::8 131994 # Per bank write bursts -system.physmem.perBankRdBursts::9 134060 # Per bank write bursts -system.physmem.perBankRdBursts::10 132574 # Per bank write bursts -system.physmem.perBankRdBursts::11 133683 # Per bank write bursts -system.physmem.perBankRdBursts::12 133864 # Per bank write bursts -system.physmem.perBankRdBursts::13 133891 # Per bank write bursts -system.physmem.perBankRdBursts::14 129793 # Per bank write bursts -system.physmem.perBankRdBursts::15 130326 # Per bank write bursts -system.physmem.perBankWrBursts::0 65785 # Per bank write bursts -system.physmem.perBankWrBursts::1 64106 # Per bank write bursts -system.physmem.perBankWrBursts::2 62369 # Per bank write bursts -system.physmem.perBankWrBursts::3 62872 # Per bank write bursts -system.physmem.perBankWrBursts::4 62855 # Per bank write bursts -system.physmem.perBankWrBursts::5 62943 # Per bank write bursts -system.physmem.perBankWrBursts::6 64256 # Per bank write bursts -system.physmem.perBankWrBursts::7 65177 # Per bank write bursts -system.physmem.perBankWrBursts::8 67064 # Per bank write bursts -system.physmem.perBankWrBursts::9 67603 # Per bank write bursts -system.physmem.perBankWrBursts::10 67361 # Per bank write bursts -system.physmem.perBankWrBursts::11 67637 # Per bank write bursts -system.physmem.perBankWrBursts::12 67067 # Per bank write bursts -system.physmem.perBankWrBursts::13 67487 # Per bank write bursts -system.physmem.perBankWrBursts::14 66154 # Per bank write bursts -system.physmem.perBankWrBursts::15 65656 # Per bank write bursts +system.physmem.perBankRdBursts::0 127988 # Per bank write bursts +system.physmem.perBankRdBursts::1 125250 # Per bank write bursts +system.physmem.perBankRdBursts::2 122092 # Per bank write bursts +system.physmem.perBankRdBursts::3 124158 # Per bank write bursts +system.physmem.perBankRdBursts::4 123330 # Per bank write bursts +system.physmem.perBankRdBursts::5 123315 # Per bank write bursts +system.physmem.perBankRdBursts::6 123951 # Per bank write bursts +system.physmem.perBankRdBursts::7 124319 # Per bank write bursts +system.physmem.perBankRdBursts::8 132052 # Per bank write bursts +system.physmem.perBankRdBursts::9 134015 # Per bank write bursts +system.physmem.perBankRdBursts::10 132327 # Per bank write bursts +system.physmem.perBankRdBursts::11 133706 # Per bank write bursts +system.physmem.perBankRdBursts::12 133817 # Per bank write bursts +system.physmem.perBankRdBursts::13 133969 # Per bank write bursts +system.physmem.perBankRdBursts::14 129938 # Per bank write bursts +system.physmem.perBankRdBursts::15 130315 # Per bank write bursts +system.physmem.perBankWrBursts::0 65788 # Per bank write bursts +system.physmem.perBankWrBursts::1 64148 # Per bank write bursts +system.physmem.perBankWrBursts::2 62323 # Per bank write bursts +system.physmem.perBankWrBursts::3 62858 # Per bank write bursts +system.physmem.perBankWrBursts::4 62842 # Per bank write bursts +system.physmem.perBankWrBursts::5 62926 # Per bank write bursts +system.physmem.perBankWrBursts::6 64344 # Per bank write bursts +system.physmem.perBankWrBursts::7 65270 # Per bank write bursts +system.physmem.perBankWrBursts::8 67114 # Per bank write bursts +system.physmem.perBankWrBursts::9 67597 # Per bank write bursts +system.physmem.perBankWrBursts::10 67253 # Per bank write bursts +system.physmem.perBankWrBursts::11 67655 # Per bank write bursts +system.physmem.perBankWrBursts::12 67032 # Per bank write bursts +system.physmem.perBankWrBursts::13 67505 # Per bank write bursts +system.physmem.perBankWrBursts::14 66189 # Per bank write bursts +system.physmem.perBankWrBursts::15 65662 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1108725299500 # Total gap between requests +system.physmem.totGap 1121241338000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2055599 # Read request sizes (log2) +system.physmem.readPktSize::6 2055883 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046417 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1922438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046531 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1926751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,104 +193,105 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1917383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.495400 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.766538 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.134212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1491936 77.81% 77.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 306042 15.96% 93.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52771 2.75% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21239 1.11% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13137 0.69% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7295 0.38% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5316 0.28% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4195 0.22% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15452 0.81% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1917383 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60970 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.645219 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 157.122880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60927 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1919691 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.383938 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.729389 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 124.654868 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1494811 77.87% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305161 15.90% 93.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53151 2.77% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21323 1.11% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13050 0.68% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7398 0.39% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5428 0.28% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5020 0.26% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14349 0.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1919691 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60985 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.641650 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.664141 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60945 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60970 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60970 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.162408 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.127431 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.097398 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27276 44.74% 44.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1165 1.91% 46.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28420 46.61% 93.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3653 5.99% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 385 0.63% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 61 0.10% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 7 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60970 # Writes before turning the bus around for reads -system.physmem.totQLat 38268969000 # Total ticks spent queuing -system.physmem.totMemAccLat 76786250250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10271275000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18629.12 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60985 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60985 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.160056 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.125150 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.096252 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27287 44.74% 44.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1323 2.17% 46.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28176 46.20% 93.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3806 6.24% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 330 0.54% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 51 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60985 # Writes before turning the bus around for reads +system.physmem.totQLat 38434565750 # Total ticks spent queuing +system.physmem.totMemAccLat 76957228250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10272710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18707.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37379.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 118.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 60.40 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 118.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.40 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37457.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 117.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 59.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 117.35 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 59.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.40 # Data bus utilization in percentage -system.physmem.busUtilRead 0.93 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.38 # Data bus utilization in percentage +system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing -system.physmem.readRowHits 776845 # Number of row buffer hits during reads -system.physmem.writeRowHits 406412 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.84 # Row buffer hit rate for writes -system.physmem.avgGap 357420.88 # Average gap between requests -system.physmem.pageHitRate 38.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7070973840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3858170250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7753512000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3307152240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 416204777970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 300142086750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 810753074250 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.249224 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 496624730250 # Time in different power states -system.physmem_0.memoryStateTime::REF 37022700000 # Time in different power states +system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing +system.physmem.readRowHits 774810 # Number of row buffer hits during reads +system.physmem.writeRowHits 406537 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes +system.physmem.avgGap 361409.32 # Average gap between requests +system.physmem.pageHitRate 38.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7080832080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3863549250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7756031400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3308033520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 73233657120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 422818284195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301848259500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 819908647065 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.254419 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 499427924250 # Time in different power states +system.physmem_0.memoryStateTime::REF 37440520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 575075912250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 584369735750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7424434080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4051030500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8269419600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3473467920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 425140731810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 292303530750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 813079015860 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.347080 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 483537101750 # Time in different power states -system.physmem_1.memoryStateTime::REF 37022700000 # Time in different power states +system.physmem_1.actEnergy 7432016760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4055167875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8269029600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3473325360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 73233657120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 431345081205 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 294368613000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 822176890920 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.277404 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 486933261750 # Time in different power states +system.physmem_1.memoryStateTime::REF 37440520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 588165429250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 596864300250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 240158127 # Number of BP lookups -system.cpu.branchPred.condPredicted 186758642 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14604059 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 133657061 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122306338 # Number of BTB hits +system.cpu.branchPred.lookups 240141363 # Number of BP lookups +system.cpu.branchPred.condPredicted 186745178 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14595264 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132286201 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122283419 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.507577 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15659556 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.438530 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15659523 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -410,90 +411,90 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2217450776 # number of cpu cycles simulated +system.cpu.numCycles 2242482865 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563087 # Number of instructions committed system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed -system.cpu.discardedOps 40093383 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 40063389 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.435649 # CPI: cycles per instruction -system.cpu.ipc 0.696549 # IPC: instructions per cycle -system.cpu.tickCycles 1838812013 # Number of cycles that the object actually ticked -system.cpu.idleCycles 378638763 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9223724 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.606596 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624087400 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9227820 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.631076 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.606596 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997463 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy +system.cpu.cpi 1.451856 # CPI: cycles per instruction +system.cpu.ipc 0.688774 # IPC: instructions per cycle +system.cpu.tickCycles 1838984641 # Number of cycles that the object actually ticked +system.cpu.idleCycles 403498224 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9223361 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.642530 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624067003 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9227457 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.631527 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9813070000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642530 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997471 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1296 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2482 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1217 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276555670 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276555670 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453740634 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453740634 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170346644 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170346644 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276544027 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276544027 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453735354 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453735354 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331527 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331527 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624087278 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624087278 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624087278 # number of overall hits -system.cpu.dcache.overall_hits::total 624087278 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7337122 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7337122 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2239403 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2239403 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9576525 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9576525 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9576525 # number of overall misses -system.cpu.dcache.overall_misses::total 9576525 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 183400270746 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183400270746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 101399706750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 101399706750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 284799977496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 284799977496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 284799977496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 284799977496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461077756 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461077756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 624066881 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624066881 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624066881 # number of overall hits +system.cpu.dcache.overall_hits::total 624066881 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7336762 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7336762 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254520 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254520 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9591282 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9591282 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9591282 # number of overall misses +system.cpu.dcache.overall_misses::total 9591282 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442349996 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 192442349996 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711138250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109711138250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 302153488246 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 302153488246 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 302153488246 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 302153488246 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461072116 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461072116 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633663803 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633663803 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633663803 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633663803 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012976 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015113 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015113 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015113 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015113 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24996.213876 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24996.213876 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45279.794101 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45279.794101 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29739.386416 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29739.386416 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 633658163 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633658163 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633658163 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633658163 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015912 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015912 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013063 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013063 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015136 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015136 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015136 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015136 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.874977 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.874977 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48662.747835 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48662.747835 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31502.930291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31502.930291 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,101 +503,101 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3701129 # number of writebacks -system.cpu.dcache.writebacks::total 3701129 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 221 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 348484 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 348484 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 348705 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348705 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 348705 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348705 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336901 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7336901 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890919 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890919 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9227820 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9227820 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9227820 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9227820 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168309061254 # 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Number of misses that were no-allocate -system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.153981 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466170177 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 568500.215854 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 32 # number of replacements +system.cpu.icache.tags.tagsinuse 661.433391 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466139352 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 566390.464156 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.153981 # 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Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932342814 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932342814 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 466170177 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466170177 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466170177 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466170177 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466170177 # number of overall hits -system.cpu.icache.overall_hits::total 466170177 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 820 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71171.035366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71171.035366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71171.035366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77419.196841 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77419.196841 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77419.196841 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77419.196841 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62148501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 62148501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62148501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 62148501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62148501 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 62148501 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68781.403659 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68781.403659 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68781.403659 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68781.403659 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68781.403659 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68781.403659 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75514.582017 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75514.582017 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2022895 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31254.140512 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8985448 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2052670 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.377444 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 59502848750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14999.285776 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2055883 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51087500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93955002000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006089500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459125500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459125500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51087500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414127500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 154465215000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51087500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414127500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 154465215000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171054 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171142 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423156 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423156 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222781 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222781 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64667.721519 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74867.764828 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.347847 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.022721 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.022721 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7337721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7337721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3701129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890919 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156769 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22158409 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827452736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827505216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7337377 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7337377 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3701040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890903 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890903 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1646 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22155954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22157600 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827423808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827476480 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12929769 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12929320 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 12929769 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 12929320 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12929769 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10166013500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12929320 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10165700000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1389749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1400999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14186681246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14190167496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1255503 # Transaction distribution -system.membus.trans_dist::ReadResp 1255503 # Transaction distribution -system.membus.trans_dist::Writeback 1046417 # Transaction distribution -system.membus.trans_dist::ReadExReq 800096 # Transaction distribution -system.membus.trans_dist::ReadExResp 800096 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157615 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5157615 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198529024 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198529024 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1255736 # Transaction distribution +system.membus.trans_dist::ReadResp 1255736 # Transaction distribution +system.membus.trans_dist::Writeback 1046531 # Transaction distribution +system.membus.trans_dist::ReadExReq 800147 # Transaction distribution +system.membus.trans_dist::ReadExResp 800147 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158297 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5158297 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198554496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198554496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3102016 # Request fanout histogram +system.membus.snoop_fanout::samples 3102414 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3102016 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3102414 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3102016 # Request fanout histogram -system.membus.reqLayer0.occupancy 12126859000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 19430032500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.8 # Layer utilization (%) +system.membus.snoop_fanout::total 3102414 # Request fanout histogram +system.membus.reqLayer0.occupancy 7944829000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 11243795500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 2039a5a26..d3007a8e0 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.756343 # Number of seconds simulated -sim_ticks 756342731500 # Number of ticks simulated -final_tick 756342731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.771783 # Number of seconds simulated +sim_ticks 771782683000 # Number of ticks simulated +final_tick 771782683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137786 # Simulator instruction rate (inst/s) -host_op_rate 148444 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67471289 # Simulator tick rate (ticks/s) -host_mem_usage 311496 # Number of bytes of host memory used -host_seconds 11209.85 # Real time elapsed on the host +host_inst_rate 141348 # Simulator instruction rate (inst/s) +host_op_rate 152281 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70628369 # Simulator tick rate (ticks/s) +host_mem_usage 310548 # Number of bytes of host memory used +host_seconds 10927.38 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1664032415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 238887296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63148480 # Number of bytes read from this memory -system.physmem.bytes_read::total 302102080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104863424 # Number of bytes written to this memory -system.physmem.bytes_written::total 104863424 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3732614 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 986695 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4720345 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1638491 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1638491 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 87664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 315845299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 83491885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 399424847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 87664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 87664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 138645378 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 138645378 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 138645378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 87664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 315845299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 83491885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 538070225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4720345 # Number of read requests accepted -system.physmem.writeReqs 1638491 # Number of write requests accepted -system.physmem.readBursts 4720345 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1638491 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 301644480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 457600 # Total number of bytes read from write queue -system.physmem.bytesWritten 104860480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 302102080 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104863424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7150 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 66112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 238756480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63336128 # Number of bytes read from this memory +system.physmem.bytes_read::total 302158720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104900608 # Number of bytes written to this memory +system.physmem.bytes_written::total 104900608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1033 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3730570 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 989627 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4721230 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1639072 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1639072 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 85661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309357135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82064718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 391507515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 85661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 135919878 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 135919878 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 135919878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 85661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309357135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82064718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 527427392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4721230 # Number of read requests accepted +system.physmem.writeReqs 1639072 # Number of write requests accepted +system.physmem.readBursts 4721230 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1639072 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 301708544 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 450176 # Total number of bytes read from write queue +system.physmem.bytesWritten 104898432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 302158720 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104900608 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7034 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 296862 # Per bank write bursts -system.physmem.perBankRdBursts::1 294626 # Per bank write bursts -system.physmem.perBankRdBursts::2 288270 # Per bank write bursts -system.physmem.perBankRdBursts::3 292812 # Per bank write bursts -system.physmem.perBankRdBursts::4 290199 # Per bank write bursts -system.physmem.perBankRdBursts::5 289793 # Per bank write bursts -system.physmem.perBankRdBursts::6 284872 # Per bank write bursts -system.physmem.perBankRdBursts::7 281493 # Per bank write bursts -system.physmem.perBankRdBursts::8 297311 # Per bank write bursts -system.physmem.perBankRdBursts::9 303290 # Per bank write bursts -system.physmem.perBankRdBursts::10 295469 # Per bank write bursts -system.physmem.perBankRdBursts::11 301855 # Per bank write bursts -system.physmem.perBankRdBursts::12 303298 # Per bank write bursts -system.physmem.perBankRdBursts::13 302373 # Per bank write bursts -system.physmem.perBankRdBursts::14 297652 # Per bank write bursts -system.physmem.perBankRdBursts::15 293020 # Per bank write bursts -system.physmem.perBankWrBursts::0 104131 # Per bank write bursts -system.physmem.perBankWrBursts::1 101826 # Per bank write bursts -system.physmem.perBankWrBursts::2 99098 # Per bank write bursts -system.physmem.perBankWrBursts::3 99979 # Per bank write bursts -system.physmem.perBankWrBursts::4 99438 # Per bank write bursts -system.physmem.perBankWrBursts::5 99115 # Per bank write bursts -system.physmem.perBankWrBursts::6 102674 # Per bank write bursts -system.physmem.perBankWrBursts::7 104427 # Per bank write bursts -system.physmem.perBankWrBursts::8 105209 # Per bank write bursts -system.physmem.perBankWrBursts::9 104570 # Per bank write bursts -system.physmem.perBankWrBursts::10 102342 # Per bank write bursts -system.physmem.perBankWrBursts::11 102683 # Per bank write bursts -system.physmem.perBankWrBursts::12 102787 # Per bank write bursts -system.physmem.perBankWrBursts::13 102808 # Per bank write bursts -system.physmem.perBankWrBursts::14 104630 # Per bank write bursts -system.physmem.perBankWrBursts::15 102728 # Per bank write bursts +system.physmem.perBankRdBursts::0 296496 # Per bank write bursts +system.physmem.perBankRdBursts::1 294922 # Per bank write bursts +system.physmem.perBankRdBursts::2 288553 # Per bank write bursts +system.physmem.perBankRdBursts::3 293200 # Per bank write bursts +system.physmem.perBankRdBursts::4 290519 # Per bank write bursts +system.physmem.perBankRdBursts::5 289057 # Per bank write bursts +system.physmem.perBankRdBursts::6 284695 # Per bank write bursts +system.physmem.perBankRdBursts::7 280747 # Per bank write bursts +system.physmem.perBankRdBursts::8 297891 # Per bank write bursts +system.physmem.perBankRdBursts::9 303659 # Per bank write bursts +system.physmem.perBankRdBursts::10 295750 # Per bank write bursts +system.physmem.perBankRdBursts::11 302488 # Per bank write bursts +system.physmem.perBankRdBursts::12 303486 # Per bank write bursts +system.physmem.perBankRdBursts::13 302338 # Per bank write bursts +system.physmem.perBankRdBursts::14 297681 # Per bank write bursts +system.physmem.perBankRdBursts::15 292714 # Per bank write bursts +system.physmem.perBankWrBursts::0 104090 # Per bank write bursts +system.physmem.perBankWrBursts::1 102136 # Per bank write bursts +system.physmem.perBankWrBursts::2 99204 # Per bank write bursts +system.physmem.perBankWrBursts::3 100079 # Per bank write bursts +system.physmem.perBankWrBursts::4 99319 # Per bank write bursts +system.physmem.perBankWrBursts::5 99058 # Per bank write bursts +system.physmem.perBankWrBursts::6 102867 # Per bank write bursts +system.physmem.perBankWrBursts::7 104266 # Per bank write bursts +system.physmem.perBankWrBursts::8 105488 # Per bank write bursts +system.physmem.perBankWrBursts::9 104503 # Per bank write bursts +system.physmem.perBankWrBursts::10 102301 # Per bank write bursts +system.physmem.perBankWrBursts::11 102956 # Per bank write bursts +system.physmem.perBankWrBursts::12 103260 # Per bank write bursts +system.physmem.perBankWrBursts::13 102520 # Per bank write bursts +system.physmem.perBankWrBursts::14 104484 # Per bank write bursts +system.physmem.perBankWrBursts::15 102507 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 756342591500 # Total gap between requests +system.physmem.totGap 771782536000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4720345 # Read request sizes (log2) +system.physmem.readPktSize::6 4721230 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1638491 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2764600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1036830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 329452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 239558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 162691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 91104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 40419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1639072 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2775597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1044443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 331745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 234202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 153941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 85295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 39428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,38 +148,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 59650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 74848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 91913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 98459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 106253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 107840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 108834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 109988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 110978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 113431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 107071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 104798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 103128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 22873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 60114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 75847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 110847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 113228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 106323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 103422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -197,123 +197,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4285614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.853108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.948636 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 101.693693 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3410667 79.58% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 676414 15.78% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 97051 2.26% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35005 0.82% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22710 0.53% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12276 0.29% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7200 0.17% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5155 0.12% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19136 0.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4285614 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98802 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.703225 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 32.303831 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 97.301104 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-127 94981 96.13% 96.13% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-255 1362 1.38% 97.51% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-383 759 0.77% 98.28% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-511 434 0.44% 98.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-639 380 0.38% 99.10% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-767 348 0.35% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-895 273 0.28% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::896-1023 148 0.15% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1151 67 0.07% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1152-1279 20 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1407 9 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1408-1535 8 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1663 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4289012 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.801701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.923105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 101.558340 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3414847 79.62% 79.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 675748 15.76% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96615 2.25% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35482 0.83% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22807 0.53% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12154 0.28% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7173 0.17% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5164 0.12% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19022 0.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4289012 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98837 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.696531 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 32.309771 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 98.301255 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 95044 96.16% 96.16% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1344 1.36% 97.52% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-383 770 0.78% 98.30% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 419 0.42% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 374 0.38% 99.10% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 356 0.36% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 254 0.26% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 146 0.15% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 62 0.06% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 41 0.04% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 8 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 7 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1663 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1920-2047 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2687 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-2943 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98802 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98802 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.583116 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.550078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.089696 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 73349 74.24% 74.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1793 1.81% 76.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18295 18.52% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3696 3.74% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 920 0.93% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 398 0.40% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 161 0.16% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 94 0.10% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 50 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 24 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 14 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98802 # Writes before turning the bus around for reads -system.physmem.totQLat 132475907765 # Total ticks spent queuing -system.physmem.totMemAccLat 220848314015 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23565975000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28107.45 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2687 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3200-3327 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 98837 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98837 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.583243 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.550199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.089458 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 73410 74.27% 74.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1674 1.69% 75.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18461 18.68% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3603 3.65% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 928 0.94% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 388 0.39% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 174 0.18% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 100 0.10% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 61 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 27 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 98837 # Writes before turning the bus around for reads +system.physmem.totQLat 132409571838 # Total ticks spent queuing +system.physmem.totMemAccLat 220800746838 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23570980000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28087.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46857.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 398.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 138.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 399.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 138.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46837.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 390.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 135.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 391.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 135.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.20 # Data bus utilization in percentage -system.physmem.busUtilRead 3.12 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.08 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing -system.physmem.readRowHits 1712938 # Number of row buffer hits during reads -system.physmem.writeRowHits 353078 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.55 # Row buffer hit rate for writes -system.physmem.avgGap 118943.56 # Average gap between requests -system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16066436400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8766408750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18087404400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5253193440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 400853320515 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 102178887750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 600606152535 # Total energy per rank (pJ) -system.physmem_0.averagePower 794.094387 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 167492103071 # Time in different power states -system.physmem_0.memoryStateTime::REF 25255880000 # Time in different power states +system.physmem.busUtil 4.12 # Data bus utilization in percentage +system.physmem.busUtilRead 3.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing +system.physmem.readRowHits 1710867 # Number of row buffer hits during reads +system.physmem.writeRowHits 353347 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.56 # Row buffer hit rate for writes +system.physmem.avgGap 121343.69 # Average gap between requests +system.physmem.pageHitRate 32.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16078381200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8772926250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18081671400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5255351280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 410988240855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 102552687000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 612138233745 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.150023 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 168058001250 # Time in different power states +system.physmem_0.memoryStateTime::REF 25771460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 563593117929 # Time in different power states +system.physmem_0.memoryStateTime::ACT 577951698750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16332729840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8911707750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18675259200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5363826480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 402415744095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100808340750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 601908109395 # Total energy per rank (pJ) -system.physmem_1.averagePower 795.815775 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165215512876 # Time in different power states -system.physmem_1.memoryStateTime::REF 25255880000 # Time in different power states +system.physmem_1.actEnergy 16346489040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8919215250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18688846800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5365504800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 412404849315 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 101310048000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 613443928965 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.841817 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165993972457 # Time in different power states +system.physmem_1.memoryStateTime::REF 25771460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 565869633374 # Time in different power states +system.physmem_1.memoryStateTime::ACT 580015821043 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286251205 # Number of BP lookups -system.cpu.branchPred.condPredicted 223383370 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14630986 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158738952 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150334108 # Number of BTB hits +system.cpu.branchPred.lookups 286268512 # Number of BP lookups +system.cpu.branchPred.condPredicted 223399208 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631885 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157652290 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150341382 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.705242 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16640646 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.362638 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16641174 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -432,233 +430,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1512685464 # number of cpu cycles simulated +system.cpu.numCycles 1543565367 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13925295 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067334861 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286251205 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166974754 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1484044715 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29286501 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 170 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1090 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656878260 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 961 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1512614520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.464203 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.224459 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13925779 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067423618 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286268512 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166982556 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1514915602 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29288421 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 919 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656914213 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 942 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1543486763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.434983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229356 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 430302331 28.45% 28.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465370544 30.77% 59.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101420857 6.71% 65.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515520788 34.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 461116597 29.87% 29.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465422138 30.15% 60.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101389056 6.57% 66.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515558972 33.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1512614520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.189234 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.366665 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74740374 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 515177494 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849893259 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58160845 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14642548 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42195150 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2036986769 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52385989 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14642548 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139815435 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 436624028 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12701 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837804287 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 83715521 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976173031 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26689335 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45146280 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125414 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1394915 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22818803 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985649062 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9127137269 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432583454 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 143 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1543486763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185459 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.339382 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74615169 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 546131714 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 850052649 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58043724 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14643507 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42202613 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037139109 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52472329 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14643507 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139680975 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 464946049 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14177 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837873228 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86328827 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976320354 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26732336 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45128593 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125639 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1500891 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25518898 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985788047 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9127865226 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432787425 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 124 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310750117 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 155 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111721700 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542489680 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199288909 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26826914 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28715919 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947778041 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857580897 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13541153 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 279193675 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 645796508 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1512614520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.228060 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150014 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 310889102 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 151 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 141 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111344488 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542536301 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199301557 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26908887 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29198248 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947883742 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 210 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857409514 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13500100 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 279518916 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 646881302 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1543486763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.203385 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151093 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 560160519 37.03% 37.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325201183 21.50% 58.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378431439 25.02% 83.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219774852 14.53% 98.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29040355 1.92% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6172 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 590762659 38.27% 38.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325764931 21.11% 59.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378272466 24.51% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219653351 14.23% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29027182 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6174 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1512614520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1543486763 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166509117 41.02% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1974 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191277328 47.12% 88.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 48123931 11.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166053840 40.99% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1992 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191416352 47.25% 88.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47630536 11.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138363415 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801029 0.04% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532094788 28.64% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186321614 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138248479 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801009 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 26 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532044411 28.64% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186315567 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857580897 # Type of FU issued -system.cpu.iq.rate 1.228002 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405912350 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218517 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5647229580 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2226984572 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805831958 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2263493115 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17832338 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857409514 # Type of FU issued +system.cpu.iq.rate 1.203324 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405102720 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218101 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5676908390 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2227415601 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805707256 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 208 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262512110 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 124 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17814082 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84183346 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66238 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13114 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24441864 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84229967 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66402 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13168 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24454512 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4579390 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4849629 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4520775 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4802645 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14642548 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25281228 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1183865 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947778336 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14643507 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25316113 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1330365 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947884031 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542489680 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199288909 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 152 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 158613 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1024253 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13114 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7709445 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8723908 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16433353 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827918594 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516926976 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29662303 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542536301 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199301557 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 148 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 158933 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1170467 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13168 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7700956 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8705023 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16405979 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827745758 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516865735 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29663756 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 81 # number of nop insts executed -system.cpu.iew.exec_refs 698686621 # number of memory reference insts executed -system.cpu.iew.exec_branches 229598858 # Number of branches executed -system.cpu.iew.exec_stores 181759645 # Number of stores executed -system.cpu.iew.exec_rate 1.208393 # Inst execution rate -system.cpu.iew.wb_sent 1808851456 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805832027 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169265268 # num instructions producing a value -system.cpu.iew.wb_consumers 1689455879 # num instructions consuming a value +system.cpu.iew.exec_nop 79 # number of nop insts executed +system.cpu.iew.exec_refs 698617938 # number of memory reference insts executed +system.cpu.iew.exec_branches 229554698 # Number of branches executed +system.cpu.iew.exec_stores 181752203 # Number of stores executed +system.cpu.iew.exec_rate 1.184106 # Inst execution rate +system.cpu.iew.wb_sent 1808737138 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805707322 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169287953 # num instructions producing a value +system.cpu.iew.wb_consumers 1689671414 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.193792 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back +system.cpu.iew.wb_rate 1.169829 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692021 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 257820227 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 257958644 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14630284 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1473146552 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.129577 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.040655 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14631182 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1504006174 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.106400 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.024308 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 893288218 60.64% 60.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250810214 17.03% 77.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 109558722 7.44% 85.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55058301 3.74% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29206870 1.98% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 33934631 2.30% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24884814 1.69% 94.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18117903 1.23% 96.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58286879 3.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 923727407 61.42% 61.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250637926 16.66% 78.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110048306 7.32% 85.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55269063 3.67% 89.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29308073 1.95% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34102690 2.27% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24713726 1.64% 94.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18129256 1.21% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58069727 3.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1473146552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1504006174 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -704,77 +702,77 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction -system.cpu.commit.bw_lim_events 58286879 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 58069727 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3336711734 # The number of ROB reads -system.cpu.rob.rob_writes 3883178493 # The number of ROB writes -system.cpu.timesIdled 871 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 70944 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3367926925 # The number of ROB reads +system.cpu.rob.rob_writes 3883468057 # The number of ROB writes +system.cpu.timesIdled 846 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 78604 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.979361 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.979361 # CPI: Total CPI of All Threads -system.cpu.ipc 1.021073 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.021073 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175874054 # number of integer regfile reads -system.cpu.int_regfile_writes 1261590215 # number of integer regfile writes +system.cpu.cpi 0.999354 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.999354 # CPI: Total CPI of All Threads +system.cpu.ipc 1.000646 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.000646 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175695472 # number of integer regfile reads +system.cpu.int_regfile_writes 1261559121 # number of integer regfile writes system.cpu.fp_regfile_reads 38 # number of floating regfile reads -system.cpu.fp_regfile_writes 51 # number of floating regfile writes -system.cpu.cc_regfile_reads 6966029517 # number of cc regfile reads -system.cpu.cc_regfile_writes 551971474 # number of cc regfile writes -system.cpu.misc_regfile_reads 675853074 # number of misc regfile reads +system.cpu.fp_regfile_writes 48 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965502930 # number of cc regfile reads +system.cpu.cc_regfile_writes 551873305 # number of cc regfile writes +system.cpu.misc_regfile_reads 675842878 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17007297 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.963762 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638259274 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17007809 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.527425 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 79888000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.963762 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 17005493 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964646 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638183172 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17006005 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.526931 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 79063000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964646 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 405 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335624835 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335624835 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469463783 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469463783 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168795373 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168795373 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335677307 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335677307 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469397613 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469397613 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168785441 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168785441 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638259156 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638259156 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638259156 # number of overall hits -system.cpu.dcache.overall_hits::total 638259156 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17258559 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17258559 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3790674 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3790674 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638183054 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638183054 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638183054 # number of overall hits +system.cpu.dcache.overall_hits::total 638183054 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17351867 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17351867 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3800606 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3800606 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21049233 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21049233 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21049235 # number of overall misses -system.cpu.dcache.overall_misses::total 21049235 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 392276819281 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 392276819281 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 143202458834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 143202458834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 535479278115 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 535479278115 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 535479278115 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 535479278115 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486722342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486722342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21152473 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21152473 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21152475 # number of overall misses +system.cpu.dcache.overall_misses::total 21152475 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 417182903209 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 417182903209 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149917932873 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149917932873 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 358750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 567100836082 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 567100836082 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 567100836082 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 567100836082 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486749480 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486749480 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -783,421 +781,419 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659308389 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659308389 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659308391 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659308391 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035459 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035459 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021964 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.021964 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659335527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659335527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659335529 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659335529 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035648 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035648 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022022 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022022 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.031926 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.031926 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.031926 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.031926 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22729.407437 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22729.407437 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37777.571702 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37777.571702 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25439.372452 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25439.372452 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25439.370035 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25439.370035 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19976216 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2938205 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1014245 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 66761 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.695651 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44.010800 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.032082 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032082 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032082 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032082 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24042.536933 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24042.536933 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39445.797032 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39445.797032 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 89687.500000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 89687.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26810.143480 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26810.143480 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26810.140945 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26810.140945 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20723795 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3315809 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 944207 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67033 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.948360 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49.465323 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4837992 # number of writebacks -system.cpu.dcache.writebacks::total 4837992 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2988204 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2988204 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1053221 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1053221 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 4835251 # number of writebacks +system.cpu.dcache.writebacks::total 4835251 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3083373 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3083373 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1063096 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1063096 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4041425 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4041425 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4041425 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4041425 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270355 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14270355 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737453 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737453 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4146469 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4146469 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4146469 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4146469 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268494 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14268494 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737510 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737510 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17007808 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17007808 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17007809 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17007809 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 303479537034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 303479537034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 110174073244 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 110174073244 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 413653610278 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 413653610278 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 413653672278 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 413653672278 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029319 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029319 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015861 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015861 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 17006004 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17006004 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17006005 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17006005 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 329072767985 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 329072767985 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115107857313 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 115107857313 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 67750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 67750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444180625298 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 444180625298 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444180693048 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 444180693048 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029314 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029314 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025796 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025796 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21266.432197 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21266.432197 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40246.927799 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40246.927799 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24321.394637 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24321.394637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24321.396852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24321.396852 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025793 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025793 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23062.894233 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23062.894233 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42048.378750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42048.378750 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67750 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67750 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26119.047443 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26119.047443 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26119.049891 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26119.049891 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 591 # number of replacements -system.cpu.icache.tags.tagsinuse 445.749905 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656876635 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1079 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 608782.794254 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 588 # number of replacements +system.cpu.icache.tags.tagsinuse 446.068543 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656912599 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 610513.567844 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 445.749905 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.870605 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.870605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 446.068543 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.871228 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.871228 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313757597 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313757597 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656876635 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656876635 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656876635 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656876635 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656876635 # number of overall hits -system.cpu.icache.overall_hits::total 656876635 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1624 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1624 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1624 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1624 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1624 # number of overall misses -system.cpu.icache.overall_misses::total 1624 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 95182738 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 95182738 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 95182738 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 95182738 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 95182738 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 95182738 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656878259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656878259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656878259 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656878259 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656878259 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656878259 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313829498 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313829498 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656912599 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656912599 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656912599 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656912599 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656912599 # number of overall hits +system.cpu.icache.overall_hits::total 656912599 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1612 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1612 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1612 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1612 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1612 # number of overall misses +system.cpu.icache.overall_misses::total 1612 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 102924516 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 102924516 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 102924516 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 102924516 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 102924516 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 102924516 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656914211 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656914211 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656914211 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656914211 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656914211 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656914211 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58610.060345 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58610.060345 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58610.060345 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58610.060345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58610.060345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58610.060345 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 15932 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 279 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 193 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 82.549223 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 39.857143 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63848.955335 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63848.955335 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63848.955335 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63848.955335 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17306 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 93.043011 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 38.375000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 545 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 545 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 545 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 545 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 545 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 545 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1079 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1079 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1079 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1079 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1079 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1079 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69657739 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 69657739 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69657739 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 69657739 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69657739 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 69657739 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 536 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 536 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 536 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76203217 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 76203217 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76203217 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 76203217 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76203217 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 76203217 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64557.682113 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64557.682113 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64557.682113 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64557.682113 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64557.682113 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64557.682113 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70820.833643 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70820.833643 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 10957108 # 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number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 39731 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 39731 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1033 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2748196 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2749229 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993723 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 993723 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981763 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 981763 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1033 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3729959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3730992 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1033 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3729959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993723 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4724715 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66585771 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 212846915589 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212913501360 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 71046693133 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 91372170669 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 91372170669 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66585771 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304219086258 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 304285672029 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66585771 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304219086258 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 375332365162 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192664 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358524 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358524 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.219377 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358628 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358628 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.219379 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.277771 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57885.859073 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70417.702439 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70412.981182 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69007.892781 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89081.022602 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89081.022602 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75323.218263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73995.579018 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.277809 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64458.636012 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77449.685390 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77444.804111 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71495.470199 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93069.478753 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93069.478753 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81556.238134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79440.212830 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 14271401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 14271401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4837992 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1352607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737487 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2158 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38853610 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 38855768 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1398131264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1398200320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1352607 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23199492 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.058303 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.234316 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 14269530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 14269530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4835251 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1300143 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737551 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38847261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 38849413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397840384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1397909248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1300143 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 23142477 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.056180 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.230269 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 21846885 94.17% 94.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 1352607 5.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 21842334 94.38% 94.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 1300143 5.62% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23199492 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15761436995 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1798250 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 23142477 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15756418748 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1812271 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 26002804288 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 26100835834 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3738412 # Transaction distribution -system.membus.trans_dist::ReadResp 3738412 # Transaction distribution -system.membus.trans_dist::Writeback 1638491 # Transaction distribution -system.membus.trans_dist::ReadExReq 981933 # Transaction distribution -system.membus.trans_dist::ReadExResp 981933 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11079181 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11079181 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406965504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 406965504 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3739202 # Transaction distribution +system.membus.trans_dist::ReadResp 3739202 # Transaction distribution +system.membus.trans_dist::Writeback 1639072 # Transaction distribution +system.membus.trans_dist::ReadExReq 982028 # Transaction distribution +system.membus.trans_dist::ReadExResp 982028 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11081532 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11081532 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407059328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 407059328 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6358836 # Request fanout histogram +system.membus.snoop_fanout::samples 6360302 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6358836 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6360302 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6358836 # Request fanout histogram -system.membus.reqLayer0.occupancy 20942586092 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 44003891862 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 5.8 # Layer utilization (%) +system.membus.snoop_fanout::total 6360302 # Request fanout histogram +system.membus.reqLayer0.occupancy 14493239223 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 25671846860 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index c26ad4c6d..a5246083c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490000 # Number of ticks simulated final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1680600 # Simulator instruction rate (inst/s) -host_op_rate 1810592 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 905297170 # Simulator tick rate (ticks/s) -host_mem_usage 301428 # Number of bytes of host memory used -host_seconds 919.05 # Real time elapsed on the host +host_inst_rate 1937211 # Simulator instruction rate (inst/s) +host_op_rate 2087051 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1043527090 # Simulator tick rate (ticks/s) +host_mem_usage 301332 # Number of bytes of host memory used +host_seconds 797.31 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1664032433 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram -system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram +system.membus.snoop_fanout::mean 2.711106 # Request fanout histogram system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram -system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 627495305 28.89% 28.89% # Request fanout histogram +system.membus.snoop_fanout::3 1544565589 71.11% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 2172060894 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 89012dc1c..893b8aa6f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.363671 # Number of seconds simulated -sim_ticks 2363670998000 # Number of ticks simulated -final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.363663 # Number of seconds simulated +sim_ticks 2363662966500 # Number of ticks simulated +final_tick 2363662966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1113267 # Simulator instruction rate (inst/s) -host_op_rate 1199701 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1710076181 # Simulator tick rate (ticks/s) -host_mem_usage 309628 # Number of bytes of host memory used -host_seconds 1382.20 # Real time elapsed on the host +host_inst_rate 1021163 # Simulator instruction rate (inst/s) +host_op_rate 1100446 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1568591191 # Simulator tick rate (ticks/s) +host_mem_usage 309800 # Number of bytes of host memory used +host_seconds 1506.87 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1658228914 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,16 +26,16 @@ system.physmem.num_reads::total 1958774 # Nu system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53020297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53036976 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 27542282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27542282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27542282 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53020297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80579258 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4727341996 # number of cpu cycles simulated +system.cpu.numCycles 4727325933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759601 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 633153380 # nu system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4727341995.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4727325932.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 213462426 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032480 # Class of executed instruction system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.733675 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 25164658000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733675 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143400508500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143400508500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57355969000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57355969000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200756477500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200756477500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200756477500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200756477500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19844.838340 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19844.838340 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30360.743912 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30360.743912 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22024.278858 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22024.278858 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22024.276442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22024.276442 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132561379500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 132561379500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54522245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 54522245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187083625000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 187083625000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187083678500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 187083678500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18344.838340 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18344.838340 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28860.743912 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28860.743912 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20524.278858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20524.278858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20524.282476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20524.282476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.012767 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 515.012767 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id @@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34207000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34207000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34207000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34207000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34207000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34207000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses @@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53615.987461 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53615.987461 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53615.987461 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53615.987461 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -411,37 +411,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33250000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33250000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33250000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33250000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33250000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33250000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52115.987461 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52115.987461 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1926075 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31008.535045 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 150067842000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876098 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498459 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.477849 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.467728 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.946305 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id @@ -476,17 +476,17 @@ system.cpu.l2cache.demand_misses::total 1958774 # nu system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32381000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61822893500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61855274500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40996230000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40996230000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32381000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102819123500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 102851504500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32381000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102819123500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102851504500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) @@ -511,17 +511,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.214875 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52566.558442 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52513.241093 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52513.268976 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.307347 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.307347 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52566.558442 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.083362 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52508.101751 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52566.558442 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.083362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52508.101751 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,17 +543,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1958774 system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24978000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47681937000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47706915000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31625653000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31625653000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24978000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79307590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 79332568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24978000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79307590000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 79332568000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses @@ -565,17 +565,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40548.701299 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40501.712419 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40501.736993 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.224107 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.224107 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution @@ -590,19 +590,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 12813292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) @@ -630,9 +628,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 2975972 # Request fanout histogram -system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 7175472500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 9807518500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |