diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
| commit | c6cede244b431c167ac0213d89ad2bd7a0abbd96 (patch) | |
| tree | fb0e63d4172746d5b1a8edeb859f7ee68cfe13a6 /tests/long/se/60.bzip2/ref/arm | |
| parent | 83a5977481d55916b200740cf03748a20777bdf1 (diff) | |
| download | gem5-c6cede244b431c167ac0213d89ad2bd7a0abbd96.tar.xz | |
stats: Update stats to reflect changes to cache and crossbar
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm')
3 files changed, 835 insertions, 844 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 144dc4013..0ee27457c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.116861 # Nu sim_ticks 1116860578500 # Number of ticks simulated final_tick 1116860578500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237615 # Simulator instruction rate (inst/s) -host_op_rate 255994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171817202 # Simulator tick rate (ticks/s) -host_mem_usage 317996 # Number of bytes of host memory used -host_seconds 6500.28 # Real time elapsed on the host +host_inst_rate 228405 # Simulator instruction rate (inst/s) +host_op_rate 246072 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 165157932 # Simulator tick rate (ticks/s) +host_mem_usage 318996 # Number of bytes of host memory used +host_seconds 6762.38 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 130981888 # To system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1309 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 962724 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 127279 # Per bank write bursts system.physmem.perBankRdBursts::1 124661 # Per bank write bursts system.physmem.perBankRdBursts::2 121601 # Per bank write bursts @@ -833,14 +833,14 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 system.cpu.toL2Bus.trans_dist::ReadResp 7335104 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4734689 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6498678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6500272 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 820 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1669 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27669721 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27671390 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27672984 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220992 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 826275328 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 67eb4b375..901b0011b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.767966 # Number of seconds simulated -sim_ticks 767965542000 # Number of ticks simulated -final_tick 767965542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.767875 # Number of seconds simulated +sim_ticks 767874998000 # Number of ticks simulated +final_tick 767874998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135762 # Simulator instruction rate (inst/s) -host_op_rate 146263 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67501614 # Simulator tick rate (ticks/s) -host_mem_usage 354608 # Number of bytes of host memory used -host_seconds 11377.00 # Real time elapsed on the host +host_inst_rate 133325 # Simulator instruction rate (inst/s) +host_op_rate 143638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66282190 # Simulator tick rate (ticks/s) +host_mem_usage 359880 # Number of bytes of host memory used +host_seconds 11584.94 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 65024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 235466816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63671744 # Number of bytes read from this memory -system.physmem.bytes_read::total 299203584 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104705856 # Number of bytes written to this memory -system.physmem.bytes_written::total 104705856 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1016 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3679169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 994871 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4675056 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1636029 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1636029 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 84670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 306611173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82909637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 389605481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 84670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 84670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136341867 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136341867 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136341867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 84670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 306611173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82909637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 525947348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4675056 # Number of read requests accepted -system.physmem.writeReqs 1636029 # Number of write requests accepted -system.physmem.readBursts 4675056 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1636029 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 298722176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 481408 # Total number of bytes read from write queue -system.physmem.bytesWritten 104702912 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299203584 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104705856 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7522 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3003359 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301326 # Per bank write bursts -system.physmem.perBankRdBursts::1 298715 # Per bank write bursts -system.physmem.perBankRdBursts::2 284983 # Per bank write bursts -system.physmem.perBankRdBursts::3 287209 # Per bank write bursts -system.physmem.perBankRdBursts::4 287920 # Per bank write bursts -system.physmem.perBankRdBursts::5 285373 # Per bank write bursts -system.physmem.perBankRdBursts::6 281637 # Per bank write bursts -system.physmem.perBankRdBursts::7 277868 # Per bank write bursts -system.physmem.perBankRdBursts::8 293986 # Per bank write bursts -system.physmem.perBankRdBursts::9 298704 # Per bank write bursts -system.physmem.perBankRdBursts::10 291815 # Per bank write bursts -system.physmem.perBankRdBursts::11 297314 # Per bank write bursts -system.physmem.perBankRdBursts::12 299397 # Per bank write bursts -system.physmem.perBankRdBursts::13 298122 # Per bank write bursts -system.physmem.perBankRdBursts::14 294010 # Per bank write bursts -system.physmem.perBankRdBursts::15 289155 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 235361472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63663872 # Number of bytes read from this memory +system.physmem.bytes_read::total 299090176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104698048 # Number of bytes written to this memory +system.physmem.bytes_written::total 104698048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3677523 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 994748 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4673284 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1635907 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1635907 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 84430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 306510139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82909161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 389503730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 84430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 84430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136347776 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136347776 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136347776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 84430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 306510139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82909161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 525851506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4673284 # Number of read requests accepted +system.physmem.writeReqs 1635907 # Number of write requests accepted +system.physmem.readBursts 4673284 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1635907 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 298596928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 493248 # Total number of bytes read from write queue +system.physmem.bytesWritten 104694592 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299090176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104698048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7707 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 24 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 300421 # Per bank write bursts +system.physmem.perBankRdBursts::1 298937 # Per bank write bursts +system.physmem.perBankRdBursts::2 284574 # Per bank write bursts +system.physmem.perBankRdBursts::3 288248 # Per bank write bursts +system.physmem.perBankRdBursts::4 288002 # Per bank write bursts +system.physmem.perBankRdBursts::5 284734 # Per bank write bursts +system.physmem.perBankRdBursts::6 280770 # Per bank write bursts +system.physmem.perBankRdBursts::7 278050 # Per bank write bursts +system.physmem.perBankRdBursts::8 293697 # Per bank write bursts +system.physmem.perBankRdBursts::9 299275 # Per bank write bursts +system.physmem.perBankRdBursts::10 291592 # Per bank write bursts +system.physmem.perBankRdBursts::11 297756 # Per bank write bursts +system.physmem.perBankRdBursts::12 299138 # Per bank write bursts +system.physmem.perBankRdBursts::13 298570 # Per bank write bursts +system.physmem.perBankRdBursts::14 293356 # Per bank write bursts +system.physmem.perBankRdBursts::15 288457 # Per bank write bursts system.physmem.perBankWrBursts::0 103823 # Per bank write bursts -system.physmem.perBankWrBursts::1 101759 # Per bank write bursts -system.physmem.perBankWrBursts::2 99255 # Per bank write bursts -system.physmem.perBankWrBursts::3 99822 # Per bank write bursts -system.physmem.perBankWrBursts::4 99277 # Per bank write bursts -system.physmem.perBankWrBursts::5 98671 # Per bank write bursts -system.physmem.perBankWrBursts::6 102768 # Per bank write bursts -system.physmem.perBankWrBursts::7 104279 # Per bank write bursts -system.physmem.perBankWrBursts::8 105369 # Per bank write bursts -system.physmem.perBankWrBursts::9 104220 # Per bank write bursts -system.physmem.perBankWrBursts::10 102032 # Per bank write bursts -system.physmem.perBankWrBursts::11 102651 # Per bank write bursts -system.physmem.perBankWrBursts::12 102828 # Per bank write bursts -system.physmem.perBankWrBursts::13 102619 # Per bank write bursts -system.physmem.perBankWrBursts::14 104194 # Per bank write bursts +system.physmem.perBankWrBursts::1 101786 # Per bank write bursts +system.physmem.perBankWrBursts::2 99158 # Per bank write bursts +system.physmem.perBankWrBursts::3 99952 # Per bank write bursts +system.physmem.perBankWrBursts::4 99094 # Per bank write bursts +system.physmem.perBankWrBursts::5 98779 # Per bank write bursts +system.physmem.perBankWrBursts::6 102513 # Per bank write bursts +system.physmem.perBankWrBursts::7 104359 # Per bank write bursts +system.physmem.perBankWrBursts::8 105182 # Per bank write bursts +system.physmem.perBankWrBursts::9 104512 # Per bank write bursts +system.physmem.perBankWrBursts::10 101930 # Per bank write bursts +system.physmem.perBankWrBursts::11 102694 # Per bank write bursts +system.physmem.perBankWrBursts::12 102904 # Per bank write bursts +system.physmem.perBankWrBursts::13 102694 # Per bank write bursts +system.physmem.perBankWrBursts::14 104057 # Per bank write bursts system.physmem.perBankWrBursts::15 102416 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 767965500500 # Total gap between requests +system.physmem.totGap 767874956500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4675056 # Read request sizes (log2) +system.physmem.readPktSize::6 4673284 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1636029 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2763524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1029428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 325669 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 231653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 149305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 81525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18003 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 753 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1635907 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2762422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1028983 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 325435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 231330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 148884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 81578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1720 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 107107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 109521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 111129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 111161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 101092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 100232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 72944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 100110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 109501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 111603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 101089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,124 +197,116 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4246279 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 95.006264 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.933304 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.667614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3382951 79.67% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 666013 15.68% 95.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94842 2.23% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35210 0.83% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22787 0.54% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12374 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7276 0.17% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5157 0.12% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19669 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4246279 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97783 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.733256 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.725873 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-127 93691 95.82% 95.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-255 1680 1.72% 97.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-383 798 0.82% 98.35% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-511 374 0.38% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-639 374 0.38% 99.11% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-767 340 0.35% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-895 220 0.22% 99.69% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::896-1023 159 0.16% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1151 76 0.08% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1152-1279 37 0.04% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1407 11 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1408-1535 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1663 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1664-1791 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2176-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2431 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3200-3327 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3712-3839 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3840-3967 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97783 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97783 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.730751 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.687620 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.251075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 68399 69.95% 69.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 2006 2.05% 72.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18369 18.79% 90.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5745 5.88% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1950 1.99% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 718 0.73% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 317 0.32% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 149 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 75 0.08% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 33 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 10 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 4243203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 95.043673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.954417 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.715127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3379213 79.64% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 666153 15.70% 95.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95338 2.25% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35101 0.83% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23158 0.55% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12215 0.29% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7169 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5140 0.12% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19716 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4243203 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97801 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.704328 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.639805 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95408 97.55% 97.55% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1143 1.17% 98.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 693 0.71% 99.43% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 419 0.43% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 104 0.11% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 21 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 6 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97801 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97801 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.726342 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.683389 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.248647 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 68568 70.11% 70.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 2029 2.07% 72.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18244 18.65% 90.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5739 5.87% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1897 1.94% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 745 0.76% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 303 0.31% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 146 0.15% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 72 0.07% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 32 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 13 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 4 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97783 # Writes before turning the bus around for reads -system.physmem.totQLat 128413030932 # Total ticks spent queuing -system.physmem.totMemAccLat 215929293432 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23337670000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27511.96 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 97801 # Writes before turning the bus around for reads +system.physmem.totQLat 128464947947 # Total ticks spent queuing +system.physmem.totMemAccLat 215944516697 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23327885000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27534.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46261.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 388.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 46284.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 388.86 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 136.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 389.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.34 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 389.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.35 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.10 # Data bus utilization in percentage system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.89 # Average write queue length when enqueuing -system.physmem.readRowHits 1709654 # Number of row buffer hits during reads -system.physmem.writeRowHits 347571 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.63 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing +system.physmem.readRowHits 1710553 # Number of row buffer hits during reads +system.physmem.writeRowHits 347662 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate 21.25 # Row buffer hit rate for writes -system.physmem.avgGap 121685.18 # Average gap between requests -system.physmem.pageHitRate 32.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15953799960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8704950375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 17977486800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5246246880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50159272800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 414403163865 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 97263315750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 609708236430 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.934243 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 159282861364 # Time in different power states -system.physmem_0.memoryStateTime::REF 25643800000 # Time in different power states +system.physmem.avgGap 121707.36 # Average gap between requests +system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15942837960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8698969125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 17968828800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5245261920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50153678640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 415022318100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 96668804250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 609700698795 # Total energy per rank (pJ) +system.physmem_0.averagePower 794.012990 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 158294269639 # Time in different power states +system.physmem_0.memoryStateTime::REF 25640940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 583033093643 # Time in different power states +system.physmem_0.memoryStateTime::ACT 583937331861 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16147600560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8810694750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18427445400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5354300880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50159272800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 410341742010 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100825962000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 610067018400 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.401440 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165241048217 # Time in different power states -system.physmem_1.memoryStateTime::REF 25643800000 # Time in different power states +system.physmem_1.actEnergy 16135663320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8804181375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18422297400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5354961840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50153678640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 410145276690 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100946910750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 609962970015 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.354545 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165441923935 # Time in different power states +system.physmem_1.memoryStateTime::REF 25640940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 577073869783 # Time in different power states +system.physmem_1.memoryStateTime::ACT 576789598565 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286290965 # Number of BP lookups -system.cpu.branchPred.condPredicted 223414875 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14630075 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157650249 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150360830 # Number of BTB hits +system.cpu.branchPred.lookups 286279645 # Number of BP lookups +system.cpu.branchPred.condPredicted 223407155 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631310 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157715633 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150347717 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.376208 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16641594 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.328354 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16640366 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -433,128 +425,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1535931085 # number of cpu cycles simulated +system.cpu.numCycles 1535749997 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13926236 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067547876 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286290965 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 167002424 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1507284638 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29284969 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 196 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 917 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656963855 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 927 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1535854471 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.442200 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228202 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13928863 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067540877 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286279645 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166988083 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1507099451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29287501 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 190 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 976 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656956376 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 928 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1535673230 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.442364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228170 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 453416615 29.52% 29.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465436740 30.30% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101431033 6.60% 66.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515570083 33.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 453232887 29.51% 29.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465446694 30.31% 59.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101428513 6.60% 66.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515565136 33.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1535854471 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.186396 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.346120 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74705927 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 538395080 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849912555 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58199125 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14641784 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42202960 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 1535673230 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.186410 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.346274 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74702692 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 538196786 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849939330 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58191372 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14643050 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42203099 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 740 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037254051 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52495885 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14641784 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139801946 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 457449218 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13751 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837842602 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86105170 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976447004 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26743472 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45311241 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126368 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1599527 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25035305 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985923292 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128451044 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432959840 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 125 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 2037258767 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52502216 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14643050 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139798596 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 457232788 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14060 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837861639 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86123097 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976450357 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26748217 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45311443 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 127280 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1601349 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25060230 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985922281 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128467759 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432961586 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 131 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 311024347 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 154 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 145 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111506310 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542573483 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199309856 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26973622 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29535518 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1948030100 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 311023336 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 153 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 144 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111484275 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542573994 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199309930 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26884095 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29108781 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1948029821 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 211 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857442950 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13480165 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283997895 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647563158 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1857521274 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13507542 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283997616 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647442130 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1535854471 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.209387 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150580 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1535673230 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.209581 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150633 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 582872858 37.95% 37.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326140941 21.24% 59.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378202799 24.62% 83.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219661262 14.30% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28970430 1.89% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6181 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 582693827 37.94% 37.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326116884 21.24% 59.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378188392 24.63% 83.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219675077 14.30% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28992875 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6175 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1535854471 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1535673230 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166043738 41.02% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1958 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191460391 47.30% 88.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47270881 11.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166036820 40.98% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1982 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191468502 47.25% 88.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47685170 11.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138255914 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800916 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138261186 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800987 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -576,88 +568,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 28 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532080715 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186305355 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532140310 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186318740 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857442950 # Type of FU issued -system.cpu.iq.rate 1.209327 # Inst issue rate -system.cpu.iq.fu_busy_cnt 404776968 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.217922 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5668997271 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2232041055 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805706922 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 233 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 216 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262219787 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 131 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17802666 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857521274 # Type of FU issued +system.cpu.iq.rate 1.209521 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405192474 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218136 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5669415557 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2232040499 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805727122 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 228 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262713615 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17816594 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84267149 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66494 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13286 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24462811 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84267660 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66369 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13310 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24462885 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4478194 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4870766 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4528039 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4867222 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14641784 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25370881 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1332488 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1948030384 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14643050 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25368203 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1322817 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1948030107 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542573483 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199309856 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 542573994 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199309930 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 149 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159276 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1171811 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13286 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7699902 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8704078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16403980 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827785519 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516901938 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29657431 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 159427 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1161958 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13310 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7700527 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8706121 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16406648 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827850066 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516960251 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29671208 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 73 # number of nop insts executed -system.cpu.iew.exec_refs 698651224 # number of memory reference insts executed -system.cpu.iew.exec_branches 229542579 # Number of branches executed -system.cpu.iew.exec_stores 181749286 # Number of stores executed -system.cpu.iew.exec_rate 1.190018 # Inst execution rate -system.cpu.iew.wb_sent 1808742163 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805706990 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169201528 # num instructions producing a value -system.cpu.iew.wb_consumers 1689618558 # num instructions consuming a value -system.cpu.iew.wb_rate 1.175643 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691991 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258099025 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 75 # number of nop insts executed +system.cpu.iew.exec_refs 698714373 # number of memory reference insts executed +system.cpu.iew.exec_branches 229541828 # Number of branches executed +system.cpu.iew.exec_stores 181754122 # Number of stores executed +system.cpu.iew.exec_rate 1.190200 # Inst execution rate +system.cpu.iew.wb_sent 1808757098 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805727191 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169214999 # num instructions producing a value +system.cpu.iew.wb_consumers 1689608003 # num instructions consuming a value +system.cpu.iew.wb_rate 1.175795 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692004 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 258092940 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14629375 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1496362804 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.112051 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.027734 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14630610 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1496181220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.112186 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.028021 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 916038990 61.22% 61.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250656359 16.75% 77.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110050903 7.35% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55261193 3.69% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29363802 1.96% 90.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34102831 2.28% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24718362 1.65% 94.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18151757 1.21% 96.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58018607 3.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 915888142 61.22% 61.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250644385 16.75% 77.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110066561 7.36% 85.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55290971 3.70% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29288855 1.96% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34073264 2.28% 93.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24725039 1.65% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18121984 1.21% 96.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58082019 3.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1496362804 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1496181220 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -703,76 +695,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58018607 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3360475057 # The number of ROB reads -system.cpu.rob.rob_writes 3883759706 # The number of ROB writes -system.cpu.timesIdled 836 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76614 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58082019 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3360223976 # The number of ROB reads +system.cpu.rob.rob_writes 3883747904 # The number of ROB writes +system.cpu.timesIdled 828 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76767 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.994411 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.994411 # CPI: Total CPI of All Threads -system.cpu.ipc 1.005620 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.005620 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175771978 # number of integer regfile reads -system.cpu.int_regfile_writes 1261585669 # number of integer regfile writes +system.cpu.cpi 0.994294 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.994294 # CPI: Total CPI of All Threads +system.cpu.ipc 1.005739 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.005739 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175836503 # number of integer regfile reads +system.cpu.int_regfile_writes 1261593461 # number of integer regfile writes system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 50 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965626191 # number of cc regfile reads -system.cpu.cc_regfile_writes 551852831 # number of cc regfile writes -system.cpu.misc_regfile_reads 675841321 # number of misc regfile reads +system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965846001 # number of cc regfile reads +system.cpu.cc_regfile_writes 551857157 # number of cc regfile writes +system.cpu.misc_regfile_reads 675854889 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17004065 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964813 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638072070 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17004577 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.523549 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 17003582 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964809 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638071493 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17004094 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.524580 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 77932500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964813 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964809 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 416 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335720557 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335720557 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469353506 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469353506 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168718419 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168718419 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335716396 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335716396 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469352988 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469352988 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168718360 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168718360 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638071925 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638071925 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638071925 # number of overall hits -system.cpu.dcache.overall_hits::total 638071925 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17418313 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17418313 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3867628 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3867628 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638071348 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638071348 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638071348 # number of overall hits +system.cpu.dcache.overall_hits::total 638071348 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17416992 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17416992 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3867687 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3867687 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21285941 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21285941 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21285943 # number of overall misses -system.cpu.dcache.overall_misses::total 21285943 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 412331077000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 412331077000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 148962559255 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 148962559255 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 21284679 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21284679 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21284681 # number of overall misses +system.cpu.dcache.overall_misses::total 21284681 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 412160487500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 412160487500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 148823410876 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 148823410876 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 561293636255 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 561293636255 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 561293636255 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 561293636255 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486771819 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486771819 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 560983898376 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 560983898376 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 560983898376 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 560983898376 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486769980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486769980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -781,470 +773,469 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659357866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659357866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659357868 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659357868 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659356027 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659356027 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659356029 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659356029 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035781 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035781 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022410 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.022410 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032283 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032283 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032283 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032283 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23672.273945 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23672.273945 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.224126 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.224126 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.032281 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032281 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032281 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032281 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23664.274951 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23664.274951 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38478.659435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38478.659435 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26369.218831 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26369.218831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26369.216353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26369.216353 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20544187 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3409553 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 942936 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67231 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.787467 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50.714001 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26356.230149 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26356.230149 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26356.227673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26356.227673 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20486404 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3408907 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 942205 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67188 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.743043 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50.736843 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 17004065 # number of writebacks -system.cpu.dcache.writebacks::total 17004065 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151291 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3151291 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130068 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1130068 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17003582 # number of writebacks +system.cpu.dcache.writebacks::total 17003582 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150438 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3150438 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130143 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1130143 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4281359 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4281359 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4281359 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4281359 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267022 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14267022 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737560 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737560 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4280581 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4280581 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4280581 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4280581 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266554 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14266554 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737544 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737544 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17004582 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17004582 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17004583 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17004583 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331931922000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 331931922000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115721294597 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 115721294597 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17004098 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17004098 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17004099 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17004099 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331835130000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 331835130000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115624975794 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 115624975794 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447653216597 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 447653216597 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447653284597 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 447653284597 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447460105794 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 447460105794 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447460173794 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 447460173794 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029309 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029309 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025790 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025790 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025790 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025790 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23265.676747 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23265.676747 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42271.692528 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42271.692528 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23259.655415 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23259.655415 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42236.755206 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42236.755206 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26325.446671 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26325.446671 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26325.449121 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26325.449121 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26314.839270 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26314.839270 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26314.841721 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26314.841721 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 587 # number of replacements -system.cpu.icache.tags.tagsinuse 444.617750 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656962266 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1073 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 612266.790308 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 590 # number of replacements +system.cpu.icache.tags.tagsinuse 444.554720 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656954786 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 610552.775093 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 444.617750 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.868394 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.868394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 444.554720 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.868271 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.868271 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 440 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313928777 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313928777 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656962266 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656962266 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656962266 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656962266 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656962266 # number of overall hits -system.cpu.icache.overall_hits::total 656962266 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1586 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1586 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1586 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1586 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1586 # number of overall misses -system.cpu.icache.overall_misses::total 1586 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 98890487 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 98890487 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 98890487 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 98890487 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 98890487 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 98890487 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656963852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656963852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656963852 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656963852 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656963852 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656963852 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313913824 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313913824 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656954786 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656954786 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656954786 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656954786 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656954786 # number of overall hits +system.cpu.icache.overall_hits::total 656954786 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1588 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1588 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1588 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1588 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1588 # number of overall misses +system.cpu.icache.overall_misses::total 1588 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 98682987 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 98682987 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 98682987 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 98682987 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 98682987 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 98682987 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656956374 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656956374 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656956374 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656956374 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656956374 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656956374 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62352.135561 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62352.135561 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62352.135561 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62352.135561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62352.135561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62352.135561 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17132 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 145 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62142.938917 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62142.938917 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62142.938917 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62142.938917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62142.938917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62142.938917 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17933 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 176 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 194 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88.309278 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29 # average number of cycles each access was blocked +system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 92.438144 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 587 # number of writebacks -system.cpu.icache.writebacks::total 587 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 511 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 511 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 511 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 511 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 511 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1075 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1075 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1075 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73172990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 73172990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73172990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 73172990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73172990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 73172990 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 590 # number of writebacks +system.cpu.icache.writebacks::total 590 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 510 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 510 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 510 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 510 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 510 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 510 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1078 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1078 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74485990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 74485990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74485990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 74485990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74485990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 74485990 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68067.897674 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68067.897674 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68067.897674 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68067.897674 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68067.897674 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68067.897674 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69096.465677 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69096.465677 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69096.465677 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69096.465677 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69096.465677 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69096.465677 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 11609988 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11638125 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 19145 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 11607933 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11636199 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 19107 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 5 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4657211 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 4708196 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16099.895635 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 22828795 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4724118 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.832393 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 54830616500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 13098.409047 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2.246929 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2999.239659 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.799463 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000137 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183059 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.982660 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 830 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15092 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 625 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 476 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2900 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4269 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5555 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1892 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050659 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921143 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 552251030 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 552251030 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 4828216 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 4828216 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 12155140 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 12155140 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1757112 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1757112 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 57 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 57 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11520085 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 11520085 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 57 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13277197 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13277254 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 57 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13277197 # number of overall hits -system.cpu.l2cache.overall_hits::total 13277254 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 980492 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 980492 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1018 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1018 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2746888 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2746888 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1018 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3727380 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3728398 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1018 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3727380 # number of overall misses -system.cpu.l2cache.overall_misses::total 3728398 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 137500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 137500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 99075323500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 99075323500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 71685000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 71685000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234271379500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 234271379500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 71685000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 333346703000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 333418388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 71685000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 333346703000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 333418388000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 4828216 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 4828216 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 12155140 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 12155140 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737604 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2737604 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1075 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1075 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266973 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 14266973 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1075 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 17004577 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17005652 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1075 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17004577 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17005652 # number of overall (read+write) accesses +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 4655601 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 4705755 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16099.742972 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 22830947 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4721680 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.835344 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 54104143500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 13103.742170 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 2.284694 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2993.716107 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.799789 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000139 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.182722 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.982650 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 804 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15121 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 610 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 192 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 461 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2942 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4257 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5586 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1875 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.049072 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.922913 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 552235013 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 552235013 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 4829213 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 4829213 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 12153673 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 12153673 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1758045 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1758045 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 63 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 63 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11520714 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 11520714 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 63 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 13278759 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13278822 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 63 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 13278759 # number of overall hits +system.cpu.l2cache.overall_hits::total 13278822 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 979533 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 979533 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1015 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1015 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2745802 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 2745802 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1015 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3725335 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3726350 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1015 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3725335 # number of overall misses +system.cpu.l2cache.overall_misses::total 3726350 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 100500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 100500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98972728500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 98972728500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72952500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 72952500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234172325000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 234172325000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 72952500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 333145053500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 333218006000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 72952500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 333145053500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 333218006000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 4829213 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 4829213 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 12153673 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 12153673 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2737578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1078 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1078 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266516 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 14266516 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1078 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 17004094 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17005172 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1078 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 17004094 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 17005172 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358157 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.358157 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.946977 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.946977 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192535 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192535 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.946977 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.219199 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.219245 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.946977 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.219199 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.219245 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22916.666667 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22916.666667 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101046.539390 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101046.539390 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70417.485265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70417.485265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85286.105404 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85286.105404 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70417.485265 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89431.907399 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89426.715710 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70417.485265 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89431.907399 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89426.715710 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 83 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.357810 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.357810 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.941558 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.941558 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192465 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192465 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.941558 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.219085 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.219130 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.941558 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.219085 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.219130 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20100 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20100 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101040.729103 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101040.729103 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71874.384236 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71874.384236 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85283.762267 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85283.762267 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71874.384236 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89426.871275 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89422.090249 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71874.384236 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89426.871275 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89422.090249 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 879 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 41.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 146.500000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1636029 # number of writebacks -system.cpu.l2cache.writebacks::total 1636029 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3958 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3958 # number of ReadExReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 1635907 # number of writebacks +system.cpu.l2cache.writebacks::total 1635907 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3910 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3910 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45559 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45559 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45136 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45136 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 49517 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 49518 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 49046 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 49047 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 49517 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 49518 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1144921 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1144921 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976534 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 976534 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1017 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1017 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2701329 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2701329 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3677863 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3678880 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3677863 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1144921 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4823801 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72325395404 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72325395404 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 101500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 101500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92841040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92841040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65516000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65516000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215255322500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215255322500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65516000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 308096362500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 308161878500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65516000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 308096362500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72325395404 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 380487273904 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 49046 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 49047 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1143496 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1143496 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 975623 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 975623 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1014 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1014 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2700666 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2700666 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3676289 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3677303 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3676289 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1143496 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4820799 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72430896209 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72430896209 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 70500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 70500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92751563000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92751563000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66801500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66801500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215184233000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215184233000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66801500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307935796000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 308002597500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66801500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307935796000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72430896209 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 380433493709 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.946047 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189341 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189341 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216287 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216333 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216287 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356382 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356382 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.940631 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189301 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189301 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216200 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216246 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216200 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.283659 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63170.642694 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63170.642694 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16916.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16916.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95071.999541 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95071.999541 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64420.845624 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64420.845624 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79684.970805 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79684.970805 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64420.845624 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83770.483702 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83765.134633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64420.845624 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83770.483702 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63170.642694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78877.066841 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.283490 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63341.626214 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63341.626214 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95069.061512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95069.061512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65879.191321 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65879.191321 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79678.210116 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79678.210116 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65879.191321 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83762.673718 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83757.742427 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65879.191321 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83762.673718 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63341.626214 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78915.029170 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 34010311 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004668 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21296 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2921208 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2902417 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18791 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 14268046 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6464245 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12155140 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5774511 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1435676 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737604 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737604 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266973 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2731 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50991946 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50994677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 105984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2175190848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2175296832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 8846223 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 25851874 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.114549 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.320751 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 34009349 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004186 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21286 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2918754 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899783 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18971 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 14267592 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6465120 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12174959 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5771526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1434255 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266516 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2744 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51014533 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176491840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176598464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 8841697 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 25846865 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.114483 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.320694 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22909361 88.62% 88.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2923722 11.31% 99.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 18791 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22906816 88.63% 88.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2921078 11.30% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 18971 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25851874 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34009808017 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25846865 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34008846525 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 10525 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 13536 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1610997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1615497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25506872492 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25506147987 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3698381 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1636029 # Transaction distribution -system.membus.trans_dist::CleanEvict 3003353 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 976674 # Transaction distribution -system.membus.trans_dist::ReadExResp 976674 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3698382 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13989505 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13989505 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403909376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 403909376 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3697520 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1635907 # Transaction distribution +system.membus.trans_dist::CleanEvict 3001520 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 975763 # Transaction distribution +system.membus.trans_dist::ReadExResp 975763 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3697521 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13983999 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13983999 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403788160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 403788160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9314444 # Request fanout histogram +system.membus.snoop_fanout::samples 9310716 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9314444 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9310716 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9314444 # Request fanout histogram -system.membus.reqLayer0.occupancy 17663480706 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9310716 # Request fanout histogram +system.membus.reqLayer0.occupancy 17657125833 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 25423271236 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25413031627 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 02c08f292..232fe8b45 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.377030 # Nu sim_ticks 2377029670500 # Number of ticks simulated final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 970948 # Simulator instruction rate (inst/s) -host_op_rate 1046333 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1499891883 # Simulator tick rate (ticks/s) -host_mem_usage 316204 # Number of bytes of host memory used -host_seconds 1584.80 # Real time elapsed on the host +host_inst_rate 872363 # Simulator instruction rate (inst/s) +host_op_rate 940093 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1347600333 # Simulator tick rate (ticks/s) +host_mem_usage 317216 # Number of bytes of host memory used +host_seconds 1763.90 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -606,14 +606,14 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6326510 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27340461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27341744 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes) |