diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-03-09 15:33:07 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-03-09 15:33:07 -0500 |
| commit | 470051345af2a78425730bd790000530b1b8a1f5 (patch) | |
| tree | d2bdfb09a2cfc4c96a5fcd9c4399610fbf4206a3 /tests/long/se/60.bzip2/ref/arm | |
| parent | 9a9a4a0780865dc722b7564ea1c1bf8bacb4e5ce (diff) | |
| download | gem5-470051345af2a78425730bd790000530b1b8a1f5.tar.xz | |
ARM: Update stats for CBNZ fix.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm')
8 files changed, 538 insertions, 532 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 51e908aa2..cdbe03d5f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +148,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -161,7 +161,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -428,7 +428,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -449,7 +449,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -465,11 +465,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -489,8 +489,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -500,7 +500,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -532,7 +533,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -542,5 +544,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr index e45cd058f..b4d96e4ea 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections +warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 8fb7001b0..d23947013 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:19:56 -gem5 started Feb 12 2012 20:51:32 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:27:07 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 464073050000 because target called exit() +Exiting @ tick 464094642500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 9e645d1ea..b46ca3b4f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.464073 # Number of seconds simulated -sim_ticks 464073050000 # Number of ticks simulated -final_tick 464073050000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.464095 # Number of seconds simulated +sim_ticks 464094642500 # Number of ticks simulated +final_tick 464094642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176271 # Simulator instruction rate (inst/s) -host_op_rate 196643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52961695 # Simulator tick rate (ticks/s) -host_mem_usage 223676 # Number of bytes of host memory used -host_seconds 8762.43 # Real time elapsed on the host -sim_insts 1544563056 # Number of instructions simulated -sim_ops 1723073869 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 189754368 # Number of bytes read from this memory -system.physmem.bytes_inst_read 48448 # Number of instructions bytes read from this memory -system.physmem.bytes_written 78230272 # Number of bytes written to this memory -system.physmem.num_reads 2964912 # Number of read requests responded to by this memory -system.physmem.num_writes 1222348 # Number of write requests responded to by this memory +host_inst_rate 178110 # Simulator instruction rate (inst/s) +host_op_rate 198694 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53516537 # Simulator tick rate (ticks/s) +host_mem_usage 227392 # Number of bytes of host memory used +host_seconds 8671.99 # Real time elapsed on the host +sim_insts 1544563041 # Number of instructions simulated +sim_ops 1723073854 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 189817088 # Number of bytes read from this memory +system.physmem.bytes_inst_read 48640 # Number of instructions bytes read from this memory +system.physmem.bytes_written 78237376 # Number of bytes written to this memory +system.physmem.num_reads 2965892 # Number of read requests responded to by this memory +system.physmem.num_writes 1222459 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 408889006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 104397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 168573185 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 577462190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 409005127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 104806 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 168580649 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 577585776 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,107 +64,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 928146101 # number of cpu cycles simulated +system.cpu.numCycles 928189286 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 300566019 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 246342426 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16106991 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 172736235 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 156347078 # Number of BTB hits +system.cpu.BPredUnit.lookups 300558884 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 246363041 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16110008 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 171748174 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 156362542 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18335765 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 410 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 292802110 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2158556881 # Number of instructions fetch has processed -system.cpu.fetch.Branches 300566019 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174682843 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 429264774 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83785432 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 129176492 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 309 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 283792946 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5380579 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 918501449 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.613879 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.238743 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18325675 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 390 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 292832773 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2158671516 # Number of instructions fetch has processed +system.cpu.fetch.Branches 300558884 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174688217 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 429285540 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83802150 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 129138530 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 283809493 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5370008 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 918527985 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.613925 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.238783 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 489236723 53.26% 53.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23024875 2.51% 55.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38786234 4.22% 59.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47824320 5.21% 65.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40756189 4.44% 69.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46964078 5.11% 74.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39095628 4.26% 79.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18144974 1.98% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174668428 19.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 489242491 53.26% 53.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23031671 2.51% 55.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38788083 4.22% 59.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47826065 5.21% 65.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40763412 4.44% 69.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46954546 5.11% 74.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39099426 4.26% 79.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18124481 1.97% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174697810 19.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 918501449 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.323835 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.325665 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 322112975 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 109206216 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403275742 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16649458 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 67257058 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46176709 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 759 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2347040926 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2511 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 67257058 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 343744693 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50775772 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 22198 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 397120131 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 59581597 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2290149919 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23251 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4667919 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 46275027 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2264746735 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10570831764 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10570827058 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4706 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319983 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 558426752 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5769 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5766 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 136911238 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624866711 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 218769389 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86004799 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66542105 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2190647853 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1858 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2016093743 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4890618 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462875235 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1075025863 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1351 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 918501449 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.194982 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.923350 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 918527985 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.323812 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325680 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 322137890 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 109173401 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403303983 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16642613 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 67270098 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46182318 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 747 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2347171741 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2550 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 67270098 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 343773810 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50758192 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21988 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 397138305 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 59565592 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2290275122 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23158 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4666704 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 46265569 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 2 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2264842596 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10571584644 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10571581459 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3185 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319959 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 558522637 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5679 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5674 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 136915079 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624891325 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 218844969 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86018221 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 66187056 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2190772661 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1712 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2016120341 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4885308 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 463006686 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1075673735 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1208 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 918527985 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.194947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.923224 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 251234212 27.35% 27.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 138874484 15.12% 42.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158306174 17.24% 59.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 116338080 12.67% 72.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125703968 13.69% 86.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75541719 8.22% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39131512 4.26% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10691268 1.16% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2680032 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 251260735 27.35% 27.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 138867546 15.12% 42.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158222967 17.23% 59.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 116427032 12.68% 72.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125736326 13.69% 86.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75508875 8.22% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39162431 4.26% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10675084 1.16% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2666989 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 918501449 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 918527985 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 823704 3.29% 3.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4653 0.02% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 822239 3.28% 3.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4824 0.02% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available @@ -192,13 +192,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18995164 75.78% 79.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5243478 20.92% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19001190 75.81% 79.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5234373 20.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234318256 61.22% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 931291 0.05% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234297815 61.22% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 931066 0.05% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued @@ -220,160 +220,160 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 86 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 50 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 36 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 19 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 9 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587032832 29.12% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193811220 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587044073 29.12% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193847304 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2016093743 # Type of FU issued -system.cpu.iq.rate 2.172173 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25066999 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012433 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4980646048 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2653710289 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1958144551 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 504 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 870 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 197 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2041160487 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 255 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63652463 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2016120341 # Type of FU issued +system.cpu.iq.rate 2.172100 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25062626 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012431 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4980716257 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2653967070 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1958162011 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 344 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 554 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2041182792 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 175 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63608263 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138939936 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 281971 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189096 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 43922339 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138964553 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 284704 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189296 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 43997922 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 450534 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 451252 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 67257058 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23170910 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1317099 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2190657684 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5590225 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624866711 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 218769389 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1791 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 207758 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 50528 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189096 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8640354 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10202609 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18842963 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1986590915 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 572448085 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29502828 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 67270098 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23165985 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1316827 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2190782552 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5581738 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624891325 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 218844969 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1648 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 207697 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 50017 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189296 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8647984 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10198062 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18846046 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1986617242 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 572452659 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29503099 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 7973 # number of nop insts executed -system.cpu.iew.exec_refs 763288309 # number of memory reference insts executed -system.cpu.iew.exec_branches 238204396 # Number of branches executed -system.cpu.iew.exec_stores 190840224 # Number of stores executed -system.cpu.iew.exec_rate 2.140386 # Inst execution rate -system.cpu.iew.wb_sent 1967133109 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1958144748 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296172102 # num instructions producing a value -system.cpu.iew.wb_consumers 2068722658 # num instructions consuming a value +system.cpu.iew.exec_nop 8179 # number of nop insts executed +system.cpu.iew.exec_refs 763318356 # number of memory reference insts executed +system.cpu.iew.exec_branches 238198091 # Number of branches executed +system.cpu.iew.exec_stores 190865697 # Number of stores executed +system.cpu.iew.exec_rate 2.140315 # Inst execution rate +system.cpu.iew.wb_sent 1967150761 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1958162143 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296167059 # num instructions producing a value +system.cpu.iew.wb_consumers 2068734310 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.109738 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626557 # average fanout of values written-back +system.cpu.iew.wb_rate 2.109658 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626551 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1544563074 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1723073887 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 467651163 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 507 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16106465 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 851244392 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.024182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.756273 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1544563059 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1723073872 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 467775476 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 504 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16109498 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 851257888 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.024150 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.756084 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 363008407 42.64% 42.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192701589 22.64% 65.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73550522 8.64% 73.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35106838 4.12% 78.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18707332 2.20% 80.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30658705 3.60% 83.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19651115 2.31% 86.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10957875 1.29% 87.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106902009 12.56% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 363004636 42.64% 42.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192697561 22.64% 65.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73553862 8.64% 73.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35091204 4.12% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18733793 2.20% 80.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30684966 3.60% 83.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19668934 2.31% 86.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10962087 1.29% 87.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106860845 12.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 851244392 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563074 # Number of instructions committed -system.cpu.commit.committedOps 1723073887 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 851257888 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563059 # Number of instructions committed +system.cpu.commit.committedOps 1723073872 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773825 # Number of memory references committed -system.cpu.commit.loads 485926775 # Number of loads committed +system.cpu.commit.refs 660773819 # Number of memory references committed +system.cpu.commit.loads 485926772 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462369 # Number of branches committed +system.cpu.commit.branches 213462366 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941869 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106902009 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106860845 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2935066834 # The number of ROB reads -system.cpu.rob.rob_writes 4448881416 # The number of ROB writes -system.cpu.timesIdled 899412 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9644652 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563056 # Number of Instructions Simulated -system.cpu.committedOps 1723073869 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563056 # Number of Instructions Simulated -system.cpu.cpi 0.600912 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.600912 # CPI: Total CPI of All Threads -system.cpu.ipc 1.664138 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.664138 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9951907734 # number of integer regfile reads -system.cpu.int_regfile_writes 1938294940 # number of integer regfile writes -system.cpu.fp_regfile_reads 210 # number of floating regfile reads -system.cpu.fp_regfile_writes 230 # number of floating regfile writes -system.cpu.misc_regfile_reads 2898206993 # number of misc regfile reads -system.cpu.misc_regfile_writes 134 # number of misc regfile writes -system.cpu.icache.replacements 22 # number of replacements -system.cpu.icache.tagsinuse 634.912102 # Cycle average of tags in use -system.cpu.icache.total_refs 283791788 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 786 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 361058.254453 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2935245792 # The number of ROB reads +system.cpu.rob.rob_writes 4449143808 # The number of ROB writes +system.cpu.timesIdled 899784 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9661301 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563041 # Number of Instructions Simulated +system.cpu.committedOps 1723073854 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563041 # Number of Instructions Simulated +system.cpu.cpi 0.600940 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.600940 # CPI: Total CPI of All Threads +system.cpu.ipc 1.664060 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.664060 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9952061686 # number of integer regfile reads +system.cpu.int_regfile_writes 1938314522 # number of integer regfile writes +system.cpu.fp_regfile_reads 132 # number of floating regfile reads +system.cpu.fp_regfile_writes 135 # number of floating regfile writes +system.cpu.misc_regfile_reads 2898335768 # number of misc regfile reads +system.cpu.misc_regfile_writes 128 # number of misc regfile writes +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.tagsinuse 636.409684 # Cycle average of tags in use +system.cpu.icache.total_refs 283808312 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 793 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 357891.944515 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 634.912102 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.310016 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.310016 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 283791788 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 283791788 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 283791788 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 283791788 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 283791788 # number of overall hits -system.cpu.icache.overall_hits::total 283791788 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses -system.cpu.icache.overall_misses::total 1158 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38624000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38624000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38624000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38624000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38624000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38624000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 283792946 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 283792946 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 283792946 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 283792946 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 283792946 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 283792946 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 636.409684 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.310747 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.310747 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 283808312 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 283808312 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 283808312 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 283808312 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 283808312 # number of overall hits +system.cpu.icache.overall_hits::total 283808312 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1181 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1181 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1181 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1181 # number of overall misses +system.cpu.icache.overall_misses::total 1181 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39284000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39284000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39284000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39284000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39284000 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 33354.058722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 33354.058722 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33263.336156 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33263.336156 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33263.336156 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,269 +382,269 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 388 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 793 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 793 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 793 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 793 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 793 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27229500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27229500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27229500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27229500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27229500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27229500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34414.122137 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34414.122137 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34414.122137 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34337.326608 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34337.326608 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.664224 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3348066000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.714803 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997977 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997977 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 493410063 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 493410063 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167378645 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167378645 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 88 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 88 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 63 # 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number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15904629 # number of overall misses +system.cpu.dcache.overall_misses::total 15904629 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 189148262000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 189148262000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129349741794 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129349741794 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 318498003794 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 318498003794 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 318498003794 # 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number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 676693337 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 676693337 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021220 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030173 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.032967 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.023503 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.023503 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.102760 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24885.656309 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20040.335214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20040.335214 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 270494777 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 161000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 91798 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2946.630395 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16100 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.990108 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24839.592141 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20025.490931 # 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number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 757 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2964155 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2964912 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 757 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2964155 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2964912 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23603500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63886529000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63910132500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28922104500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28922104500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23603500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92808633500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 92832237000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23603500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92808633500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 92832237000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265059 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483449 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308045 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308045 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31180.317041 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31186.919332 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31586.384441 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31180.317041 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31310.317274 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31180.317041 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31310.317274 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1222459 # number of writebacks +system.cpu.l2cache.writebacks::total 1222459 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 760 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2049470 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2050230 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915662 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 915662 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 760 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2965132 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2965892 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 760 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2965132 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2965892 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63915816500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63939496500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28922990000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28922990000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92838806500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 92862486500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23680000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92838806500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 92862486500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265146 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483481 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308114 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308114 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.894737 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31186.509927 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31586.972049 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.894737 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31310.176579 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.894737 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31310.176579 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 6c19f0c57..9508b6eff 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -71,7 +71,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts @@ -87,7 +87,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -119,7 +119,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory @@ -129,5 +130,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 1bd7f49d7..bd3b0790d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu sim_ticks 861538205000 # Number of ticks simulated final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3097767 # Simulator instruction rate (inst/s) -host_op_rate 3455787 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1727895925 # Simulator tick rate (ticks/s) -host_mem_usage 212936 # Number of bytes of host memory used -host_seconds 498.61 # Real time elapsed on the host +host_inst_rate 3009474 # Simulator instruction rate (inst/s) +host_op_rate 3357290 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1678647401 # Simulator tick rate (ticks/s) +host_mem_usage 216676 # Number of bytes of host memory used +host_seconds 513.23 # Real time elapsed on the host sim_insts 1544563049 # Number of instructions simulated sim_ops 1723073862 # Number of ops (including micro ops) simulated system.physmem.bytes_read 7759650064 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 1723073862 # Nu system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330134 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 177498450 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941850 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions system.cpu.num_int_register_reads 7861284536 # number of times the integer registers were read diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 9736169e4..ce3f8d9d1 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +80,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -93,11 +93,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -118,7 +118,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -134,11 +134,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -158,8 +158,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -169,7 +169,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -201,7 +202,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -211,5 +213,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index e00ec713c..515a2d834 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.431420 # Nu sim_ticks 2431419954000 # Number of ticks simulated final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1647360 # Simulator instruction rate (inst/s) -host_op_rate 1838469 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2603021191 # Simulator tick rate (ticks/s) -host_mem_usage 221840 # Number of bytes of host memory used -host_seconds 934.08 # Real time elapsed on the host +host_inst_rate 1665877 # Simulator instruction rate (inst/s) +host_op_rate 1859134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2632279795 # Simulator tick rate (ticks/s) +host_mem_usage 225588 # Number of bytes of host memory used +host_seconds 923.69 # Real time elapsed on the host sim_insts 1538759609 # Number of instructions simulated sim_ops 1717270343 # Number of ops (including micro ops) simulated system.physmem.bytes_read 172766016 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 1717270343 # Nu system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330134 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 177498450 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941850 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read |