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author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-05-22 11:38:04 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-05-22 11:38:04 -0500 |
commit | 0bff8eb210fedd89baed36ecab3608bb259ff520 (patch) | |
tree | dc4a9c3ec0a1ab297a69a3fec3111d7e431b09cd /tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout | |
parent | 1031fe7b6f6e29e3367750c3029b4dc850e062f5 (diff) | |
download | gem5-0bff8eb210fedd89baed36ecab3608bb259ff520.tar.xz |
X86 Regression: update stats due to cc register split
Diffstat (limited to 'tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout')
-rwxr-xr-x | tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index a0492ef0b..f085076c6 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:30 -gem5 started May 8 2012 15:58:27 -gem5 executing on piton +gem5 compiled May 21 2012 19:00:49 +gem5 started May 21 2012 19:07:40 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... |