regressions: x86: stats updates due to new x87 insts

1 files changed, 37 insertions, 37 deletions

diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index 790f1ac3e..914311460 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  5.882581                       # Number of seconds simulated
-sim_ticks                                5882580525000                       # Number of ticks simulated
-final_tick                               5882580525000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                5882580526000                       # Number of ticks simulated
+final_tick                               5882580526000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 639726                       # Simulator instruction rate (inst/s)
-host_op_rate                                   996751                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1251043124                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 291744                       # Number of bytes of host memory used
-host_seconds                                  4702.14                       # Real time elapsed on the host
+host_inst_rate                                 579739                       # Simulator instruction rate (inst/s)
+host_op_rate                                   903286                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1133733281                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 291512                       # Number of bytes of host memory used
+host_seconds                                  5188.68                       # Real time elapsed on the host
 sim_insts                                  3008081022                       # Number of instructions simulated
-sim_ops                                    4686862595                       # Number of ops (including micro ops) simulated
+sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             43200                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         125326976                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            125370176                       # Number of bytes read from this memory
@@ -35,26 +35,26 @@ system.physmem.bw_total::cpu.inst                7344                       # To
 system.physmem.bw_total::cpu.data            21304762                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               32392097                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                      11765161050                       # number of cpu cycles simulated
+system.cpu.numCycles                      11765161052                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  3008081022                       # Number of instructions committed
-system.cpu.committedOps                    4686862595                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            4686862525                       # Number of integer alu accesses
+system.cpu.committedOps                    4686862596                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            4686862527                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts    182173300                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   4686862525                       # number of integer instructions
+system.cpu.num_int_insts                   4686862527                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads         11915474423                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         5355771936                       # number of times the integer registers were written
+system.cpu.num_int_register_reads         11915474428                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         5355771938                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                    1677713083                       # number of memory refs
-system.cpu.num_load_insts                  1239184745                       # Number of load instructions
+system.cpu.num_mem_refs                    1677713084                       # number of memory refs
+system.cpu.num_load_insts                  1239184746                       # Number of load instructions
 system.cpu.num_store_insts                  438528338                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                11765161050                       # Number of busy cycles
+system.cpu.num_busy_cycles                11765161052                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     10                       # number of replacements
@@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926
 system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               1926197                       # number of replacements
-system.cpu.l2cache.tagsinuse             31136.249384                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             31136.249379                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 8965026                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs               1955980                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  4.583393                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          340768634000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 15396.795536                       # Average occupied blocks per requestor
+system.cpu.l2cache.warmup_cycle          340768635000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 15396.795533                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_blocks::cpu.inst     25.641016                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  15713.812833                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  15713.812830                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.469873                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.000783                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.479548                       # Average percentage of cache occupancy
@@ -271,22 +271,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9108581                       # number of replacements
-system.cpu.dcache.tagsinuse               4084.587031                       # Cycle average of tags in use
-system.cpu.dcache.total_refs               1668600406                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               4084.587030                       # Cycle average of tags in use
+system.cpu.dcache.total_refs               1668600407                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                9112677                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 183.107599                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            58853921000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4084.587031                       # Average occupied blocks per requestor
+system.cpu.dcache.warmup_cycle            58853922000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4084.587030                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.997214                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.997214                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data   1231961895                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total      1231961895                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data   1231961896                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total      1231961896                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    436638511                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total      436638511                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data    1668600406                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total       1668600406                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data   1668600406                       # number of overall hits
-system.cpu.dcache.overall_hits::total      1668600406                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data    1668600407                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total       1668600407                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data   1668600407                       # number of overall hits
+system.cpu.dcache.overall_hits::total      1668600407                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      7222850                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       7222850                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data      1889827                       # number of WriteReq misses
@@ -303,14 +303,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 200710756000
 system.cpu.dcache.demand_miss_latency::total 200710756000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data 200710756000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total 200710756000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data   1239184745                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total   1239184745                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data   1239184746                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total   1239184746                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    438528338                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    438528338                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data   1677713083                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total   1677713083                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data   1677713083                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total   1677713083                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data   1677713084                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total   1677713084                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data   1677713084                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total   1677713084                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.005829                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.005829                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.004309                       # miss rate for WriteReq accesses