stats: Update the stats to reflect bus and memory changes

This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.

1 files changed, 40 insertions, 0 deletions

diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index 225f011f6..136c3d430 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -34,6 +34,26 @@ system.physmem.bw_total::writebacks          11079992                       # To
 system.physmem.bw_total::cpu.inst                7344                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            21304762                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               32392097                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     32392097                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             1177614                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1177614                       # Transaction distribution
+system.membus.trans_dist::Writeback           1018421                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            781295                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           781295                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4936239                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4936239                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port      4936239                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4936239                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190549120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total    190549120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port    190549120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           190549120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              190549120                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy         11124698000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        17630181000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
 system.cpu.numCycles                      11765161052                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -370,5 +390,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput               139381638                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        7223525                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7223525                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3697956                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1889827                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1889827                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side         1350                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side     21923310                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count                 21924660                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        43200                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side    819880512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size             819923712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         819923712                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy    10103610000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1012500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy   13669015500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------