diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/60.bzip2/ref/x86/linux | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/60.bzip2/ref/x86/linux')
6 files changed, 328 insertions, 197 deletions
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index fe30d10a3..6cebafbf0 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,34 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[7] +pio=system.membus.port[6] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +97,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic +cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +121,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index a5a0064e6..23e0a7dab 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 07:13:31 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:34:58 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 6725100b8..c4996594d 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007259500 # Number of ticks simulated final_tick 2846007259500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2006575 # Simulator instruction rate (inst/s) -host_tick_rate 1218454030 # Simulator tick rate (ticks/s) -host_mem_usage 204704 # Number of bytes of host memory used -host_seconds 2335.75 # Real time elapsed on the host -sim_insts 4686862651 # Number of instructions simulated +host_inst_rate 1815306 # Simulator instruction rate (inst/s) +host_op_rate 2828411 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1717498350 # Simulator tick rate (ticks/s) +host_mem_usage 210188 # Number of bytes of host memory used +host_seconds 1657.07 # Real time elapsed on the host +sim_insts 3008081057 # Number of instructions simulated +sim_ops 4686862651 # Number of ops (including micro ops) simulated system.physmem.bytes_read 37129731755 # Number of bytes read from this memory system.physmem.bytes_inst_read 32105863408 # Number of instructions bytes read from this memory system.physmem.bytes_written 1544656790 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 46 # Nu system.cpu.numCycles 5692014520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 4686862651 # Number of instructions executed +system.cpu.committedInsts 3008081057 # Number of instructions committed +system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index e57f67518..a21cde2b2 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +104,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +118,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +149,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +171,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr @@ -191,7 +203,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 5d5232885..0e700a575 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 07:30:19 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:48:34 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 94c5d24c6..aefb42b3b 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 5.923548 # Nu sim_ticks 5923548078000 # Number of ticks simulated final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1176749 # Simulator instruction rate (inst/s) -host_tick_rate 1487248019 # Simulator tick rate (ticks/s) -host_mem_usage 213688 # Number of bytes of host memory used -host_seconds 3982.89 # Real time elapsed on the host -sim_insts 4686862651 # Number of instructions simulated +host_inst_rate 1064786 # Simulator instruction rate (inst/s) +host_op_rate 1659033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2096788716 # Simulator tick rate (ticks/s) +host_mem_usage 219100 # Number of bytes of host memory used +host_seconds 2825.06 # Real time elapsed on the host +sim_insts 3008081057 # Number of instructions simulated +sim_ops 4686862651 # Number of ops (including micro ops) simulated system.physmem.bytes_read 173910080 # Number of bytes read from this memory system.physmem.bytes_inst_read 43200 # Number of instructions bytes read from this memory system.physmem.bytes_written 75176384 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 46 # Nu system.cpu.numCycles 11847096156 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 4686862651 # Number of instructions executed +system.cpu.committedInsts 3008081057 # Number of instructions committed +system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -47,26 +50,39 @@ system.cpu.icache.total_refs 4013232252 # To system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits -system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits -system.cpu.icache.overall_hits 4013232252 # number of overall hits -system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses -system.cpu.icache.demand_misses 675 # number of demand (read+write) misses -system.cpu.icache.overall_misses 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 555.713137 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.271344 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.271344 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4013232252 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4013232252 # number of overall hits +system.cpu.icache.overall_hits::total 4013232252 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses +system.cpu.icache.overall_misses::total 675 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37800000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37800000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37800000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37800000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37800000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37800000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 4013232927 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4013232927 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4013232927 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4013232927 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35775000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 35775000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35775000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 35775000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35775000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 35775000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use @@ -102,32 +116,49 @@ system.cpu.dcache.total_refs 1668600409 # To system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 436638510 # number of WriteReq hits -system.cpu.dcache.demand_hits 1668600409 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1668600409 # number of overall hits -system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1889827 # number of WriteReq misses -system.cpu.dcache.demand_misses 9112677 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 177808540000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 63869078000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 241677618000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 241677618000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.005432 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 26521.034159 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4084.662246 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997232 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997232 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1231961899 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1231961899 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1668600409 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1668600409 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1668600409 # number of overall hits +system.cpu.dcache.overall_hits::total 1668600409 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses +system.cpu.dcache.overall_misses::total 9112677 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 177808540000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177808540000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63869078000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63869078000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 241677618000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 241677618000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 241677618000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 241677618000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1239184749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1239184749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1677713086 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1677713086 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1677713086 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1677713086 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24617.504171 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33796.256483 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3053391 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9112677 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 58199597000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 214339587000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 214339587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.004309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005432 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 3053391 # number of writebacks +system.cpu.dcache.writebacks::total 3053391 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156139990000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 156139990000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58199597000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 58199597000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214339587000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 214339587000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214339587000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 214339587000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21617.504171 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30796.256483 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2706631 # number of replacements system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use @@ -167,36 +200,72 @@ system.cpu.l2cache.total_refs 7537629 # To system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.472376 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.336564 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5396930 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3053391 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 999077 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6396007 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6396007 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1826595 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 890750 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2717345 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2717345 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 94982940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 46319000000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 141301940000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 141301940000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3053391 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.252868 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.471339 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.298172 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.298172 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 11028.544571 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 19.163936 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15459.641562 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.336564 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000585 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.471791 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.808940 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5396930 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5396930 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3053391 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3053391 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 999077 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 999077 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6396007 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6396007 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6396007 # number of overall hits +system.cpu.l2cache.overall_hits::total 6396007 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1825920 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1826595 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 890750 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 890750 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2716670 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2717345 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2716670 # number of overall misses +system.cpu.l2cache.overall_misses::total 2717345 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35100000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94947840000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94982940000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46319000000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46319000000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35100000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 141266840000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 141301940000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35100000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 141266840000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 141301940000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3053391 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3053391 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.252798 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471339 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.298120 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.298120 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,30 +274,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1174631 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1826595 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 890750 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2717345 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2717345 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 73063800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35630000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 108693800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 108693800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252868 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471339 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.298172 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.298172 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 1174631 # number of writebacks +system.cpu.l2cache.writebacks::total 1174631 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1825920 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1826595 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 890750 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 890750 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2716670 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2717345 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2716670 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2717345 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27000000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 73036800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 73063800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35630000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35630000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108666800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 108693800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108666800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 108693800000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.252798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471339 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |