Stats: Updates due to bus changes

This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.

3 files changed, 91 insertions, 91 deletions

diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index 643e6799d..f840aa9a4 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -169,7 +169,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -201,7 +201,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index 5dc44ec4f..05d9e4afd 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 28 2012 23:47:42
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 14:08:03
 gem5 executing on zizzer
 command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -24,4 +24,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 5900695290000 because target called exit()
+Exiting @ tick 5901048931000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index faa206e56..50b0e856f 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.900695                       # Number of seconds simulated
-sim_ticks                                5900695290000                       # Number of ticks simulated
-final_tick                               5900695290000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.901049                       # Number of seconds simulated
+sim_ticks                                5901048931000                       # Number of ticks simulated
+final_tick                               5901048931000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1070782                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1668375                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2100461088                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228516                       # Number of bytes of host memory used
-host_seconds                                  2809.24                       # Real time elapsed on the host
+host_inst_rate                                 821481                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1279942                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1611526350                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228472                       # Number of bytes of host memory used
+host_seconds                                  3661.78                       # Real time elapsed on the host
 sim_insts                                  3008081057                       # Number of instructions simulated
 sim_ops                                    4686862651                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             43200                       # Number of bytes read from this memory
@@ -24,18 +24,18 @@ system.physmem.num_reads::total               2173231                       # Nu
 system.physmem.num_writes::writebacks         1053029                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1053029                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst                 7321                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             23563932                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                23571253                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             23562520                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                23569841                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst            7321                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total               7321                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          11421342                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               11421342                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          11421342                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks          11420657                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               11420657                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          11420657                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst                7321                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            23563932                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               34992595                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            23562520                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               34990498                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                      11801390580                       # number of cpu cycles simulated
+system.cpu.numCycles                      11802097862                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  3008081057                       # Number of instructions committed
@@ -54,16 +54,16 @@ system.cpu.num_mem_refs                    1677713086                       # nu
 system.cpu.num_load_insts                  1239184749                       # Number of load instructions
 system.cpu.num_store_insts                  438528337                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                11801390580                       # Number of busy cycles
+system.cpu.num_busy_cycles                11802097862                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     10                       # number of replacements
-system.cpu.icache.tagsinuse                555.745205                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                555.745883                       # Cycle average of tags in use
 system.cpu.icache.total_refs               4013232252                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    675                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               5945529.262222                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     555.745205                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     555.745883                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.271360                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.271360                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   4013232252                       # number of ReadReq hits
@@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst          675                       # n
 system.cpu.icache.demand_misses::total            675                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          675                       # number of overall misses
 system.cpu.icache.overall_misses::total           675                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     37800000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     37800000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     37800000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     37800000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     37800000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     37800000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     37868000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     37868000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     37868000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     37868000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     37868000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     37868000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   4013232927                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   4013232927                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   4013232927                       # number of demand (read+write) accesses
@@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000000
 system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56100.740741                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56100.740741                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56100.740741                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56100.740741                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56100.740741                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56100.740741                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -116,32 +116,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          675
 system.cpu.icache.demand_mshr_misses::total          675                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          675                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     35775000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     35775000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     35775000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     35775000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     35775000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     35775000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     35843000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     35843000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     35843000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     35843000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     35843000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     35843000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53100.740741                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53100.740741                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53100.740741                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53100.740741                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9108581                       # number of replacements
-system.cpu.dcache.tagsinuse               4084.618409                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4084.618075                       # Cycle average of tags in use
 system.cpu.dcache.total_refs               1668600409                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                9112677                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 183.107599                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            58862653000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4084.618409                       # Average occupied blocks per requestor
+system.cpu.dcache.warmup_cycle            58864243000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4084.618075                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.997221                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.997221                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data   1231961899                       # number of ReadReq hits
@@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data      9112677                       # n
 system.cpu.dcache.demand_misses::total        9112677                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      9112677                       # number of overall misses
 system.cpu.dcache.overall_misses::total       9112677                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 159193930000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 159193930000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  59630900000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  59630900000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 218824830000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 218824830000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 218824830000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 218824830000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 159195313000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 159195313000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  59631053000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  59631053000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 218826366000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 218826366000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 218826366000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 218826366000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data   1239184749                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total   1239184749                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    438528337                       # number of WriteReq accesses(hits+misses)
@@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.005432
 system.cpu.dcache.demand_miss_rate::total     0.005432                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.005432                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.005432                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.320649                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.320649                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.628983                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.628983                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.232336                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24013.232336                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.232336                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 24013.232336                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.512125                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.512125                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.709943                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.709943                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.400892                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24013.400892                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.400892                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24013.400892                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9112677
 system.cpu.dcache.demand_mshr_misses::total      9112677                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9112677                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9112677                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525380000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525380000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53961419000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  53961419000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486799000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 191486799000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486799000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 191486799000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137526763000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 137526763000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53961572000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  53961572000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191488335000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 191488335000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191488335000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 191488335000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.005829                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.005829                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.004309                       # mshr miss rate for WriteReq accesses
@@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005432
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005432                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005432                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005432                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.320649                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.320649                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.628983                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.628983                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.232336                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.232336                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.232336                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.232336                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.512125                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.512125                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.709943                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.709943                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.400892                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.400892                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               2158210                       # number of replacements
-system.cpu.l2cache.tagsinuse             30851.506102                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             30851.471232                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 8410861                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs               2187939                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  3.844194                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          1317336331000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 14661.525978                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     21.582601                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  16168.397523                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.447434                       # Average percentage of cache occupancy
+system.cpu.l2cache.warmup_cycle          1317386171000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 14661.795010                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     21.581563                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  16168.094659                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.447442                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.000659                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.493420                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.941513                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.493411                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.941512                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.data      5840135                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        5840135                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3375759                       # number of Writeback hits