diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/long/se/60.bzip2/ref/x86 | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long/se/60.bzip2/ref/x86')
8 files changed, 747 insertions, 717 deletions
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 3f64cee84..2dc49338c 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic @@ -88,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=bzip2 input.source 1 cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic drivers= @@ -176,14 +178,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/bzip2 +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -207,6 +210,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -218,7 +222,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -226,6 +230,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -234,6 +245,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -241,7 +253,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 715860400..c93c64d50 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -3,20 +3,16 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atom gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:17 -gem5 executing on e108600-lin, pid 18539 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-atomic +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:24 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87211 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -27,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2846007227500 because target called exit() +Exiting @ tick 2846007227500 because exiting with last active thread context diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 213b5c5af..3d3e0703d 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846007 # Number of seconds simulated -sim_ticks 2846007227500 # Number of ticks simulated -final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1654731 # Simulator instruction rate (inst/s) -host_op_rate 2578221 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1565575242 # Simulator tick rate (ticks/s) -host_mem_usage 262288 # Number of bytes of host memory used -host_seconds 1817.87 # Real time elapsed on the host -sim_insts 3008081022 # Number of instructions simulated -sim_ops 4686862596 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory -system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory -system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1239184746 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5252417628 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory -system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11281019509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13046253376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11281019509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11281019509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5692014456 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 3008081022 # Number of instructions committed -system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 33534539 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4684368009 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read -system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read -system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written -system.cpu.num_mem_refs 1677713084 # number of memory refs -system.cpu.num_load_insts 1239184746 # Number of load instructions -system.cpu.num_store_insts 438528338 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5692014455.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 248500691 # Number of branches fetched -system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction -system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction -system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction -system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 4686862596 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution -system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution -system.membus.trans_dist::WriteReq 438528338 # Transaction distribution -system.membus.trans_dist::WriteResp 438528338 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5690945966 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5690945966 # Request fanout histogram +sim_seconds 2.846007 +sim_ticks 2846007227500 +final_tick 2846007227500 +sim_freq 1000000000000 +host_inst_rate 877028 +host_op_rate 1366490 +host_tick_rate 829774485 +host_mem_usage 274188 +host_seconds 3429.86 +sim_insts 3008081022 +sim_ops 4686862596 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.physmem.bytes_read::cpu.inst 32105863056 +system.physmem.bytes_read::cpu.data 5023868345 +system.physmem.bytes_read::total 37129731401 +system.physmem.bytes_inst_read::cpu.inst 32105863056 +system.physmem.bytes_inst_read::total 32105863056 +system.physmem.bytes_written::cpu.data 1544656792 +system.physmem.bytes_written::total 1544656792 +system.physmem.num_reads::cpu.inst 4013232882 +system.physmem.num_reads::cpu.data 1239184746 +system.physmem.num_reads::total 5252417628 +system.physmem.num_writes::cpu.data 438528338 +system.physmem.num_writes::total 438528338 +system.physmem.bw_read::cpu.inst 11281019509 +system.physmem.bw_read::cpu.data 1765233867 +system.physmem.bw_read::total 13046253376 +system.physmem.bw_inst_read::cpu.inst 11281019509 +system.physmem.bw_inst_read::total 11281019509 +system.physmem.bw_write::cpu.data 542745211 +system.physmem.bw_write::total 542745211 +system.physmem.bw_total::cpu.inst 11281019509 +system.physmem.bw_total::cpu.data 2307979078 +system.physmem.bw_total::total 13588998587 +system.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.cpu.workload.numSyscalls 46 +system.cpu.pwrStateResidencyTicks::ON 2846007227500 +system.cpu.numCycles 5692014456 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 3008081022 +system.cpu.committedOps 4686862596 +system.cpu.num_int_alu_accesses 4684368009 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 33534539 +system.cpu.num_conditional_control_insts 182173300 +system.cpu.num_int_insts 4684368009 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10688755601 +system.cpu.num_int_register_writes 3999841477 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 1226718827 +system.cpu.num_cc_register_writes 1355930461 +system.cpu.num_mem_refs 1677713084 +system.cpu.num_load_insts 1239184746 +system.cpu.num_store_insts 438528338 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5692014456 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 248500691 +system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% +system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% +system.cpu.op_class::IntMult 6215 0.00% 64.20% +system.cpu.op_class::IntDiv 904 0.00% 64.20% +system.cpu.op_class::FloatAdd 0 0.00% 64.20% +system.cpu.op_class::FloatCmp 0 0.00% 64.20% +system.cpu.op_class::FloatCvt 0 0.00% 64.20% +system.cpu.op_class::FloatMult 0 0.00% 64.20% +system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% +system.cpu.op_class::FloatDiv 0 0.00% 64.20% +system.cpu.op_class::FloatMisc 0 0.00% 64.20% +system.cpu.op_class::FloatSqrt 0 0.00% 64.20% +system.cpu.op_class::SimdAdd 0 0.00% 64.20% +system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% +system.cpu.op_class::SimdAlu 0 0.00% 64.20% +system.cpu.op_class::SimdCmp 0 0.00% 64.20% +system.cpu.op_class::SimdCvt 0 0.00% 64.20% +system.cpu.op_class::SimdMisc 0 0.00% 64.20% +system.cpu.op_class::SimdMult 0 0.00% 64.20% +system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% +system.cpu.op_class::SimdShift 0 0.00% 64.20% +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% +system.cpu.op_class::SimdSqrt 0 0.00% 64.20% +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% +system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% +system.cpu.op_class::MemRead 1239184746 26.44% 90.64% +system.cpu.op_class::MemWrite 438528338 9.36% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 4686862596 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.membus.trans_dist::ReadReq 5252417628 +system.membus.trans_dist::ReadResp 5252417628 +system.membus.trans_dist::WriteReq 438528338 +system.membus.trans_dist::WriteResp 438528338 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 +system.membus.pkt_count_system.cpu.icache_port::total 8026465764 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 +system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 +system.membus.pkt_count::total 11381891932 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 +system.membus.pkt_size_system.cpu.icache_port::total 32105863056 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 +system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 +system.membus.pkt_size::total 38674388193 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 5690945966 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 5690945966 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 5690945966 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index 1048d999e..136c4396f 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -100,14 +102,14 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +123,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +136,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -187,6 +191,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -199,15 +204,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -274,6 +280,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -286,15 +293,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -330,7 +338,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=bzip2 input.source 1 cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing drivers= @@ -339,14 +347,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/bzip2 +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -370,6 +379,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -381,7 +391,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -389,6 +399,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -397,6 +414,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -404,7 +422,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 0337bc6ef..f2fd8c974 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -3,20 +3,16 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:20 -gem5 executing on e108600-lin, pid 18569 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87163 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -27,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 5895947852500 because target called exit() +Exiting @ tick 5898831348500 because exiting with last active thread context diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 4f06487d9..01185a8e0 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,541 +1,541 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.898831 # Number of seconds simulated -sim_ticks 5898831348500 # Number of ticks simulated -final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1175665 # Simulator instruction rate (inst/s) -host_op_rate 1831792 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2305472192 # Simulator tick rate (ticks/s) -host_mem_usage 275096 # Number of bytes of host memory used -host_seconds 2558.62 # Real time elapsed on the host -sim_insts 3008081022 # Number of instructions simulated -sim_ops 4686862596 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126068992 # Number of bytes read from this memory -system.physmem.bytes_read::total 126112192 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66108032 # Number of bytes written to this memory -system.physmem.bytes_written::total 66108032 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1969828 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1970503 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1032938 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1032938 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 21371859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 21379183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7323 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7323 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11206971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11206971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11206971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 21371859 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 32586154 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 11797662697 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 3008081022 # Number of instructions committed -system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 33534539 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4684368009 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read -system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read -system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written -system.cpu.num_mem_refs 1677713084 # number of memory refs -system.cpu.num_load_insts 1239184746 # Number of load instructions -system.cpu.num_store_insts 438528338 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11797662696.997999 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 248500691 # Number of branches fetched -system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction -system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction -system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction -system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 4686862596 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9108581 # number of replacements -system.cpu.dcache.tags.tagsinuse 4084.589706 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 58922805500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4084.589706 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 898 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2768 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits -system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses -system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 152690255000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64265951000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64265951000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 216956206000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 216956206000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 216956206000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 216956206000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21139.890071 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21139.890071 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.261420 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.261420 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23808.174700 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23808.174700 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3669049 # number of writebacks -system.cpu.dcache.writebacks::total 3669049 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62376124000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 62376124000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 207843529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 207843529000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20139.890071 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10 # number of replacements -system.cpu.icache.tags.tagsinuse 555.760511 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 555.760511 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.271367 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.271367 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits -system.cpu.icache.overall_hits::total 4013232207 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses -system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 42528500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 42528500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 42528500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 42528500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 42528500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 42528500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63005.185185 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63005.185185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63005.185185 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 10 # number of writebacks -system.cpu.icache.writebacks::total 10 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41853500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 41853500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41853500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 41853500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41853500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 41853500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62005.185185 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1938075 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31745.660470 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16250887 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1970843 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.245653 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 320350195000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11.856683 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.308015 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000362 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000772 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.967666 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.968801 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 435 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 786 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28399 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 147746387 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 147746387 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3669049 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3669049 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095863 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095863 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046986 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6046986 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7142849 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7142849 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7142849 # number of overall hits -system.cpu.l2cache.overall_hits::total 7142849 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 793964 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 793964 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1175864 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1175864 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1969828 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1970503 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1969828 # number of overall misses -system.cpu.l2cache.overall_misses::total 1970503 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48034822000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 48034822000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40839500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 40839500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71139776000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 71139776000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 40839500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 119215437500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 40839500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 119215437500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3669049 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3669049 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 675 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222850 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7222850 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420125 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.420125 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses 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miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1032938 # number of writebacks -system.cpu.l2cache.writebacks::total 1032938 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 213 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 213 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793964 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 793964 # number of ReadExReq MSHR misses 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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40095182000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40095182000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34089500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34089500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59381136000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59381136000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34089500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99476318000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 99510407500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34089500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99476318000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 99510407500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162798 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162798 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216222 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.216222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1186 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1186 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4701987 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6344669 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818030464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818074304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1938075 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66108032 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11051427 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000107 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010359 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11050241 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1186 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11051427 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12780030500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3907605 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1937102 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1176539 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1032938 # Transaction distribution -system.membus.trans_dist::CleanEvict 904164 # Transaction distribution -system.membus.trans_dist::ReadExReq 793964 # Transaction distribution -system.membus.trans_dist::ReadExResp 793964 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1176539 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5878108 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192220224 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1970503 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1970503 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1970503 # Request fanout histogram -system.membus.reqLayer0.occupancy 8039359500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9852515000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +sim_seconds 5.898831 +sim_ticks 5898831348500 +final_tick 5898831348500 +sim_freq 1000000000000 +host_inst_rate 712175 +host_op_rate 1109633 +host_tick_rate 1396571526 +host_mem_usage 285208 +host_seconds 4223.79 +sim_insts 3008081022 +sim_ops 4686862596 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 +system.physmem.bytes_read::cpu.inst 43200 +system.physmem.bytes_read::cpu.data 126068992 +system.physmem.bytes_read::total 126112192 +system.physmem.bytes_inst_read::cpu.inst 43200 +system.physmem.bytes_inst_read::total 43200 +system.physmem.bytes_written::writebacks 66108032 +system.physmem.bytes_written::total 66108032 +system.physmem.num_reads::cpu.inst 675 +system.physmem.num_reads::cpu.data 1969828 +system.physmem.num_reads::total 1970503 +system.physmem.num_writes::writebacks 1032938 +system.physmem.num_writes::total 1032938 +system.physmem.bw_read::cpu.inst 7323 +system.physmem.bw_read::cpu.data 21371859 +system.physmem.bw_read::total 21379183 +system.physmem.bw_inst_read::cpu.inst 7323 +system.physmem.bw_inst_read::total 7323 +system.physmem.bw_write::writebacks 11206971 +system.physmem.bw_write::total 11206971 +system.physmem.bw_total::writebacks 11206971 +system.physmem.bw_total::cpu.inst 7323 +system.physmem.bw_total::cpu.data 21371859 +system.physmem.bw_total::total 32586154 +system.pwrStateResidencyTicks::UNDEFINED 5898831348500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 +system.cpu.workload.numSyscalls 46 +system.cpu.pwrStateResidencyTicks::ON 5898831348500 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+system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% +system.cpu.op_class::IntMult 6215 0.00% 64.20% +system.cpu.op_class::IntDiv 904 0.00% 64.20% +system.cpu.op_class::FloatAdd 0 0.00% 64.20% +system.cpu.op_class::FloatCmp 0 0.00% 64.20% +system.cpu.op_class::FloatCvt 0 0.00% 64.20% +system.cpu.op_class::FloatMult 0 0.00% 64.20% +system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% +system.cpu.op_class::FloatDiv 0 0.00% 64.20% +system.cpu.op_class::FloatMisc 0 0.00% 64.20% +system.cpu.op_class::FloatSqrt 0 0.00% 64.20% +system.cpu.op_class::SimdAdd 0 0.00% 64.20% +system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% +system.cpu.op_class::SimdAlu 0 0.00% 64.20% +system.cpu.op_class::SimdCmp 0 0.00% 64.20% +system.cpu.op_class::SimdCvt 0 0.00% 64.20% +system.cpu.op_class::SimdMisc 0 0.00% 64.20% +system.cpu.op_class::SimdMult 0 0.00% 64.20% +system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% +system.cpu.op_class::SimdShift 0 0.00% 64.20% +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% 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+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045 +system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 1186 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1186 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500 +system.cpu.toL2Bus.trans_dist::ReadResp 7223525 +system.cpu.toL2Bus.trans_dist::WritebackDirty 4701987 +system.cpu.toL2Bus.trans_dist::WritebackClean 10 +system.cpu.toL2Bus.trans_dist::CleanEvict 6344669 +system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 +system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 +system.cpu.toL2Bus.pkt_count::total 27335295 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818030464 +system.cpu.toL2Bus.pkt_size::total 818074304 +system.cpu.toL2Bus.snoops 1938075 +system.cpu.toL2Bus.snoopTraffic 66108032 +system.cpu.toL2Bus.snoop_fanout::samples 11051427 +system.cpu.toL2Bus.snoop_fanout::mean 0.000107 +system.cpu.toL2Bus.snoop_fanout::stdev 0.010359 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 11050241 99.99% 99.99% +system.cpu.toL2Bus.snoop_fanout::1 1186 0.01% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 11051427 +system.cpu.toL2Bus.reqLayer0.occupancy 12780030500 +system.cpu.toL2Bus.reqLayer0.utilization 0.2 +system.cpu.toL2Bus.respLayer0.occupancy 1012500 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 13669015500 +system.cpu.toL2Bus.respLayer1.utilization 0.2 +system.membus.snoop_filter.tot_requests 3907605 +system.membus.snoop_filter.hit_single_requests 1937102 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500 +system.membus.trans_dist::ReadResp 1176539 +system.membus.trans_dist::WritebackDirty 1032938 +system.membus.trans_dist::CleanEvict 904164 +system.membus.trans_dist::ReadExReq 793964 +system.membus.trans_dist::ReadExResp 793964 +system.membus.trans_dist::ReadSharedReq 1176539 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108 +system.membus.pkt_count::total 5878108 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224 +system.membus.pkt_size::total 192220224 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1970503 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1970503 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1970503 +system.membus.reqLayer0.occupancy 8039359500 +system.membus.reqLayer0.utilization 0.1 +system.membus.respLayer1.occupancy 9852515000 +system.membus.respLayer1.utilization 0.2 ---------- End Simulation Statistics ---------- |