summaryrefslogtreecommitdiff
path: root/tests/long/se/60.bzip2/ref/x86
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:36 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:36 -0400
commitb63631536d974f31cf99ee280271dc0f7b4c746f (patch)
treeff83820d8dd75de8238e4b7ddaf3b91e4cf8374f /tests/long/se/60.bzip2/ref/x86
parent646c4a23ca44aab5468c896034288151c89be782 (diff)
downloadgem5-b63631536d974f31cf99ee280271dc0f7b4c746f.tar.xz
stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/x86')
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt78
1 files changed, 38 insertions, 40 deletions
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index cc029b4bd..776ec92d3 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu
sim_ticks 5882580526000 # Number of ticks simulated
final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 548624 # Simulator instruction rate (inst/s)
-host_op_rate 854806 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1072884756 # Simulator tick rate (ticks/s)
-host_mem_usage 295308 # Number of bytes of host memory used
-host_seconds 5482.96 # Real time elapsed on the host
+host_inst_rate 645050 # Simulator instruction rate (inst/s)
+host_op_rate 1005047 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1261455450 # Simulator tick rate (ticks/s)
+host_mem_usage 245540 # Number of bytes of host memory used
+host_seconds 4663.33 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
@@ -42,11 +42,9 @@ system.membus.trans_dist::ReadExReq 781295 # Tr
system.membus.trans_dist::ReadExResp 781295 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 190549120 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
@@ -77,15 +75,15 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_busy_cycles 11765161052 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.icache.tags.replacements 10 # number of replacements
-system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 10 # number of replacements
+system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
@@ -155,19 +153,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 1926197 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements 1926197 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits
@@ -290,15 +288,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 9108581 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 9108581 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
@@ -396,12 +394,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Tr
system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1350 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21923310 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 21924660 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 43200 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819880512 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 819923712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)