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authorNilay Vaish <nilay@cs.wisc.edu>2014-10-11 16:18:51 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2014-10-11 16:18:51 -0500
commit1efe42fa97ed03662666cafee1b9dec9dfe524e9 (patch)
treedd35dfa8f257445840ea3afe71ebdce4d8e4030e /tests/long/se/60.bzip2/ref/x86
parent8e07b36d2b6c1db8c4196336acc66d16e63f8ff3 (diff)
downloadgem5-1efe42fa97ed03662666cafee1b9dec9dfe524e9.tar.xz
stats: updates due to changes to x86, stale configs.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/x86')
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini7
2 files changed, 8 insertions, 6 deletions
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index abb41bc37..36079bdaf 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -158,6 +155,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index eedfe9da7..1cf904013 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -267,6 +268,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8