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authorAli Saidi <Ali.Saidi@ARM.com>2012-06-29 11:19:03 -0400
committerAli Saidi <Ali.Saidi@ARM.com>2012-06-29 11:19:03 -0400
commit3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch)
tree63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/se/60.bzip2/ref
parentaf2b14a362281f36347728e13dcd6b2c4d3c4991 (diff)
downloadgem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/se/60.bzip2/ref')
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini2
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt670
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini2
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt1060
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini2
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt294
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini2
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt1158
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini2
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt78
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini2
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt372
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini2
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt294
21 files changed, 1998 insertions, 1998 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
index 1fcd4f24c..4a4e79f41 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
@@ -191,7 +191,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
index 0482efbeb..74ab835bf 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 13:44:37
+gem5 compiled Jun 28 2012 22:05:18
+gem5 started Jun 28 2012 22:25:40
gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@@ -23,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 1009998808500 because target called exit()
+Exiting @ tick 991340143500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index 0ddfc2b1c..35d38838f 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.009999 # Number of seconds simulated
-sim_ticks 1009998808500 # Number of ticks simulated
-final_tick 1009998808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.991340 # Number of seconds simulated
+sim_ticks 991340143500 # Number of ticks simulated
+final_tick 991340143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 98665 # Simulator instruction rate (inst/s)
-host_op_rate 98665 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 54760444 # Simulator tick rate (ticks/s)
-host_mem_usage 215204 # Number of bytes of host memory used
-host_seconds 18443.95 # Real time elapsed on the host
+host_inst_rate 147354 # Simulator instruction rate (inst/s)
+host_op_rate 147354 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 80272080 # Simulator tick rate (ticks/s)
+host_mem_usage 218972 # Number of bytes of host memory used
+host_seconds 12349.75 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 172563072 # Number of bytes read from this memory
-system.physmem.bytes_read::total 172618048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 137579712 # Number of bytes read from this memory
+system.physmem.bytes_read::total 137634688 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 74938304 # Number of bytes written to this memory
-system.physmem.bytes_written::total 74938304 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 67105088 # Number of bytes written to this memory
+system.physmem.bytes_written::total 67105088 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2696298 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2697157 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1170911 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1170911 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 54432 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 170854728 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 170909160 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 54432 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 54432 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 74196428 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 74196428 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 74196428 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 54432 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 170854728 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 245105588 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 2149683 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2150542 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1048517 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1048517 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 55456 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 138781540 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 138836996 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 55456 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 55456 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 67691285 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 67691285 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 67691285 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 55456 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 138781540 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 206528281 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 444614444 # DTB read hits
+system.cpu.dtb.read_hits 444614343 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 449511522 # DTB read accesses
-system.cpu.dtb.write_hits 160920906 # DTB write hits
+system.cpu.dtb.read_accesses 449511421 # DTB read accesses
+system.cpu.dtb.write_hits 160920087 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 162622210 # DTB write accesses
-system.cpu.dtb.data_hits 605535350 # DTB hits
+system.cpu.dtb.write_accesses 162621391 # DTB write accesses
+system.cpu.dtb.data_hits 605534430 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 612133732 # DTB accesses
-system.cpu.itb.fetch_hits 231980230 # ITB hits
+system.cpu.dtb.data_accesses 612132812 # DTB accesses
+system.cpu.itb.fetch_hits 232194533 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 231980252 # ITB accesses
+system.cpu.itb.fetch_accesses 232194555 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 2019997618 # number of cpu cycles simulated
+system.cpu.numCycles 1982680288 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 328891112 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 253883187 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 140042357 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 232477361 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 138151285 # Number of BTB hits
+system.cpu.branch_predictor.lookups 328915928 # Number of BP lookups
+system.cpu.branch_predictor.condPredicted 253819011 # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect 140072488 # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups 231593889 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 138169193 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 59.425694 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 175108073 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 153783039 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 1669728742 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct 59.660120 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 175201939 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 153713989 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 1669764044 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 3045931359 # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses 3045966661 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads 236 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 651109695 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 617989652 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 121368305 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 12075594 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 133443899 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 81756170 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 62.009227 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 1139611303 # Number of Instructions Executed.
+system.cpu.regfile_manager.floatRegFileAccesses 581 # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards 651015392 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 617989806 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 121318277 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 12155753 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 133474030 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 81726039 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 62.023228 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 1139614733 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 1746428176 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 1746574278 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 7533729 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 443112454 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 1576885164 # Number of cycles cpu stages are processed.
-system.cpu.activity 78.063714 # Percentage of cycles cpu is active
+system.cpu.timesIdled 7486032 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 405569141 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 1577111147 # Number of cycles cpu stages are processed.
+system.cpu.activity 79.544400 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
@@ -114,144 +114,144 @@ system.cpu.committedInsts 1819780127 # Nu
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
-system.cpu.cpi 1.110023 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 1.089516 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 1.110023 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.900882 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 1.089516 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.917838 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.900882 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 829317091 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 1190680527 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 58.944650 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 1087591326 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 932406292 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 46.158782 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 1046003601 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 973994017 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 48.217582 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 1610294122 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 409703496 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 20.282375 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 997062989 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 1022934629 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 50.640388 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total 0.917838 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 791779407 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 1190900881 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 60.065200 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 1050371352 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 932308936 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 47.022656 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 1008674680 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 974005608 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 49.125702 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 1572973951 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 409706337 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 20.664266 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 959730175 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 1022950113 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 51.594305 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.tagsinuse 666.311000 # Cycle average of tags in use
-system.cpu.icache.total_refs 231979155 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 666.725255 # Cycle average of tags in use
+system.cpu.icache.total_refs 232193463 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 270057.223516 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 270306.708964 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 666.311000 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.325347 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.325347 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 231979155 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 231979155 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 231979155 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 231979155 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 231979155 # number of overall hits
-system.cpu.icache.overall_hits::total 231979155 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses
-system.cpu.icache.overall_misses::total 1072 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 58539000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 58539000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 58539000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 58539000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 58539000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 58539000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 231980227 # number of ReadReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250216 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250306 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470613 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.470613 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188435 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417455 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417455 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.295991 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.295991 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.279395 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.540678 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.597095 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.619831 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40112.619831 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.861467 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40024.167616 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.241229 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40086.156385 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40086.156385 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.861467 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40046.914592 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40046.952117 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.861467 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40046.914592 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40046.952117 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index b6ae8cce3..b3f63cedd 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -489,7 +489,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 3e17983a4..41442f622 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 13:48:46
+gem5 compiled Jun 28 2012 22:05:18
+gem5 started Jun 28 2012 22:26:23
gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@@ -23,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 614317285000 because target called exit()
+Exiting @ tick 607216877500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index ad65e54b6..66e8bd283 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.614317 # Number of seconds simulated
-sim_ticks 614317285000 # Number of ticks simulated
-final_tick 614317285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.607217 # Number of seconds simulated
+sim_ticks 607216877500 # Number of ticks simulated
+final_tick 607216877500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 134863 # Simulator instruction rate (inst/s)
-host_op_rate 134863 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47722573 # Simulator tick rate (ticks/s)
-host_mem_usage 216172 # Number of bytes of host memory used
-host_seconds 12872.68 # Real time elapsed on the host
+host_inst_rate 209626 # Simulator instruction rate (inst/s)
+host_op_rate 209626 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 73321119 # Simulator tick rate (ticks/s)
+host_mem_usage 219996 # Number of bytes of host memory used
+host_seconds 8281.61 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 62784 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 173186944 # Number of bytes read from this memory
-system.physmem.bytes_read::total 173249728 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 62784 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 62784 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 75020608 # Number of bytes written to this memory
-system.physmem.bytes_written::total 75020608 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 981 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2706046 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2707027 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1172197 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1172197 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 102201 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 281917745 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 282019947 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 102201 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 102201 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 122120295 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 122120295 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 122120295 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 102201 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 281917745 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 404140242 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 138164352 # Number of bytes read from this memory
+system.physmem.bytes_read::total 138226304 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 67205952 # Number of bytes written to this memory
+system.physmem.bytes_written::total 67205952 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2158818 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2159786 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1050093 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1050093 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 102026 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 227537075 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 227639101 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 102026 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 102026 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 110678663 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 110678663 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 110678663 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 102026 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 227537075 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 338317764 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 613430411 # DTB read hits
-system.cpu.dtb.read_misses 10984160 # DTB read misses
+system.cpu.dtb.read_hits 612238035 # DTB read hits
+system.cpu.dtb.read_misses 10898868 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 624414571 # DTB read accesses
-system.cpu.dtb.write_hits 208466528 # DTB write hits
-system.cpu.dtb.write_misses 6835381 # DTB write misses
+system.cpu.dtb.read_accesses 623136903 # DTB read accesses
+system.cpu.dtb.write_hits 208056215 # DTB write hits
+system.cpu.dtb.write_misses 6766994 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 215301909 # DTB write accesses
-system.cpu.dtb.data_hits 821896939 # DTB hits
-system.cpu.dtb.data_misses 17819541 # DTB misses
+system.cpu.dtb.write_accesses 214823209 # DTB write accesses
+system.cpu.dtb.data_hits 820294250 # DTB hits
+system.cpu.dtb.data_misses 17665862 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 839716480 # DTB accesses
-system.cpu.itb.fetch_hits 401793450 # ITB hits
-system.cpu.itb.fetch_misses 51 # ITB misses
+system.cpu.dtb.data_accesses 837960112 # DTB accesses
+system.cpu.itb.fetch_hits 401011528 # ITB hits
+system.cpu.itb.fetch_misses 57 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 401793501 # ITB accesses
+system.cpu.itb.fetch_accesses 401011585 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -67,146 +67,146 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 1228634571 # number of cpu cycles simulated
+system.cpu.numCycles 1214433756 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 381761173 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 293769294 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 18987814 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 267293652 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 262906896 # Number of BTB hits
+system.cpu.BPredUnit.lookups 380951023 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 293099658 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 18933784 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 266477220 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 262392566 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 25187123 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 6338 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 413237757 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3162516337 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 381761173 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 288094019 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 577364277 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 136217023 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 121997880 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 25151704 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 6168 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 412376649 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3157323952 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 380951023 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 287544270 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 576306152 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 134891835 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 111419989 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1099 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 401793450 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10461001 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1223060627 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.585740 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.163188 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 1063 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 401011528 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 10506825 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1209281794 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.610908 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.168401 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 645696350 52.79% 52.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 43491890 3.56% 56.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 22343235 1.83% 58.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 40947227 3.35% 61.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 127434510 10.42% 71.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 63845944 5.22% 77.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 40777509 3.33% 80.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 30328214 2.48% 82.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 208195748 17.02% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 632975642 52.34% 52.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 43351030 3.58% 55.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 22268396 1.84% 57.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 40872577 3.38% 61.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 127179039 10.52% 71.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 63789232 5.27% 76.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 40665333 3.36% 80.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 30280275 2.50% 82.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 207900270 17.19% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1223060627 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.310720 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.574009 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 442798352 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 107558051 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 546235232 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 16010373 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 110458619 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 60401844 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 1104 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3083471433 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2212 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 110458619 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 464144259 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 59142722 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 6290 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 539650759 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 49657978 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3001214428 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 543640 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1796675 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 45123611 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2245055787 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3876991628 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3875592361 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1399267 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1209281794 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.313686 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.599832 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 441212287 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 97730865 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 545630156 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 15531465 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 109177021 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 60290905 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 1025 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3078047382 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2151 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 109177021 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 462067522 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 51929068 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 5163 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 539154184 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 46948836 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2995870549 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 446955 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1708785 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 42808765 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2241183009 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3870137990 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3868740839 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1397151 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 868852824 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 246 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 246 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 105587598 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 677972013 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 251679590 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 61268278 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 33927488 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2695905085 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 208 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2494910980 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3371495 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 947658243 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 400911726 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1223060627 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.039892 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.968690 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 864980046 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 207 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 206 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 100505126 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 676579077 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 251278116 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 61563067 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 34698773 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2690247704 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 183 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2489728191 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3267337 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 942739143 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 400071480 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 154 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1209281794 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.058849 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.971213 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 388423198 31.76% 31.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 198296660 16.21% 47.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 183821950 15.03% 63.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 153332369 12.54% 75.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 135876340 11.11% 86.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 79653803 6.51% 93.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 63718799 5.21% 98.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 14613920 1.19% 99.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 5323588 0.44% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 378679312 31.31% 31.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 195809975 16.19% 47.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 182681515 15.11% 62.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 152412696 12.60% 75.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 135959135 11.24% 86.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 80206603 6.63% 93.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 63601344 5.26% 98.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 14610233 1.21% 99.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 5320981 0.44% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1223060627 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1209281794 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2019639 10.76% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 12227310 65.14% 75.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4524424 24.10% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1977743 10.56% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 12229984 65.27% 75.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4528924 24.17% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1630534588 65.35% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93 0.00% 65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1627060855 65.35% 65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 100 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 292 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 176 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 286 0.00% 65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 14 0.00% 65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 171 0.00% 65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued
@@ -228,86 +228,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 642000765 25.73% 91.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 222374992 8.91% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 640749326 25.74% 91.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 221917384 8.91% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2494910980 # Type of FU issued
-system.cpu.iq.rate 2.030637 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 18771373 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007524 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6233033546 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3642313752 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2391820907 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1991909 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1355027 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 871735 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2512703438 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 978915 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 57347014 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2489728191 # Type of FU issued
+system.cpu.iq.rate 2.050114 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 18736651 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.007526 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6208757898 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3631737993 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2386612184 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1984266 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1351861 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 870224 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2507489711 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 975131 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 57077193 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 233376350 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 247116 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 107150 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 90951088 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 231983414 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 247523 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 104727 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 90549614 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 227 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 162717 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 172 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 177103 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 110458619 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 22362549 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1121439 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2838563958 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 17898504 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 677972013 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 251679590 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 208 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 216005 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 15651 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 107150 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 13325619 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 8884381 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 22210000 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2442758638 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 624415478 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 52152342 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 109177021 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 19521566 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 973961 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2832586299 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 17875212 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 676579077 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 251278116 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 183 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 178484 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 13307 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 104727 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 13292243 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 8865054 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 22157297 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2437364251 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 623138442 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 52363940 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 142658665 # number of nop insts executed
-system.cpu.iew.exec_refs 839717432 # number of memory reference insts executed
-system.cpu.iew.exec_branches 299305457 # Number of branches executed
-system.cpu.iew.exec_stores 215301954 # Number of stores executed
-system.cpu.iew.exec_rate 1.988190 # Inst execution rate
-system.cpu.iew.wb_sent 2421432535 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2392692642 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1370537618 # num instructions producing a value
-system.cpu.iew.wb_consumers 1736169101 # num instructions consuming a value
+system.cpu.iew.exec_nop 142338412 # number of nop insts executed
+system.cpu.iew.exec_refs 837961692 # number of memory reference insts executed
+system.cpu.iew.exec_branches 298501873 # Number of branches executed
+system.cpu.iew.exec_stores 214823250 # Number of stores executed
+system.cpu.iew.exec_rate 2.006996 # Inst execution rate
+system.cpu.iew.wb_sent 2416135407 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2387482408 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1367770503 # num instructions producing a value
+system.cpu.iew.wb_consumers 1732591741 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.947440 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.789403 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.965922 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.789436 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitCommittedOps 1819780126 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 782630603 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 773736355 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 18986848 # The number of times a branch was mispredicted
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::1 179628091 16.14% 69.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 90469983 8.13% 77.24% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::8 89394462 8.03% 100.00% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::2 90628498 8.24% 77.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 53598095 4.87% 81.87% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::6 22568883 2.05% 89.80% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::8 89144280 8.10% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::total 1100104773 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -318,70 +318,70 @@ system.cpu.commit.branches 214632552 # Nu
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 89394462 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.idleCycles 5573944 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
-system.cpu.cpi 0.707721 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.707721 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.412986 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.412986 # IPC: Total IPC of All Threads
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-system.cpu.fp_regfile_writes 577 # number of floating regfile writes
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+system.cpu.cpi_total 0.699541 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.429509 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.429509 # IPC: Total IPC of All Threads
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -390,301 +390,301 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.l2cache.ReadReq_hits::cpu.data 5920236 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 5920236 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 3416687 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 3416687 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 1101316 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 1101316 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data 7021552 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 7021552 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data 7021552 # number of overall hits
+system.cpu.l2cache.overall_hits::total 7021552 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 968 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1376308 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1377276 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 782510 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 782510 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 968 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 2158818 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 2159786 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 968 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 2158818 # number of overall misses
+system.cpu.l2cache.overall_misses::total 2159786 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 33271000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 47267569500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 47300840500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 26934706500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 26934706500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 33271000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 74202276000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 74235547000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 33271000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 74202276000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 74235547000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 968 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 7296544 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 7297512 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 3416687 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 3416687 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883826 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1883826 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 968 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 9180370 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 9181338 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 968 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 9180370 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 9181338 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250005 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.250106 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.468092 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.468092 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188625 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.188732 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415383 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.415383 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.294753 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.294828 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.235156 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.235237 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.294753 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.294828 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34371.049949 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34338.518024 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34338.535509 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34465.947843 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34465.947843 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34371.049949 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34380.041027 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34380.037768 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34371.049949 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34380.041027 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34380.037768 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 17522000 # number of cycles access was blocked
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.235156 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.235237 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34370.867769 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34343.743915 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34343.762979 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34420.910276 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34420.910276 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34370.867769 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34371.714522 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34371.714142 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34370.867769 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34371.714522 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34371.714142 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 10439000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 1684 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 1011 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10404.988124 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10325.420376 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1172197 # number of writebacks
-system.cpu.l2cache.writebacks::total 1172197 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 981 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1824281 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1825262 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 881765 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 881765 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 981 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 2706046 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 2707027 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 981 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 2706046 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 2707027 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 30568000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56848109000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56878677000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 27575743000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 27575743000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30568000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 84423852000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 84454420000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30568000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84423852000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 84454420000 # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks 1050093 # number of writebacks
+system.cpu.l2cache.writebacks::total 1050093 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376308 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1377276 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782510 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 782510 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 2158818 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 2159786 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 2158818 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 2159786 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 30173000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42897858500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 42928031500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 24429166000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 24429166000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30173000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67327024500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 67357197500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30173000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67327024500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 67357197500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250005 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250106 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.468092 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.468092 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188625 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188732 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415383 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415383 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.294828 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235156 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.235237 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.294828 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31160.040775 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31161.925712 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31161.924699 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31273.347207 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31273.347207 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31198.218562 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31198.218562 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235156 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.235237 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31170.454545 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31168.792523 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31168.793691 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31218.982505 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31218.982505 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31170.454545 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31186.984961 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31186.977552 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31170.454545 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31186.984961 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31186.977552 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index f89f54e31..51c5aee6c 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -158,7 +158,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 267941dc1..80ad9dac8 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 13:42:46
+gem5 compiled Jun 28 2012 22:05:18
+gem5 started Jun 28 2012 22:33:25
gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@@ -23,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2663443716000 because target called exit()
+Exiting @ tick 2640486390000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 3da64d83e..02104b02f 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.663444 # Number of seconds simulated
-sim_ticks 2663443716000 # Number of ticks simulated
-final_tick 2663443716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.640486 # Number of seconds simulated
+sim_ticks 2640486390000 # Number of ticks simulated
+final_tick 2640486390000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1479188 # Simulator instruction rate (inst/s)
-host_op_rate 1479188 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2164950496 # Simulator tick rate (ticks/s)
-host_mem_usage 214896 # Number of bytes of host memory used
-host_seconds 1230.26 # Real time elapsed on the host
+host_inst_rate 2162683 # Simulator instruction rate (inst/s)
+host_op_rate 2162683 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3138035754 # Simulator tick rate (ticks/s)
+host_mem_usage 218976 # Number of bytes of host memory used
+host_seconds 841.45 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 172562880 # Number of bytes read from this memory
-system.physmem.bytes_read::total 172614208 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 137580288 # Number of bytes read from this memory
+system.physmem.bytes_read::total 137631616 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 74939072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 74939072 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 67105600 # Number of bytes written to this memory
+system.physmem.bytes_written::total 67105600 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2696295 # Number of read requests responded to by this memory
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-system.physmem.num_writes::total 1170923 # Number of write requests responded to by this memory
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-system.physmem.bw_read::total 64808656 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 19271 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 19271 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_write::total 28136158 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 28136158 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 19271 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.num_writes::total 1048525 # Number of write requests responded to by this memory
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+system.physmem.bw_write::total 25414106 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 25414106 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu.data 52104146 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 77537690 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1819780127 # Number of instructions committed
@@ -86,18 +86,18 @@ system.cpu.num_mem_refs 611922547 # nu
system.cpu.num_load_insts 449492741 # Number of load instructions
system.cpu.num_store_insts 162429806 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
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+system.cpu.num_busy_cycles 5280972780 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1 # number of replacements
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system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits
@@ -168,14 +168,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9107638 # number of replacements
-system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use
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system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
@@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n
system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
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system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
@@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053
system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24508.481513 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24508.481513 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33767.845574 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33767.845574 # average WriteReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses
@@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734
system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
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@@ -258,65 +258,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053
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system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 3058802 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 3058802 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 3389919 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 3389919 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses
@@ -326,16 +326,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 802
system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250202 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.250285 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470663 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.470663 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188425 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.188515 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417509 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.417509 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.295915 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.295977 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.235926 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.235993 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.295915 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.295977 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.235926 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.235993 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
@@ -355,41 +355,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1170923 # number of writebacks
-system.cpu.l2cache.writebacks::total 1170923 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 1048525 # number of writebacks
+system.cpu.l2cache.writebacks::total 1048525 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1807062 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1807864 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889233 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 889233 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360883 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1361685 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788809 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 788809 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 2696295 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 2697097 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 2149692 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 2150494 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 2696295 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 2697097 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 2149692 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 2150494 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32080000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72282480000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72314560000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35569320000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35569320000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54435320000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54467400000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31552360000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31552360000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32080000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107851800000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 107883880000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85987680000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 86019760000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32080000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107851800000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 107883880000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85987680000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 86019760000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250202 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250285 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470663 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.470663 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188425 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188515 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417509 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417509 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.295977 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.235993 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.295977 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.235993 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 48015577c..c94040a4a 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -507,7 +507,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index 2f52f2c05..1148e0586 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 12:14:06
-gem5 started Jun 4 2012 18:36:31
+gem5 compiled Jun 28 2012 22:10:14
+gem5 started Jun 29 2012 01:20:26
gem5 executing on zizzer
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@@ -24,4 +24,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 463993693500 because target called exit()
+Exiting @ tick 458035985000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 7863d76cc..f8f6b4a6a 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.463994 # Number of seconds simulated
-sim_ticks 463993693500 # Number of ticks simulated
-final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.458036 # Number of seconds simulated
+sim_ticks 458035985000 # Number of ticks simulated
+final_tick 458035985000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 128371 # Simulator instruction rate (inst/s)
-host_op_rate 143208 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38563333 # Simulator tick rate (ticks/s)
-host_mem_usage 232076 # Number of bytes of host memory used
-host_seconds 12031.99 # Real time elapsed on the host
-sim_insts 1544563066 # Number of instructions simulated
-sim_ops 1723073879 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 49344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 189746304 # Number of bytes read from this memory
-system.physmem.bytes_read::total 189795648 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 49344 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 49344 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 78222144 # Number of bytes written to this memory
-system.physmem.bytes_written::total 78222144 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 771 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2964786 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2965557 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1222221 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1222221 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 106346 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 408941558 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 409047904 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 106346 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 106346 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 168584498 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 168584498 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 168584498 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 106346 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 408941558 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 577632403 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 197390 # Simulator instruction rate (inst/s)
+host_op_rate 220203 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 58535443 # Simulator tick rate (ticks/s)
+host_mem_usage 234800 # Number of bytes of host memory used
+host_seconds 7824.93 # Real time elapsed on the host
+sim_insts 1544563073 # Number of instructions simulated
+sim_ops 1723073885 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 156358784 # Number of bytes read from this memory
+system.physmem.bytes_read::total 156407104 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 71946432 # Number of bytes written to this memory
+system.physmem.bytes_written::total 71946432 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2443106 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2443861 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1124163 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1124163 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 105494 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 341367904 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 341473398 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 105494 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 105494 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 157075938 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 157075938 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 157075938 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 105494 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 341367904 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 498549336 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -77,322 +77,322 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 927987388 # number of cpu cycles simulated
+system.cpu.numCycles 916071971 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 300553850 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 246366147 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 16098585 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 170916236 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 156311774 # Number of BTB hits
+system.cpu.BPredUnit.lookups 300386365 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 246254548 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 16072669 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 170403157 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 156239351 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 18335288 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 425 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 292740519 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2158326699 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 300553850 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 174647062 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 429206926 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 83759589 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 129259054 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 200 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 283730265 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 5372560 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 918446800 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.613763 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.238744 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 18292614 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 292465712 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2157283635 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 300386365 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 174531965 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 428963032 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 83531263 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 119911343 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 109 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 283465873 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 5375761 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 908345220 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.641582 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.245010 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 489239924 53.27% 53.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 23020148 2.51% 55.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 38764254 4.22% 60.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 47809734 5.21% 65.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 40766066 4.44% 69.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 46976906 5.11% 74.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 39072572 4.25% 79.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 18137057 1.97% 80.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 174660139 19.02% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 479382246 52.78% 52.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 23075019 2.54% 55.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 38696357 4.26% 59.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 47758356 5.26% 64.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 40740735 4.49% 69.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 46836926 5.16% 74.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 39064245 4.30% 78.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 18137906 2.00% 80.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 174653430 19.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 918446800 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.323877 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.325815 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 322039794 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 109288431 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 403236235 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 16643003 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 67239337 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 46165390 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 810 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2346870217 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2646 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 67239337 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 343676895 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 50827249 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 9551 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 397069716 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 59624052 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2289998307 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 23088 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4666333 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 46320806 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2264655243 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 10570139009 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 10570134861 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4148 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1706319999 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 558335244 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4462 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4454 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 136929133 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 624839821 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 218742392 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 85961960 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 66558298 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2190567677 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 692 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2016055896 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 4892741 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 462785080 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1074735939 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 918446800 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.195071 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.923309 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 908345220 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.327907 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.354928 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 321276302 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 100437637 # Number of cycles decode is blocked
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+system.cpu.decode.UnblockCycles 16012907 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 67004358 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 46143588 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 709 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2345766913 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2404 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 67004358 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 342772787 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 44470406 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 13938 # count of cycles rename stalled for serializing inst
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+system.cpu.rename.UnblockCycles 57089388 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2288809868 # Number of instructions processed by rename
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+system.cpu.rename.IQFullEvents 4587251 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 43867874 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2263371035 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 10565210641 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 10565207285 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 3356 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1706320010 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 557051025 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 5363 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 5361 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 133306732 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 624412648 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 218802984 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 85974356 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 66146404 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2189209490 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1708 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2014638202 # Number of instructions issued
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+system.cpu.iq.iqSquashedOperandsExamined 1075835396 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::1 138877340 15.12% 42.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 158309179 17.24% 59.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 116273452 12.66% 72.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 125754756 13.69% 86.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 75525220 8.22% 94.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 39163504 4.26% 98.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 10678346 1.16% 99.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2670659 0.29% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 244431658 26.91% 26.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 136114338 14.98% 41.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 157116427 17.30% 59.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 116129005 12.78% 71.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 125782921 13.85% 85.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 75959694 8.36% 94.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 39392857 4.34% 98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 10729861 1.18% 99.70% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 918446800 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 908345220 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.fu_full::IntMult 4827 0.02% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 19025079 75.82% 79.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 5238831 20.88% 100.00% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.18% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 19003801 75.87% 79.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 5245876 20.94% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1234276939 61.22% 61.22% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 932607 0.05% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 29 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 587048024 29.12% 90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 193798201 9.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1233307061 61.22% 61.22% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 930228 0.05% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 49 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 28 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 10 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 586604414 29.12% 90.38% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 193796407 9.62% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2016055896 # Type of FU issued
-system.cpu.iq.rate 2.172504 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 25092977 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.012447 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4980543862 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2653539100 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1958126109 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 448 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 790 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2041148646 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 227 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 63700277 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2014638202 # Type of FU issued
+system.cpu.iq.rate 2.199214 # Inst issue rate
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+system.cpu.iq.fu_busy_rate 0.012433 # FU busy rate (busy events/executed inst)
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+system.cpu.iq.int_inst_queue_writes 2650923657 # Number of integer instruction queue writes
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+system.cpu.iq.fp_inst_queue_reads 370 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2039685190 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 188 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 138913044 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 284373 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 189336 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 43895340 # Number of stores squashed
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system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 451092 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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-system.cpu.iew.iewBlockCycles 23164250 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1316440 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2190576494 # Number of instructions dispatched to IQ
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-system.cpu.iew.iewDispLoadInsts 624839821 # Number of dispatched load instructions
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-system.cpu.iew.iewIQFullEvents 207277 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 49894 # Number of times the LSQ has become full, causing a stall
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-system.cpu.iew.iewExecutedInsts 1986583692 # Number of executed instructions
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+system.cpu.iew.iewUnblockCycles 1127497 # Number of cycles IEW is unblocking
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 8125 # number of nop insts executed
-system.cpu.iew.exec_refs 763312359 # number of memory reference insts executed
-system.cpu.iew.exec_branches 238194699 # Number of branches executed
-system.cpu.iew.exec_stores 190834919 # Number of stores executed
-system.cpu.iew.exec_rate 2.140744 # Inst execution rate
-system.cpu.iew.wb_sent 1967109112 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1958126281 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1296093484 # num instructions producing a value
-system.cpu.iew.wb_consumers 2068479796 # num instructions consuming a value
+system.cpu.iew.exec_nop 7967 # number of nop insts executed
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.110079 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.626592 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.135837 # insts written-back per cycle
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 1544563084 # The number of committed instructions
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-system.cpu.commit.branchMispredicts 16098007 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 851207464 # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::stdev 2.756192 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 1544563091 # The number of committed instructions
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 362905349 42.63% 42.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 192760849 22.65% 65.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 73571189 8.64% 73.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 35131293 4.13% 78.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 18689200 2.20% 80.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 30622248 3.60% 83.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 19666355 2.31% 86.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10977227 1.29% 87.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106883754 12.56% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 352627350 41.91% 41.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 193034897 22.94% 64.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 73667996 8.76% 73.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 35236864 4.19% 77.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 18719576 2.22% 80.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 30675778 3.65% 83.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 19663987 2.34% 86.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10964014 1.30% 87.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 106750401 12.69% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 851207464 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 1544563084 # Number of instructions committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.membars 62 # Number of memory barriers committed
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system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
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+system.cpu.commit.int_insts 1536941881 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 106883754 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 106750401 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2934966123 # The number of ROB reads
-system.cpu.rob.rob_writes 4448699546 # The number of ROB writes
-system.cpu.timesIdled 899596 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 9540588 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1544563066 # Number of Instructions Simulated
-system.cpu.committedOps 1723073879 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 1544563066 # Number of Instructions Simulated
-system.cpu.cpi 0.600809 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.600809 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.664422 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.664422 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 9951953141 # number of integer regfile reads
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-system.cpu.misc_regfile_reads 2897977277 # number of misc regfile reads
-system.cpu.misc_regfile_writes 138 # number of misc regfile writes
-system.cpu.icache.replacements 28 # number of replacements
-system.cpu.icache.tagsinuse 641.389873 # Cycle average of tags in use
-system.cpu.icache.total_refs 283729068 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 801 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 354218.561798 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 2923869159 # The number of ROB reads
+system.cpu.rob.rob_writes 4445740607 # The number of ROB writes
+system.cpu.timesIdled 753914 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7726751 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 1544563073 # Number of Instructions Simulated
+system.cpu.committedOps 1723073885 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 1544563073 # Number of Instructions Simulated
+system.cpu.cpi 0.593095 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.593095 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.686072 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.686072 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 9944305109 # number of integer regfile reads
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+system.cpu.misc_regfile_reads 2896410924 # number of misc regfile reads
+system.cpu.misc_regfile_writes 144 # number of misc regfile writes
+system.cpu.icache.replacements 25 # number of replacements
+system.cpu.icache.tagsinuse 627.053723 # Cycle average of tags in use
+system.cpu.icache.total_refs 283464725 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 785 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 361101.560510 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 641.389873 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.313179 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.313179 # Average percentage of cache occupancy
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-system.cpu.icache.demand_hits::total 283729068 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 283729068 # number of overall hits
-system.cpu.icache.overall_hits::total 283729068 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1197 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1197 # number of ReadReq misses
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-system.cpu.icache.overall_misses::total 1197 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 39840000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 33283.208020 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 33283.208020 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 33283.208020 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33621.951220 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 33621.951220 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 33621.951220 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 33621.951220 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 33621.951220 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 33621.951220 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -401,309 +401,309 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.ReadReq_mshr_hits::total 396 # number of ReadReq MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 396 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27579500 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.308135 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31193.904021 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31187.061187 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31187.063761 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.171225 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.171225 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 755 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1612172 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1612927 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830934 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 830934 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 755 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 2443106 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 2443861 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 755 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 2443106 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 2443861 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50285384000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 50308930000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26141067500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26141067500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76426451500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 76449997500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76426451500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 76449997500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208586 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208662 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438747 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438747 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253884 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.253941 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253884 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.253941 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31186.754967 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31191.078868 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31191.076844 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31459.860230 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31459.860230 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31186.754967 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31282.495111 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31282.465533 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31186.754967 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31282.495111 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31282.465533 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index b103ca45f..e60a29e1d 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -95,7 +95,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic
egid=100
env=
errout=cerr
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
index 4559b3892..5ff891bb9 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 12:14:06
-gem5 started Jun 4 2012 18:41:45
+gem5 compiled Jun 28 2012 22:10:14
+gem5 started Jun 29 2012 01:21:22
gem5 executing on zizzer
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@@ -24,4 +24,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 861538205000 because target called exit()
+Exiting @ tick 861538200000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index 6c3e8b909..9f9278806 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -1,38 +1,38 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.861538 # Number of seconds simulated
-sim_ticks 861538205000 # Number of ticks simulated
-final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 861538200000 # Number of ticks simulated
+final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2187855 # Simulator instruction rate (inst/s)
-host_op_rate 2440714 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1220358665 # Simulator tick rate (ticks/s)
-host_mem_usage 221416 # Number of bytes of host memory used
-host_seconds 705.97 # Real time elapsed on the host
-sim_insts 1544563049 # Number of instructions simulated
-sim_ops 1723073862 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 6178262392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1581387672 # Number of bytes read from this memory
-system.physmem.bytes_read::total 7759650064 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 6178262392 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 6178262392 # Number of instructions bytes read from this memory
+host_inst_rate 3167213 # Simulator instruction rate (inst/s)
+host_op_rate 3533259 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1766632085 # Simulator tick rate (ticks/s)
+host_mem_usage 225200 # Number of bytes of host memory used
+host_seconds 487.67 # Real time elapsed on the host
+sim_insts 1544563041 # Number of instructions simulated
+sim_ops 1723073853 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory
+system.physmem.bytes_read::total 7759650027 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 6178262356 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 6178262356 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory
system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1544565598 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 482384188 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2026949786 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 1544565589 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 482384187 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2026949776 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory
system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7171199555 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1835539809 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 9006739363 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7171199555 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7171199555 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 724469778 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 724469778 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7171199555 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2560009587 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 9731209141 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 7171199554 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1835539818 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 9006739373 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7171199554 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7171199554 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 724469782 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 724469782 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7171199554 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2560009600 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 9731209155 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 1723076411 # number of cpu cycles simulated
+system.cpu.numCycles 1723076401 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 1544563049 # Number of instructions committed
-system.cpu.committedOps 1723073862 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
+system.cpu.committedInsts 1544563041 # Number of instructions committed
+system.cpu.committedOps 1723073853 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
-system.cpu.num_func_calls 27330134 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1536941850 # number of integer instructions
+system.cpu.num_func_calls 27330256 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 177498327 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1536941842 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
-system.cpu.num_int_register_reads 7861284536 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written
+system.cpu.num_int_register_reads 7861284498 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu.num_mem_refs 660773816 # number of memory refs
-system.cpu.num_load_insts 485926770 # Number of load instructions
+system.cpu.num_mem_refs 660773815 # number of memory refs
+system.cpu.num_load_insts 485926769 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 1723076411 # Number of busy cycles
+system.cpu.num_busy_cycles 1723076401 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 88ea9515a..e66f558e0 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -176,7 +176,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
index d07a6ceff..4ec39cba0 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 12:14:06
-gem5 started Jun 4 2012 18:44:07
+gem5 compiled Jun 28 2012 22:10:14
+gem5 started Jun 29 2012 01:25:17
gem5 executing on zizzer
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@@ -24,4 +24,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2431419954000 because target called exit()
+Exiting @ tick 2408512388000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index db0ae235a..c9d66243a 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.431420 # Number of seconds simulated
-sim_ticks 2431419954000 # Number of ticks simulated
-final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.408512 # Number of seconds simulated
+sim_ticks 2408512388000 # Number of ticks simulated
+final_tick 2408512388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1031283 # Simulator instruction rate (inst/s)
-host_op_rate 1150922 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1629547552 # Simulator tick rate (ticks/s)
-host_mem_usage 230584 # Number of bytes of host memory used
-host_seconds 1492.08 # Real time elapsed on the host
-sim_insts 1538759609 # Number of instructions simulated
-sim_ops 1717270343 # Number of ops (including micro ops) simulated
+host_inst_rate 1431405 # Simulator instruction rate (inst/s)
+host_op_rate 1597462 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2240478292 # Simulator tick rate (ticks/s)
+host_mem_usage 233776 # Number of bytes of host memory used
+host_seconds 1075.00 # Real time elapsed on the host
+sim_insts 1538759601 # Number of instructions simulated
+sim_ops 1717270334 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 172726592 # Number of bytes read from this memory
-system.physmem.bytes_read::total 172766016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 137819840 # Number of bytes read from this memory
+system.physmem.bytes_read::total 137859264 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 75006720 # Number of bytes written to this memory
-system.physmem.bytes_written::total 75006720 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 67221184 # Number of bytes written to this memory
+system.physmem.bytes_written::total 67221184 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2698853 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2699469 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1171980 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1171980 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 16214 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 71039391 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 71055605 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 16214 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 16214 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 30848937 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 30848937 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 30848937 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 16214 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 71039391 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 101904542 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 2153435 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2154051 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1050331 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1050331 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 16369 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 57221977 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 57238345 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 16369 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 16369 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 27909835 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 27909835 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 27909835 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 16369 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 57221977 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 85148181 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -77,43 +77,43 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 4862839908 # number of cpu cycles simulated
+system.cpu.numCycles 4817024776 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 1538759609 # Number of instructions committed
-system.cpu.committedOps 1717270343 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
+system.cpu.committedInsts 1538759601 # Number of instructions committed
+system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
-system.cpu.num_func_calls 27330134 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1536941850 # number of integer instructions
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+system.cpu.num_int_insts 1536941842 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
-system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written
+system.cpu.num_int_register_reads 9304894672 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu.num_mem_refs 660773816 # number of memory refs
-system.cpu.num_load_insts 485926770 # Number of load instructions
+system.cpu.num_mem_refs 660773815 # number of memory refs
+system.cpu.num_load_insts 485926769 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 4862839908 # Number of busy cycles
+system.cpu.num_busy_cycles 4817024776 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 7 # number of replacements
-system.cpu.icache.tagsinuse 514.872896 # Cycle average of tags in use
-system.cpu.icache.total_refs 1544564961 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.occ_percent::total 0.251403 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 1544564961 # number of ReadReq hits
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-system.cpu.icache.demand_hits::cpu.inst 1544564961 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1544564961 # number of demand (read+write) hits
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system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
@@ -126,12 +126,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 34804000
system.cpu.icache.demand_miss_latency::total 34804000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 34804000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 34804000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1544565599 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1544565599 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
@@ -178,26 +178,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138
system.cpu.icache.overall_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9111140 # number of replacements
-system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use
-system.cpu.dcache.total_refs 645855060 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4083.603265 # Cycle average of tags in use
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system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 25923025000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4083.719979 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.997002 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.997002 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 475158040 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 475158040 # number of ReadReq hits
+system.cpu.dcache.warmup_cycle 25922973000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
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-system.cpu.dcache.demand_hits::total 645854938 # number of demand (read+write) hits
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-system.cpu.dcache.overall_hits::total 645854938 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
@@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 9115236 # n
system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 177140908000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 177140908000 # number of ReadReq miss cycles
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-system.cpu.dcache.WriteReq_miss_latency::total 63824222000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 240965130000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 240965130000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 240965130000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 240965130000 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 654970174 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 654970174 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
@@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.013917
system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24514.084594 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33784.641656 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 26435.424162 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26435.424162 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21930.307786 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 21930.307786 # average ReadReq miss latency
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+system.cpu.dcache.WriteReq_avg_miss_latency::total 31541.854031 # average WriteReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 23922.317974 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23922.317974 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23922.317974 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3061985 # number of writebacks
-system.cpu.dcache.writebacks::total 3061985 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 3385547 # number of writebacks
+system.cpu.dcache.writebacks::total 3385547 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
@@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115236
system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 155462647000 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 58156775000 # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.demand_mshr_miss_latency::total 213619422000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213619422000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 213619422000 # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total 136792051000 # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total 190711866000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
@@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917
system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21514.084594 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21514.084594 # average ReadReq mshr miss latency
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-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30784.641656 # average WriteReq mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.l2cache.occ_percent::writebacks 0.451123 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.000480 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.483110 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.934713 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 5417142 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 5417164 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 3061985 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 3061985 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 999241 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 999241 # number of ReadExReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 5861680 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 5861702 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 3385547 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 3385547 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 1100121 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 1100121 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 6416383 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 6416405 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 6961801 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 6961823 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 6416383 # number of overall hits
-system.cpu.l2cache.overall_hits::total 6416405 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 6961801 # number of overall hits
+system.cpu.l2cache.overall_hits::total 6961823 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 1808945 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 1809561 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 889908 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 889908 # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1364407 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1365023 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 789028 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 789028 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 2698853 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 2699469 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 2153435 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 2154051 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 2698853 # number of overall misses
-system.cpu.l2cache.overall_misses::total 2699469 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 2153435 # number of overall misses
+system.cpu.l2cache.overall_misses::total 2154051 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94065140000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 94097172000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46275216000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 46275216000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70949164000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 70981196000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41029456000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 41029456000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 140340356000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 140372388000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 111978620000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 112010652000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 140340356000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 140372388000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 111978620000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 112010652000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 3061985 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 3061985 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 3385547 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 3385547 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses
@@ -347,16 +347,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 638
system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250335 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.250398 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471063 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.471063 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188817 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.188885 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417663 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.417663 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.296082 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.296128 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.236246 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.236297 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.296082 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.296128 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.236246 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.236297 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
@@ -376,41 +376,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1171980 # number of writebacks
-system.cpu.l2cache.writebacks::total 1171980 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 1050331 # number of writebacks
+system.cpu.l2cache.writebacks::total 1050331 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1808945 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1809561 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889908 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 889908 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1364407 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1365023 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 789028 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 789028 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 2698853 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 2699469 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 2153435 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 2154051 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 2698853 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 2699469 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 2153435 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 2154051 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72357800000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72382440000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35596320000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35596320000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54576280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54600920000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31561120000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31561120000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107954120000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 107978760000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86137400000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 86162040000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107954120000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 107978760000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86137400000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 86162040000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250335 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250398 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471063 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471063 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188817 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188885 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417663 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417663 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.296128 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.236297 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.296128 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.236297 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index 5c77a44a2..643e6799d 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -179,7 +179,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
+cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index 11192711e..5dc44ec4f 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 13:44:28
-gem5 started Jun 4 2012 16:08:32
+gem5 compiled Jun 28 2012 22:08:09
+gem5 started Jun 28 2012 23:47:42
gem5 executing on zizzer
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@@ -24,4 +24,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 5923548078000 because target called exit()
+Exiting @ tick 5900695290000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index e2cb03bbf..faa206e56 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.923548 # Number of seconds simulated
-sim_ticks 5923548078000 # Number of ticks simulated
-final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.900695 # Number of seconds simulated
+sim_ticks 5900695290000 # Number of ticks simulated
+final_tick 5900695290000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 633731 # Simulator instruction rate (inst/s)
-host_op_rate 987410 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1247949692 # Simulator tick rate (ticks/s)
-host_mem_usage 225520 # Number of bytes of host memory used
-host_seconds 4746.62 # Real time elapsed on the host
+host_inst_rate 1070782 # Simulator instruction rate (inst/s)
+host_op_rate 1668375 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2100461088 # Simulator tick rate (ticks/s)
+host_mem_usage 228516 # Number of bytes of host memory used
+host_seconds 2809.24 # Real time elapsed on the host
sim_insts 3008081057 # Number of instructions simulated
sim_ops 4686862651 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 173866880 # Number of bytes read from this memory
-system.physmem.bytes_read::total 173910080 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 139043584 # Number of bytes read from this memory
+system.physmem.bytes_read::total 139086784 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 75176384 # Number of bytes written to this memory
-system.physmem.bytes_written::total 75176384 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 67393856 # Number of bytes written to this memory
+system.physmem.bytes_written::total 67393856 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2716670 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2717345 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1174631 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1174631 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7293 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 29351814 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 29359107 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7293 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7293 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 12691107 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 12691107 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 12691107 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7293 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 29351814 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 42050214 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 2172556 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2173231 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 7321 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 23563932 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 23571253 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7321 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7321 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 11421342 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 11421342 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 11421342 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7321 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 23563932 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 34992595 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 11847096156 # number of cpu cycles simulated
+system.cpu.numCycles 11801390580 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081057 # Number of instructions committed
@@ -54,18 +54,18 @@ system.cpu.num_mem_refs 1677713086 # nu
system.cpu.num_load_insts 1239184749 # Number of load instructions
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 10 # number of replacements
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system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
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system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits
@@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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@@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n
system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
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@@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432
system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
@@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677
system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
@@ -226,65 +226,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432
system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
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@@ -294,16 +294,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 675
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system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
@@ -323,41 +323,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
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