diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/se/60.bzip2/ref | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/se/60.bzip2/ref')
7 files changed, 3143 insertions, 3061 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 617d9f369..ce3c1254b 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.208801 # Number of seconds simulated -sim_ticks 1208800797500 # Number of ticks simulated -final_tick 1208800797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.208729 # Number of seconds simulated +sim_ticks 1208728699500 # Number of ticks simulated +final_tick 1208728699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 309355 # Simulator instruction rate (inst/s) -host_op_rate 309355 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 204748768 # Simulator tick rate (ticks/s) -host_mem_usage 299532 # Number of bytes of host memory used -host_seconds 5903.82 # Real time elapsed on the host +host_inst_rate 339450 # Simulator instruction rate (inst/s) +host_op_rate 339450 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 224654099 # Simulator tick rate (ticks/s) +host_mem_usage 299384 # Number of bytes of host memory used +host_seconds 5380.40 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -18,71 +18,71 @@ system.physmem.bytes_read::cpu.data 124969728 # Nu system.physmem.bytes_read::total 125030976 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 61248 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 61248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65417024 # Number of bytes written to this memory -system.physmem.bytes_written::total 65417024 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65416576 # Number of bytes written to this memory +system.physmem.bytes_written::total 65416576 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 957 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1952652 # Number of read requests responded to by this memory system.physmem.num_reads::total 1953609 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1022141 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1022141 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 50668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 103383228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 103433896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 50668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 50668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54117291 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54117291 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54117291 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 50668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 103383228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 157551187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::writebacks 1022134 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1022134 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 50671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 103389394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103440066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 50671 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 50671 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54120148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54120148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54120148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 50671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 103389394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 157560214 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1953609 # Number of read requests accepted -system.physmem.writeReqs 1022141 # Number of write requests accepted +system.physmem.writeReqs 1022134 # Number of write requests accepted system.physmem.readBursts 1953609 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1022141 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 124949504 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 81472 # Total number of bytes read from write queue -system.physmem.bytesWritten 65415744 # Total number of bytes written to DRAM +system.physmem.writeBursts 1022134 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 124947712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83264 # Total number of bytes read from write queue +system.physmem.bytesWritten 65415296 # Total number of bytes written to DRAM system.physmem.bytesReadSys 125030976 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65417024 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1273 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesWrittenSys 65416576 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1301 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118329 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 897725 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 118310 # Per bank write bursts system.physmem.perBankRdBursts::1 113529 # Per bank write bursts -system.physmem.perBankRdBursts::2 115744 # Per bank write bursts -system.physmem.perBankRdBursts::3 117255 # Per bank write bursts +system.physmem.perBankRdBursts::2 115745 # Per bank write bursts +system.physmem.perBankRdBursts::3 117258 # Per bank write bursts system.physmem.perBankRdBursts::4 117308 # Per bank write bursts -system.physmem.perBankRdBursts::5 117125 # Per bank write bursts -system.physmem.perBankRdBursts::6 119396 # Per bank write bursts -system.physmem.perBankRdBursts::7 124121 # Per bank write bursts -system.physmem.perBankRdBursts::8 126643 # Per bank write bursts -system.physmem.perBankRdBursts::9 129581 # Per bank write bursts -system.physmem.perBankRdBursts::10 128162 # Per bank write bursts -system.physmem.perBankRdBursts::11 129917 # Per bank write bursts -system.physmem.perBankRdBursts::12 125585 # Per bank write bursts -system.physmem.perBankRdBursts::13 124851 # Per bank write bursts -system.physmem.perBankRdBursts::14 122145 # Per bank write bursts -system.physmem.perBankRdBursts::15 122645 # Per bank write bursts -system.physmem.perBankWrBursts::0 61422 # Per bank write bursts -system.physmem.perBankWrBursts::1 61663 # Per bank write bursts -system.physmem.perBankWrBursts::2 60725 # Per bank write bursts -system.physmem.perBankWrBursts::3 61394 # Per bank write bursts -system.physmem.perBankWrBursts::4 61815 # Per bank write bursts +system.physmem.perBankRdBursts::5 117123 # Per bank write bursts +system.physmem.perBankRdBursts::6 119399 # Per bank write bursts +system.physmem.perBankRdBursts::7 124116 # Per bank write bursts +system.physmem.perBankRdBursts::8 126646 # Per bank write bursts +system.physmem.perBankRdBursts::9 129571 # Per bank write bursts +system.physmem.perBankRdBursts::10 128166 # Per bank write bursts +system.physmem.perBankRdBursts::11 129914 # Per bank write bursts +system.physmem.perBankRdBursts::12 125584 # Per bank write bursts +system.physmem.perBankRdBursts::13 124843 # Per bank write bursts +system.physmem.perBankRdBursts::14 122159 # Per bank write bursts +system.physmem.perBankRdBursts::15 122637 # Per bank write bursts +system.physmem.perBankWrBursts::0 61419 # Per bank write bursts +system.physmem.perBankWrBursts::1 61661 # Per bank write bursts +system.physmem.perBankWrBursts::2 60723 # Per bank write bursts +system.physmem.perBankWrBursts::3 61396 # Per bank write bursts +system.physmem.perBankWrBursts::4 61819 # Per bank write bursts system.physmem.perBankWrBursts::5 63308 # Per bank write bursts system.physmem.perBankWrBursts::6 64356 # Per bank write bursts system.physmem.perBankWrBursts::7 65855 # Per bank write bursts -system.physmem.perBankWrBursts::8 65579 # Per bank write bursts -system.physmem.perBankWrBursts::9 66031 # Per bank write bursts -system.physmem.perBankWrBursts::10 65643 # Per bank write bursts -system.physmem.perBankWrBursts::11 65948 # Per bank write bursts -system.physmem.perBankWrBursts::12 64510 # Per bank write bursts -system.physmem.perBankWrBursts::13 64527 # Per bank write bursts -system.physmem.perBankWrBursts::14 64896 # Per bank write bursts +system.physmem.perBankWrBursts::8 65578 # Per bank write bursts +system.physmem.perBankWrBursts::9 66028 # Per bank write bursts +system.physmem.perBankWrBursts::10 65644 # Per bank write bursts +system.physmem.perBankWrBursts::11 65946 # Per bank write bursts +system.physmem.perBankWrBursts::12 64498 # Per bank write bursts +system.physmem.perBankWrBursts::13 64533 # Per bank write bursts +system.physmem.perBankWrBursts::14 64901 # Per bank write bursts system.physmem.perBankWrBursts::15 64449 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1208800695000 # Total gap between requests +system.physmem.totGap 1208728583000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -96,9 +96,9 @@ system.physmem.writePktSize::2 0 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1022141 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1830062 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 122257 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1022134 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1829960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122331 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -193,31 +193,31 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1831783 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.923052 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.128953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.461416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1453465 79.35% 79.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 261783 14.29% 93.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48685 2.66% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20654 1.13% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13128 0.72% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7168 0.39% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5621 0.31% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4509 0.25% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16770 0.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1831783 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59616 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.746846 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 147.774131 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 59455 99.73% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 113 0.19% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 11 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1831742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.922688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.125561 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.468112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1453729 79.36% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 261245 14.26% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48901 2.67% 96.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20697 1.13% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13090 0.71% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7260 0.40% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5482 0.30% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4525 0.25% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16813 0.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1831742 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59619 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.744729 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 150.866534 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 59458 99.73% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 115 0.19% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 8 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 9 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 3 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-3583 3 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 3 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes @@ -225,103 +225,104 @@ system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # R system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10752-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59616 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59616 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.145079 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.109083 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.114634 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27440 46.03% 46.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1214 2.04% 48.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26474 44.41% 92.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3953 6.63% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 450 0.75% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 71 0.12% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 11 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59616 # Writes before turning the bus around for reads -system.physmem.totQLat 36544132750 # Total ticks spent queuing -system.physmem.totMemAccLat 73150432750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9761680000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18718.16 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::15360-15871 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 59619 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59619 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.144098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.107874 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.119193 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27514 46.15% 46.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1196 2.01% 48.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26405 44.29% 92.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3955 6.63% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 448 0.75% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 78 0.13% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59619 # Writes before turning the bus around for reads +system.physmem.totQLat 36502723500 # Total ticks spent queuing +system.physmem.totMemAccLat 73108498500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9761540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18697.22 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37468.16 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 37447.22 # Average memory access latency per DRAM burst system.physmem.avgRdBW 103.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 54.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 103.43 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 103.44 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 54.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing -system.physmem.readRowHits 723493 # Number of row buffer hits during reads -system.physmem.writeRowHits 419177 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.01 # Row buffer hit rate for writes -system.physmem.avgGap 406217.15 # Average gap between requests +system.physmem.avgWrQLen 24.64 # Average write queue length when enqueuing +system.physmem.readRowHits 723641 # Number of row buffer hits during reads +system.physmem.writeRowHits 419030 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.00 # Row buffer hit rate for writes +system.physmem.avgGap 406193.88 # Average gap between requests system.physmem.pageHitRate 38.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6716750040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3664893375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7353886800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3243486240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 78952922880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 415155955455 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 361108109250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 876196004040 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.847786 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 597970225000 # Time in different power states -system.physmem_0.memoryStateTime::REF 40364480000 # Time in different power states +system.physmem_0.actEnergy 6715147320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3664018875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7353699600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3243479760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 78947837280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 414818688735 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361357239750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 876100111320 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.815145 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 598389652500 # Time in different power states +system.physmem_0.memoryStateTime::REF 40361880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 570465308750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 569973346500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7131529440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3891211500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7874240400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3379857840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 78952922880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 426545221500 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 351117525000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 878892508560 # Total energy per rank (pJ) -system.physmem_1.averagePower 727.078515 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 581276348750 # Time in different power states -system.physmem_1.memoryStateTime::REF 40364480000 # Time in different power states +system.physmem_1.actEnergy 7132791960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3891900375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7873632000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3379818960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 78947837280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 426678504030 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 350953893000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 878858377605 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.097114 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 581002634000 # Time in different power states +system.physmem_1.memoryStateTime::REF 40361880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 587159309750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 587357637250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 246104681 # Number of BP lookups -system.cpu.branchPred.condPredicted 186361047 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15590665 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 167674402 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165200232 # Number of BTB hits +system.cpu.branchPred.lookups 246098302 # Number of BP lookups +system.cpu.branchPred.condPredicted 186353272 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15586995 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167674122 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165197435 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.524420 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18413418 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104179 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.522916 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18413853 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104375 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452862393 # DTB read hits -system.cpu.dtb.read_misses 4979628 # DTB read misses +system.cpu.dtb.read_hits 452860961 # DTB read hits +system.cpu.dtb.read_misses 4979889 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457842021 # DTB read accesses -system.cpu.dtb.write_hits 161378642 # DTB write hits -system.cpu.dtb.write_misses 1709394 # DTB write misses +system.cpu.dtb.read_accesses 457840850 # DTB read accesses +system.cpu.dtb.write_hits 161378751 # DTB write hits +system.cpu.dtb.write_misses 1709377 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163088036 # DTB write accesses -system.cpu.dtb.data_hits 614241035 # DTB hits -system.cpu.dtb.data_misses 6689022 # DTB misses +system.cpu.dtb.write_accesses 163088128 # DTB write accesses +system.cpu.dtb.data_hits 614239712 # DTB hits +system.cpu.dtb.data_misses 6689266 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620930057 # DTB accesses -system.cpu.itb.fetch_hits 597998986 # ITB hits +system.cpu.dtb.data_accesses 620928978 # DTB accesses +system.cpu.itb.fetch_hits 597989879 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 597999005 # ITB accesses +system.cpu.itb.fetch_accesses 597989898 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -335,82 +336,82 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2417601595 # number of cpu cycles simulated +system.cpu.numCycles 2417457399 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 51825441 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 51810559 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.323713 # CPI: cycles per instruction -system.cpu.ipc 0.755451 # IPC: instructions per cycle -system.cpu.tickCycles 2075284528 # Number of cycles that the object actually ticked -system.cpu.idleCycles 342317067 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9121986 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.726688 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601540360 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126082 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.914415 # Average number of references to valid blocks. +system.cpu.cpi 1.323634 # CPI: cycles per instruction +system.cpu.ipc 0.755496 # IPC: instructions per cycle +system.cpu.tickCycles 2075240271 # Number of cycles that the object actually ticked +system.cpu.idleCycles 342217128 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9121937 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.725777 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601539424 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126033 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.914667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 16821281500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.726688 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.725777 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.996271 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1562 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2407 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1547 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2403 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231278878 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231278878 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 443058336 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443058336 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158482024 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158482024 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 601540360 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601540360 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 601540360 # number of overall hits -system.cpu.dcache.overall_hits::total 601540360 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7289560 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289560 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2246478 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2246478 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9536038 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9536038 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9536038 # number of overall misses -system.cpu.dcache.overall_misses::total 9536038 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 185462944500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 185462944500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108451503000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108451503000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 293914447500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 293914447500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 293914447500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 293914447500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 450347896 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450347896 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231276891 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231276891 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 443057425 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443057425 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158481999 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158481999 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 601539424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601539424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 601539424 # number of overall hits +system.cpu.dcache.overall_hits::total 601539424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7289502 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289502 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2246503 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2246503 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9536005 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9536005 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9536005 # number of overall misses +system.cpu.dcache.overall_misses::total 9536005 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 185435901500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 185435901500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108411798000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108411798000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 293847699500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 293847699500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 293847699500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 293847699500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 450346927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450346927 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 611076398 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611076398 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 611076398 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611076398 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016187 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 611075429 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611075429 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 611075429 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611075429 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016186 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016186 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013977 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013977 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.015605 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015605 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015605 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015605 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25442.268738 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25442.268738 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48276.236402 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48276.236402 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30821.442563 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30821.442563 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30821.442563 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30821.442563 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25438.761317 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25438.761317 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48258.025028 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48258.025028 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30814.549646 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30814.549646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30814.549646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30814.549646 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,32 +420,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3686591 # number of writebacks -system.cpu.dcache.writebacks::total 3686591 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50801 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50801 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359155 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 359155 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 409956 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 409956 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 409956 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 409956 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238759 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238759 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887323 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126082 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126082 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126082 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126082 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176998396500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 176998396500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83275965000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83275965000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260274361500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 260274361500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260274361500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 260274361500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3686592 # number of writebacks +system.cpu.dcache.writebacks::total 3686592 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50797 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50797 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359175 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 359175 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 409972 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 409972 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 409972 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 409972 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238705 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238705 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887328 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887328 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126033 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126033 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126033 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126033 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176973816500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 176973816500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83260117500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83260117500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260233934000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 260233934000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260233934000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 260233934000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016074 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016074 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses @@ -453,66 +454,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014934 system.cpu.dcache.demand_mshr_miss_rate::total 0.014934 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014934 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014934 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24451.483535 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24451.483535 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44123.854263 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44123.854263 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.835949 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.835949 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.835949 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.835949 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24448.270305 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24448.270305 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44115.340577 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44115.340577 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28515.559170 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28515.559170 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28515.559170 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28515.559170 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 749.172343 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 597998029 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 749.290154 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 597988922 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 957 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 624867.323929 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 624857.807732 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 749.172343 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.365807 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.365807 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 749.290154 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.365864 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.365864 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 873 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1195998929 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1195998929 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 597998029 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 597998029 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 597998029 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 597998029 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 597998029 # number of overall hits -system.cpu.icache.overall_hits::total 597998029 # number of overall hits +system.cpu.icache.tags.tag_accesses 1195980715 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1195980715 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 597988922 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 597988922 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 597988922 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 597988922 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 597988922 # number of overall hits +system.cpu.icache.overall_hits::total 597988922 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses system.cpu.icache.overall_misses::total 957 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 77181000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 77181000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 77181000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 77181000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 77181000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 77181000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 597998986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 597998986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 597998986 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 597998986 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 597998986 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 597998986 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 76621000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 76621000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 76621000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 76621000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 76621000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 76621000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 597989879 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 597989879 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 597989879 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 597989879 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 597989879 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 597989879 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80648.902821 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80648.902821 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80648.902821 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80648.902821 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80648.902821 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80648.902821 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80063.740857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80063.740857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80063.740857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80063.740857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80063.740857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80063.740857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -521,125 +522,131 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 3 # number of writebacks +system.cpu.icache.writebacks::total 3 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 957 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 957 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 957 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 957 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76224000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 76224000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76224000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 76224000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76224000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 76224000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75664000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75664000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75664000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75664000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75664000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75664000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79648.902821 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79648.902821 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79648.902821 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79648.902821 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79648.902821 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79648.902821 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79063.740857 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79063.740857 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79063.740857 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79063.740857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79063.740857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79063.740857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1920882 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30765.249465 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14409739 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1950686 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.387011 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1920885 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30765.167230 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14409636 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1950689 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.386947 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 89219766000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14798.314674 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.741446 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15924.193345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.451609 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001304 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.485968 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.938881 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14798.522218 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.781155 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15923.863857 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.451615 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001306 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.485958 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.938878 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29804 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1217 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12865 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15534 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1218 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12864 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15532 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214047 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214046 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78088.262576 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78088.262576 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68146.812957 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68146.812957 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77372.490061 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77372.490061 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68146.812957 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77658.597897 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77653.938429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68146.812957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77658.597897 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.938429 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214047 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78065.940944 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78065.940944 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67562.695925 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67562.695925 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77352.158824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77352.158824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67562.695925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77637.469964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77632.534709 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67562.695925 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77637.469964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77632.534709 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 18249028 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121989 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 18248930 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121940 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1267 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1267 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1268 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7239716 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4708732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6334139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239662 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4708726 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6334096 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887328 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887328 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 957 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238759 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238705 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1917 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374150 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27376067 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820011072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820072320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1920882 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20169910 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000063 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.007925 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374003 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27375920 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820008000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820069440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1920885 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11047875 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000115 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010713 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 20168643 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1267 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11046607 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1268 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20169910 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12811105000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11047875 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12811060000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1435500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13689123000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13689049500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1173097 # Transaction distribution -system.membus.trans_dist::Writeback 1022141 # Transaction distribution -system.membus.trans_dist::CleanEvict 897719 # Transaction distribution -system.membus.trans_dist::ReadExReq 780512 # Transaction distribution -system.membus.trans_dist::ReadExResp 780512 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1173097 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827078 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5827078 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190448000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190448000 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1173100 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1022134 # Transaction distribution +system.membus.trans_dist::CleanEvict 897725 # Transaction distribution +system.membus.trans_dist::ReadExReq 780509 # Transaction distribution +system.membus.trans_dist::ReadExResp 780509 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1173100 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827077 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5827077 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190447552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190447552 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3873469 # Request fanout histogram +system.membus.snoop_fanout::samples 3873468 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3873469 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3873468 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3873469 # Request fanout histogram -system.membus.reqLayer0.occupancy 8428000500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3873468 # Request fanout histogram +system.membus.reqLayer0.occupancy 8428126500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 10685481750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10685578000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index bb4922b1c..5a6b26759 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.669557 # Number of seconds simulated -sim_ticks 669556582000 # Number of ticks simulated -final_tick 669556582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.669525 # Number of seconds simulated +sim_ticks 669525393000 # Number of ticks simulated +final_tick 669525393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160543 # Simulator instruction rate (inst/s) -host_op_rate 160543 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61918292 # Simulator tick rate (ticks/s) -host_mem_usage 299292 # Number of bytes of host memory used -host_seconds 10813.55 # Real time elapsed on the host +host_inst_rate 166227 # Simulator instruction rate (inst/s) +host_op_rate 166227 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64107392 # Simulator tick rate (ticks/s) +host_mem_usage 299384 # Number of bytes of host memory used +host_seconds 10443.81 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125490304 # Number of bytes read from this memory -system.physmem.bytes_read::total 125551168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60864 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65555584 # Number of bytes written to this memory -system.physmem.bytes_written::total 65555584 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 951 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960786 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961737 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1024306 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1024306 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 90902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 187423001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 187513903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90902 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90902 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 97908953 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 97908953 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 97908953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 187423001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 285422856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961737 # Number of read requests accepted -system.physmem.writeReqs 1024306 # Number of write requests accepted -system.physmem.readBursts 1961737 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1024306 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125467392 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83776 # Total number of bytes read from write queue -system.physmem.bytesWritten 65553984 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125551168 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65555584 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1309 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 60992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125490432 # Number of bytes read from this memory +system.physmem.bytes_read::total 125551424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65555904 # Number of bytes written to this memory +system.physmem.bytes_written::total 65555904 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 953 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960788 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961741 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1024311 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1024311 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 91097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 187431923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 187523021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97913992 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97913992 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97913992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 187431923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 285437013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961741 # Number of read requests accepted +system.physmem.writeReqs 1024311 # Number of write requests accepted +system.physmem.readBursts 1961741 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1024311 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125468352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83072 # Total number of bytes read from write queue +system.physmem.bytesWritten 65554688 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125551424 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65555904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1298 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118679 # Per bank write bursts -system.physmem.perBankRdBursts::1 113901 # Per bank write bursts -system.physmem.perBankRdBursts::2 116111 # Per bank write bursts -system.physmem.perBankRdBursts::3 117641 # Per bank write bursts -system.physmem.perBankRdBursts::4 117753 # Per bank write bursts -system.physmem.perBankRdBursts::5 117515 # Per bank write bursts -system.physmem.perBankRdBursts::6 119854 # Per bank write bursts -system.physmem.perBankRdBursts::7 124644 # Per bank write bursts -system.physmem.perBankRdBursts::8 127345 # Per bank write bursts -system.physmem.perBankRdBursts::9 130108 # Per bank write bursts -system.physmem.perBankRdBursts::10 128796 # Per bank write bursts -system.physmem.perBankRdBursts::11 130507 # Per bank write bursts -system.physmem.perBankRdBursts::12 126297 # Per bank write bursts -system.physmem.perBankRdBursts::13 125432 # Per bank write bursts -system.physmem.perBankRdBursts::14 122623 # Per bank write bursts -system.physmem.perBankRdBursts::15 123222 # Per bank write bursts -system.physmem.perBankWrBursts::0 61508 # Per bank write bursts -system.physmem.perBankWrBursts::1 61766 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 903686 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 118677 # Per bank write bursts +system.physmem.perBankRdBursts::1 113900 # Per bank write bursts +system.physmem.perBankRdBursts::2 116118 # Per bank write bursts +system.physmem.perBankRdBursts::3 117645 # Per bank write bursts +system.physmem.perBankRdBursts::4 117762 # Per bank write bursts +system.physmem.perBankRdBursts::5 117513 # Per bank write bursts +system.physmem.perBankRdBursts::6 119856 # Per bank write bursts +system.physmem.perBankRdBursts::7 124646 # Per bank write bursts +system.physmem.perBankRdBursts::8 127338 # Per bank write bursts +system.physmem.perBankRdBursts::9 130111 # Per bank write bursts +system.physmem.perBankRdBursts::10 128791 # Per bank write bursts +system.physmem.perBankRdBursts::11 130502 # Per bank write bursts +system.physmem.perBankRdBursts::12 126296 # Per bank write bursts +system.physmem.perBankRdBursts::13 125424 # Per bank write bursts +system.physmem.perBankRdBursts::14 122633 # Per bank write bursts +system.physmem.perBankRdBursts::15 123231 # Per bank write bursts +system.physmem.perBankWrBursts::0 61509 # Per bank write bursts +system.physmem.perBankWrBursts::1 61765 # Per bank write bursts system.physmem.perBankWrBursts::2 60825 # Per bank write bursts -system.physmem.perBankWrBursts::3 61511 # Per bank write bursts -system.physmem.perBankWrBursts::4 61967 # Per bank write bursts -system.physmem.perBankWrBursts::5 63434 # Per bank write bursts +system.physmem.perBankWrBursts::3 61513 # Per bank write bursts +system.physmem.perBankWrBursts::4 61969 # Per bank write bursts +system.physmem.perBankWrBursts::5 63433 # Per bank write bursts system.physmem.perBankWrBursts::6 64481 # Per bank write bursts -system.physmem.perBankWrBursts::7 65996 # Per bank write bursts +system.physmem.perBankWrBursts::7 65997 # Per bank write bursts system.physmem.perBankWrBursts::8 65770 # Per bank write bursts -system.physmem.perBankWrBursts::9 66159 # Per bank write bursts +system.physmem.perBankWrBursts::9 66158 # Per bank write bursts system.physmem.perBankWrBursts::10 65809 # Per bank write bursts -system.physmem.perBankWrBursts::11 66083 # Per bank write bursts -system.physmem.perBankWrBursts::12 64701 # Per bank write bursts -system.physmem.perBankWrBursts::13 64659 # Per bank write bursts -system.physmem.perBankWrBursts::14 65023 # Per bank write bursts -system.physmem.perBankWrBursts::15 64589 # Per bank write bursts +system.physmem.perBankWrBursts::11 66082 # Per bank write bursts +system.physmem.perBankWrBursts::12 64703 # Per bank write bursts +system.physmem.perBankWrBursts::13 64664 # Per bank write bursts +system.physmem.perBankWrBursts::14 65021 # Per bank write bursts +system.physmem.perBankWrBursts::15 64593 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 669556486500 # Total gap between requests +system.physmem.totGap 669525297500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961737 # Read request sizes (log2) +system.physmem.readPktSize::6 1961741 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1024306 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1618471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 241016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1024311 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1618506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 241044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 26356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 61428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 63649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 65159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 63632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 65011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,149 +193,148 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1769592 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.945804 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.951779 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 137.536097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1374979 77.70% 77.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 270914 15.31% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53662 3.03% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21295 1.20% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12785 0.72% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6489 0.37% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4949 0.28% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3948 0.22% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20571 1.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1769592 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60107 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.574625 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 148.683386 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 59945 99.73% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 118 0.20% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 6 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 5 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 3 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 1 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4607 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1769975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.923423 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.935475 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 137.553027 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1375598 77.72% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 270762 15.30% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53515 3.02% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21283 1.20% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12968 0.73% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6460 0.36% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4828 0.27% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3885 0.22% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20676 1.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1769975 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60095 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.621932 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 151.728866 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 59931 99.73% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 120 0.20% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 12 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 4 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 5 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 5 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 4 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-5119 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-8703 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-9727 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60107 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60107 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.040960 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.998792 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.235687 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 31915 53.10% 53.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1364 2.27% 55.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 21027 34.98% 90.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4732 7.87% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 816 1.36% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 161 0.27% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 44 0.07% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 14 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60095 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60095 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.044546 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.002519 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.231700 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 31758 52.85% 52.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1379 2.29% 55.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 21272 35.40% 90.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4591 7.64% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 816 1.36% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 185 0.31% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 43 0.07% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 20 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::34 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::35 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::37 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60107 # Writes before turning the bus around for reads -system.physmem.totQLat 40555708000 # Total ticks spent queuing -system.physmem.totMemAccLat 77313733000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9802140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20687.17 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::41 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60095 # Writes before turning the bus around for reads +system.physmem.totQLat 40550197000 # Total ticks spent queuing +system.physmem.totMemAccLat 77308503250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9802215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20684.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39437.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 187.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 39434.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 187.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 97.91 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 187.51 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 187.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 97.91 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.23 # Data bus utilization in percentage system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing -system.physmem.readRowHits 792895 # Number of row buffer hits during reads -system.physmem.writeRowHits 422217 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing +system.physmem.readRowHits 792754 # Number of row buffer hits during reads +system.physmem.writeRowHits 422001 # Number of row buffer hits during writes system.physmem.readRowHitRate 40.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.22 # Row buffer hit rate for writes -system.physmem.avgGap 224228.68 # Average gap between requests -system.physmem.pageHitRate 40.71 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6483387960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3537562875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7379541000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3249642240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 43732091520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 304280359155 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134820686250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 503483271000 # Total energy per rank (pJ) -system.physmem_0.averagePower 751.966482 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 222309059500 # Time in different power states -system.physmem_0.memoryStateTime::REF 22357920000 # Time in different power states +system.physmem.writeRowHitRate 41.20 # Row buffer hit rate for writes +system.physmem.avgGap 224217.56 # Average gap between requests +system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6484552200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3538198125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7379689200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3249668160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 43730057280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 304192019700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134879490000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 503453674665 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.957257 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 222404009750 # Time in different power states +system.physmem_0.memoryStateTime::REF 22356880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 424888778500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 424763715750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6894704880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3761991750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7911610200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3387698640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 43732091520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 311328000180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 128638545000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 505654642170 # Total energy per rank (pJ) -system.physmem_1.averagePower 755.209486 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 211980924500 # Time in different power states -system.physmem_1.memoryStateTime::REF 22357920000 # Time in different power states +system.physmem_1.actEnergy 6896443680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3762940500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7911594600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3387744000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 43730057280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 311181502770 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 128748364500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 505618647330 # Total energy per rank (pJ) +system.physmem_1.averagePower 755.190855 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 212167441250 # Time in different power states +system.physmem_1.memoryStateTime::REF 22356880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 435216639250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 435000017500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 409355418 # Number of BP lookups -system.cpu.branchPred.condPredicted 318166975 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15963047 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 282312141 # Number of BTB lookups -system.cpu.branchPred.BTBHits 278580615 # Number of BTB hits +system.cpu.branchPred.lookups 409350195 # Number of BP lookups +system.cpu.branchPred.condPredicted 318164532 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15963584 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 282308187 # Number of BTB lookups +system.cpu.branchPred.BTBHits 278578841 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.678227 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26172204 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.678981 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26172152 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 644928587 # DTB read hits -system.cpu.dtb.read_misses 12158902 # DTB read misses +system.cpu.dtb.read_hits 644938332 # DTB read hits +system.cpu.dtb.read_misses 12159455 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 657087489 # DTB read accesses -system.cpu.dtb.write_hits 218092717 # DTB write hits -system.cpu.dtb.write_misses 7512154 # DTB write misses +system.cpu.dtb.read_accesses 657097787 # DTB read accesses +system.cpu.dtb.write_hits 218091822 # DTB write hits +system.cpu.dtb.write_misses 7511788 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225604871 # DTB write accesses -system.cpu.dtb.data_hits 863021304 # DTB hits -system.cpu.dtb.data_misses 19671056 # DTB misses +system.cpu.dtb.write_accesses 225603610 # DTB write accesses +system.cpu.dtb.data_hits 863030154 # DTB hits +system.cpu.dtb.data_misses 19671243 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 882692360 # DTB accesses -system.cpu.itb.fetch_hits 420625120 # ITB hits +system.cpu.dtb.data_accesses 882701397 # DTB accesses +system.cpu.itb.fetch_hits 420624983 # ITB hits system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 420625157 # ITB accesses +system.cpu.itb.fetch_accesses 420625020 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -349,98 +348,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1339113165 # number of cpu cycles simulated +system.cpu.numCycles 1339050787 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 431760554 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3410003764 # Number of instructions fetch has processed -system.cpu.fetch.Branches 409355418 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 304752819 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 884588278 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45380492 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 431760433 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3409990757 # Number of instructions fetch has processed +system.cpu.fetch.Branches 409350195 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 304750993 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 884524854 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45382362 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1660 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 420625120 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8288982 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1339040790 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.546602 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.150665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 420624983 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8290664 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1338978167 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.546711 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.150697 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 714026661 53.32% 53.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47659433 3.56% 56.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24224234 1.81% 58.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45105968 3.37% 62.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142792146 10.66% 72.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 65943853 4.92% 77.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43594254 3.26% 80.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29429342 2.20% 83.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226264899 16.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 713970324 53.32% 53.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47658259 3.56% 56.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24222568 1.81% 58.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45103345 3.37% 62.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142790906 10.66% 72.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 65943786 4.92% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43594409 3.26% 80.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29428241 2.20% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226266329 16.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1339040790 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305691 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.546464 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 353769612 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 403558275 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 524215531 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34807834 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22689538 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62027781 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 752 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3256129377 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2069 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22689538 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 372008249 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 212535269 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7646 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 537155328 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 194644760 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3173788478 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1809495 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20462310 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 148566154 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30882701 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2371842618 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4117718959 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4117582524 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 136434 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1338978167 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305702 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.546573 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 353776569 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 403484138 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 524228681 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34798314 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22690465 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62024721 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3256106209 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2093 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22690465 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 372012141 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 212467548 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7342 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 537162613 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 194638058 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3173768927 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1816422 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20455726 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 148599653 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30860374 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2371827952 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4117690277 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4117553850 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 136426 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 995639655 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 143 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 142 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99637264 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 717251547 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272457871 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90453848 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58428187 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2884203449 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2620051581 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1544935 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1148159789 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 502731368 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1339040790 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.956663 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.148213 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 995624989 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 146 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 145 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99592668 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 717246268 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272455740 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90411000 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58626283 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2884178650 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 125 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2620049271 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1544769 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1148134993 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 502709027 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 96 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1338978167 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.956753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.148253 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 535540081 39.99% 39.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169652118 12.67% 52.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 157969981 11.80% 64.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149186997 11.14% 75.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125999252 9.41% 85.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84166081 6.29% 91.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68019052 5.08% 96.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34101039 2.55% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14406189 1.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 535496202 39.99% 39.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169647302 12.67% 52.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 157966093 11.80% 64.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149142376 11.14% 75.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126023638 9.41% 85.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84181895 6.29% 91.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68010869 5.08% 96.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34104922 2.55% 98.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14404870 1.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1339040790 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1338978167 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13157777 35.84% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13158801 35.84% 35.84% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 35.84% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 35.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.84% # attempts to use FU when none available @@ -469,17 +468,17 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.84% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18965028 51.65% 87.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4592425 12.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18966749 51.66% 87.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4591786 12.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1716938805 65.53% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1716928227 65.53% 65.53% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.53% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896154 0.03% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896664 0.03% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 163 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued @@ -503,84 +502,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 671533572 25.63% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230682699 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 671542182 25.63% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230681845 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2620051581 # Type of FU issued -system.cpu.iq.rate 1.956557 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36715230 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014013 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6615464746 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4031257680 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2518620612 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1939371 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1248863 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 886699 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2655799836 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 966975 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69396280 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2620049271 # Type of FU issued +system.cpu.iq.rate 1.956647 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36717336 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014014 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6615397697 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4031207578 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2518612422 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1941117 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1249905 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 887144 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2655798760 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 967847 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69398293 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 272655884 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 373351 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 145486 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 111729369 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 272650605 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 374228 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 146038 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 111727238 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 229 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6306976 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 239 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6310160 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22689538 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149806110 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 21267531 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3035207367 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6595956 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 717251547 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272457871 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 801675 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 20722786 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 145486 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10633585 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8701131 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19334716 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2574896999 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 657087498 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45154582 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22690465 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149836338 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 21229362 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3035183152 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6595413 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 717246268 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272455740 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 125 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 801803 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 20684202 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 146038 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10633994 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8701055 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19335049 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2574897906 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 657097795 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45151365 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151003796 # number of nop insts executed -system.cpu.iew.exec_refs 882692437 # number of memory reference insts executed -system.cpu.iew.exec_branches 315488895 # Number of branches executed -system.cpu.iew.exec_stores 225604939 # Number of stores executed -system.cpu.iew.exec_rate 1.922837 # Inst execution rate -system.cpu.iew.wb_sent 2549331117 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2519507311 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1487495376 # num instructions producing a value -system.cpu.iew.wb_consumers 1918378348 # num instructions consuming a value +system.cpu.iew.exec_nop 151004377 # number of nop insts executed +system.cpu.iew.exec_refs 882701473 # number of memory reference insts executed +system.cpu.iew.exec_branches 315482828 # Number of branches executed +system.cpu.iew.exec_stores 225603678 # Number of stores executed +system.cpu.iew.exec_rate 1.922928 # Inst execution rate +system.cpu.iew.wb_sent 2549323154 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2519499566 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1487497634 # num instructions producing a value +system.cpu.iew.wb_consumers 1918379503 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.881475 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775392 # average fanout of values written-back +system.cpu.iew.wb_rate 1.881556 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775393 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 998666714 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 998640819 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15962339 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1201055691 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.515150 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.548433 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15962868 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1200994355 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.515228 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.548533 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 712334289 59.31% 59.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159635442 13.29% 72.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79514551 6.62% 79.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52029279 4.33% 83.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28475742 2.37% 85.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19476450 1.62% 87.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19964545 1.66% 89.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23047887 1.92% 91.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106577506 8.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 712309125 59.31% 59.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159609736 13.29% 72.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79494019 6.62% 79.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52028691 4.33% 83.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28473987 2.37% 85.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19488340 1.62% 87.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19957354 1.66% 89.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23050317 1.92% 91.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106582786 8.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1201055691 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1200994355 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -626,138 +625,138 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106577506 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3827145825 # The number of ROB reads -system.cpu.rob.rob_writes 5775013033 # The number of ROB writes -system.cpu.timesIdled 710 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 72375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 106582786 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3827053314 # The number of ROB reads +system.cpu.rob.rob_writes 5774960362 # The number of ROB writes +system.cpu.timesIdled 711 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 72620 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.771359 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.771359 # CPI: Total CPI of All Threads -system.cpu.ipc 1.296413 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.296413 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3463596666 # number of integer regfile reads -system.cpu.int_regfile_writes 2019349968 # number of integer regfile writes -system.cpu.fp_regfile_reads 39643 # number of floating regfile reads +system.cpu.cpi 0.771323 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.771323 # CPI: Total CPI of All Threads +system.cpu.ipc 1.296473 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.296473 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3463595596 # number of integer regfile reads +system.cpu.int_regfile_writes 2019348323 # number of integer regfile writes +system.cpu.fp_regfile_reads 39740 # number of floating regfile reads system.cpu.fp_regfile_writes 588 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9207223 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.441459 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 712346742 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9211319 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.333848 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 9207181 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.441061 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 712353360 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9211277 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.334919 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5127954500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.441459 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997911 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997911 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.441061 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997910 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997910 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 707 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2960 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 698 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2969 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1470153653 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1470153653 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 556848599 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 556848599 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155498140 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155498140 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1470163219 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1470163219 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 556855010 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 556855010 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155498347 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155498347 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 712346739 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 712346739 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 712346739 # number of overall hits -system.cpu.dcache.overall_hits::total 712346739 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12894062 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12894062 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5230362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5230362 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 712353357 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 712353357 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 712353357 # number of overall hits +system.cpu.dcache.overall_hits::total 712353357 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12892455 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12892455 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5230155 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5230155 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 18124424 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 18124424 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 18124424 # number of overall misses -system.cpu.dcache.overall_misses::total 18124424 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 412011773000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 412011773000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 315105865697 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 315105865697 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 18122610 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 18122610 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 18122610 # number of overall misses +system.cpu.dcache.overall_misses::total 18122610 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 411787652500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 411787652500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 315044398573 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 315044398573 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 72500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 727117638697 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 727117638697 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 727117638697 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 727117638697 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 569742661 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 569742661 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 726832051073 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 726832051073 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 726832051073 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 726832051073 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 569747465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 569747465 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 730471163 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 730471163 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 730471163 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 730471163 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022631 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022631 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032542 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032542 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 730475967 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 730475967 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 730475967 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 730475967 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022628 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022628 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032540 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032540 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024812 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024812 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024812 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024812 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31953.605698 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31953.605698 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60245.517556 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60245.517556 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.024809 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024809 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024809 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024809 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31940.204755 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31940.204755 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60236.149516 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60236.149516 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40118.110164 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40118.110164 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40118.110164 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40118.110164 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15661523 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9569226 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1103711 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 68026 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.189877 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 140.670126 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40106.367188 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40106.367188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40106.367188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40106.367188 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15689743 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9578184 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1104687 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 68028 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.202886 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 140.797672 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3727748 # number of writebacks -system.cpu.dcache.writebacks::total 3727748 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5561934 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5561934 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3351172 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3351172 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8913106 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8913106 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8913106 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8913106 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332128 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7332128 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879190 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879190 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3727717 # number of writebacks +system.cpu.dcache.writebacks::total 3727717 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5560371 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5560371 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3350963 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3350963 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8911334 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8911334 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8911334 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8911334 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332084 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7332084 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879192 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879192 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9211318 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9211318 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9211318 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9211318 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182959853500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 182959853500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84331903655 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84331903655 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9211276 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9211276 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9211276 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9211276 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182956640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 182956640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84332021587 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84332021587 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 71500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 71500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267291757155 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 267291757155 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267291757155 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 267291757155 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267288661587 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 267288661587 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267288661587 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 267288661587 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012869 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012869 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011692 # mshr miss rate for WriteReq accesses @@ -768,201 +767,208 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012610 system.cpu.dcache.demand_mshr_miss_rate::total 0.012610 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012610 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24953.172326 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24953.172326 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44876.730748 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44876.730748 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24952.883791 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24952.883791 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44876.745743 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44876.745743 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 71500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 71500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.753719 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.753719 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.753719 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.753719 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.549967 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.549967 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.549967 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.549967 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 755.106219 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 420623640 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 951 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 442296.151420 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 755.122971 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 420623501 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 953 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 441367.786988 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 755.106219 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.368704 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.368704 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 950 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 755.122971 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.368712 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.368712 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 952 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 886 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.463867 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 841251191 # Number of tag accesses -system.cpu.icache.tags.data_accesses 841251191 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 420623640 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 420623640 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 420623640 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 420623640 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 420623640 # number of overall hits -system.cpu.icache.overall_hits::total 420623640 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1480 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1480 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1480 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1480 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1480 # number of overall misses -system.cpu.icache.overall_misses::total 1480 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 114807500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 114807500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 114807500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 114807500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 114807500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 114807500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 420625120 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 420625120 # 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number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 113433000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 420624983 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 420624983 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 420624983 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 420624983 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 420624983 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 420624983 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77572.635135 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77572.635135 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77572.635135 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77572.635135 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77572.635135 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77572.635135 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 288 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76540.485830 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76540.485830 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76540.485830 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76540.485830 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76540.485830 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76540.485830 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 290 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 529 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 529 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 529 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 529 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 529 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 951 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 951 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 951 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 156296539000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1024311 # number of writebacks +system.cpu.l2cache.writebacks::total 1024311 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 240 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 772417 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 772417 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 953 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 953 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1188371 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1188371 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 953 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1960788 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961741 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 953 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1960788 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1961741 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61607524500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61607524500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68203500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68203500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 94615740500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 94615740500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68203500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156223265000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 156291468500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68203500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156223265000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 156291468500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411033 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411033 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162077 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162077 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162079 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162079 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212867 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.212948 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212868 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.212950 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212867 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.212948 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79760.492403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79760.492403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72271.293375 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72271.293375 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79621.269891 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79621.269891 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72271.293375 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79676.114069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79672.524401 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72271.293375 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79676.114069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79672.524401 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212868 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.212950 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79759.410396 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79759.410396 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71567.156348 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71567.156348 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79618.015334 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79618.015334 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71567.156348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79673.715363 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.777254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71567.156348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79673.715363 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.777254 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 18419494 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207224 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 18419412 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207182 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1279 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1280 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7333064 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4752054 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6384201 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 951 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332113 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629861 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27631764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828100288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 828161152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1929031 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20348525 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000063 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.007928 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 7333022 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4752028 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6384190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332069 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1907 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629735 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27631642 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828095616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 828156672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1929037 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11141267 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000115 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010718 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 20347246 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1279 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11139987 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1280 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20348525 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12937495000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11141267 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12937424000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1426500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1429500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13816978500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13816915500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1189321 # Transaction distribution -system.membus.trans_dist::Writeback 1024306 # Transaction distribution -system.membus.trans_dist::CleanEvict 903687 # Transaction distribution -system.membus.trans_dist::ReadExReq 772416 # Transaction distribution -system.membus.trans_dist::ReadExResp 772416 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1189321 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851467 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5851467 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191106752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191106752 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1189324 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1024311 # Transaction distribution +system.membus.trans_dist::CleanEvict 903686 # Transaction distribution +system.membus.trans_dist::ReadExReq 772417 # Transaction distribution +system.membus.trans_dist::ReadExResp 772417 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1189324 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851479 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5851479 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191107328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191107328 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3889730 # Request fanout histogram +system.membus.snoop_fanout::samples 3889738 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3889730 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3889738 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3889730 # Request fanout histogram -system.membus.reqLayer0.occupancy 8475633500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3889738 # Request fanout histogram +system.membus.reqLayer0.occupancy 8475624000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 10684578250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10684646000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index d971ffdfc..2fb4a6971 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.623057 # Number of seconds simulated -sim_ticks 2623057163500 # Number of ticks simulated -final_tick 2623057163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.636720 # Number of seconds simulated +sim_ticks 2636719559500 # Number of ticks simulated +final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1405944 # Simulator instruction rate (inst/s) -host_op_rate 1405944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2026548224 # Simulator tick rate (ticks/s) -host_mem_usage 297224 # Number of bytes of host memory used -host_seconds 1294.35 # Real time elapsed on the host +host_inst_rate 1488641 # Simulator instruction rate (inst/s) +host_op_rate 1488641 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2156924734 # Simulator tick rate (ticks/s) +host_mem_usage 297352 # Number of bytes of host memory used +host_seconds 1222.44 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 1951440 # Nu system.physmem.num_reads::total 1952242 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1021962 # Number of write requests responded to by this memory system.physmem.num_writes::total 1021962 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19568 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47613206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47632774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19568 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19568 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24934862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24934862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24934862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47613206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72567635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 19467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47366494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47385960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 24805660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24805660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24805660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5246114327 # number of cpu cycles simulated +system.cpu.numCycles 5273439119 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -89,7 +89,7 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5246114327 # Number of busy cycles +system.cpu.num_busy_cycles 5273439119 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched @@ -129,19 +129,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction system.cpu.dcache.tags.replacements 9107638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4079.260769 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 40977438500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4079.260769 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995913 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995913 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 41036287500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.293901 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995921 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995921 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1197 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses @@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143001525000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143001525000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57421337000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57421337000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200422862000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200422862000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200422862000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200422862000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151181633000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151181633000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62898029000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62898029000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 214079662000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 214079662000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 214079662000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 214079662000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19799.685396 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19799.685396 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30392.594690 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30392.594690 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21996.127411 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21996.127411 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21996.127411 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21996.127411 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20932.285660 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20932.285660 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33291.358266 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33291.358266 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23494.942017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23494.942017 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135779111000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 135779111000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55532017000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 55532017000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191311128000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191311128000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191311128000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191311128000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143959219000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 143959219000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61008709000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61008709000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204967928000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 204967928000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204967928000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 204967928000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -228,26 +228,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18799.685396 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18799.685396 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29392.594690 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29392.594690 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20996.127411 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20996.127411 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20996.127411 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20996.127411 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19932.285660 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19932.285660 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32291.358266 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32291.358266 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 612.447387 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 612.447387 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.299047 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.299047 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 612.605858 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.299124 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.299124 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses @@ -264,12 +265,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44163500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44163500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44163500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44163500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44163500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44163500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49759500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49759500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49759500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49759500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49759500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49759500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -282,12 +283,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.708229 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55066.708229 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.708229 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55066.708229 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.708229 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55066.708229 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62044.264339 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62044.264339 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62044.264339 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62044.264339 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -296,55 +297,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43361500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43361500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43361500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43361500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43361500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43361500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 48957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 48957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48957500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 48957500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54066.708229 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54066.708229 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54066.708229 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54066.708229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54066.708229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54066.708229 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61044.264339 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61044.264339 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1919524 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30534.757407 # Cycle average of tags in use +system.cpu.l2cache.tags.replacements 1919525 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1949316 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.377078 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 218167130000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15101.273798 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.972607 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15394.511002 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.460854 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001189 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.469803 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.931847 # Average percentage of cache occupancy +system.cpu.l2cache.tags.sampled_refs 1949317 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.377074 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 218471945000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15091.675189 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.824340 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15410.326183 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.460561 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001185 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.470286 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.932032 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1062 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27300 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1058 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27302 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149600036 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149600036 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 3679426 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3679426 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 149600037 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149600037 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3679426 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3679426 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1106935 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1106935 # number of ReadExReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6053359 # number of ReadSharedReq hits @@ -365,20 +370,22 @@ system.cpu.l2cache.demand_misses::total 1952242 # nu system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1951440 # number of overall misses system.cpu.l2cache.overall_misses::total 1952242 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41075219500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41075219500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 42150500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 42150500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61385220500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 61385220500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 42150500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 102460440000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 102502590500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42150500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 102460440000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 102502590500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 3679426 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3679426 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46551911500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46551911500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47746500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 47746500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69565328500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 69565328500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 47746500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 116117240000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 116164986500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 47746500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 116117240000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 116164986500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3679426 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3679426 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) @@ -403,18 +410,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.214237 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214168 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214237 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.008947 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.008947 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52556.733167 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52556.733167 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52508.411067 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52508.411067 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52556.733167 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52505.042430 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52505.063665 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52556.733167 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52505.042430 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52505.063665 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.005113 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.005113 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59534.289277 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59534.289277 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.607948 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.607948 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59534.289277 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59503.361620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59503.374326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59534.289277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59503.361620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59503.374326 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -425,8 +432,8 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1021962 # number of writebacks system.cpu.l2cache.writebacks::total 1021962 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 243 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 243 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782385 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 782385 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 802 # number of ReadCleanReq MSHR misses @@ -439,18 +446,18 @@ system.cpu.l2cache.demand_mshr_misses::total 1952242 system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1951440 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1952242 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33251369500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33251369500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34130500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34130500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49694670500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49694670500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34130500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82946040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 82980170500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34130500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82946040000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 82980170500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38728061500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38728061500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39726500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39726500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57874778500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57874778500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39726500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96602840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 96642566500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39726500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96602840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 96642566500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414109 # mshr miss rate for ReadExReq accesses @@ -465,18 +472,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214237 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214237 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.008947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.008947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42556.733167 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42556.733167 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42508.411067 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42508.411067 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42556.733167 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42556.733167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.005113 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.005113 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49534.289277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49534.289277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.607948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.607948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -485,7 +492,8 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4701388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution @@ -494,29 +502,29 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222414 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1605 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818685568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919524 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20139699 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000056 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.007464 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 818685632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919525 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11032061 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000102 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010084 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 20138577 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11030939 99.99% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20139699 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12789513500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11032061 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12789514500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) system.membus.trans_dist::ReadResp 1169857 # Transaction distribution -system.membus.trans_dist::Writeback 1021962 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution system.membus.trans_dist::CleanEvict 896683 # Transaction distribution system.membus.trans_dist::ReadExReq 782385 # Transaction distribution system.membus.trans_dist::ReadExResp 782385 # Transaction distribution @@ -526,19 +534,19 @@ system.membus.pkt_count::total 5823129 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3872712 # Request fanout histogram +system.membus.snoop_fanout::samples 3870887 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3872712 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3870887 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3872712 # Request fanout histogram -system.membus.reqLayer0.occupancy 7960873524 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3870887 # Request fanout histogram +system.membus.reqLayer0.occupancy 7958742500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9761522024 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9761210000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 766f60b6c..144dc4013 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.116866 # Number of seconds simulated -sim_ticks 1116865669500 # Number of ticks simulated -final_tick 1116865669500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.116861 # Number of seconds simulated +sim_ticks 1116860578500 # Number of ticks simulated +final_tick 1116860578500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226280 # Simulator instruction rate (inst/s) -host_op_rate 243783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 163622006 # Simulator tick rate (ticks/s) -host_mem_usage 317884 # Number of bytes of host memory used -host_seconds 6825.89 # Real time elapsed on the host +host_inst_rate 237615 # Simulator instruction rate (inst/s) +host_op_rate 255994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171817202 # Simulator tick rate (ticks/s) +host_mem_usage 317996 # Number of bytes of host memory used +host_seconds 6500.28 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130931456 # Number of bytes read from this memory -system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 50176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory +system.physmem.bytes_read::total 130981888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50176 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2045804 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2045808 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2046592 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 45098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117231158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45098 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45098 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 45098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117231158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2046591 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 44926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117231922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117276848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 44926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 44926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60175704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60175704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60175704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 44926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117231922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177452552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2046592 # Number of read requests accepted system.physmem.writeReqs 1050123 # Number of write requests accepted -system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 2046592 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 130897024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 84800 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 130898112 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83776 # Total number of bytes read from write queue system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side +system.physmem.bytesReadSys 130981888 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1325 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 1309 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127282 # Per bank write bursts -system.physmem.perBankRdBursts::1 124660 # Per bank write bursts -system.physmem.perBankRdBursts::2 121599 # Per bank write bursts -system.physmem.perBankRdBursts::3 123658 # Per bank write bursts -system.physmem.perBankRdBursts::4 122616 # Per bank write bursts -system.physmem.perBankRdBursts::5 122675 # Per bank write bursts -system.physmem.perBankRdBursts::6 123246 # Per bank write bursts -system.physmem.perBankRdBursts::7 123764 # Per bank write bursts -system.physmem.perBankRdBursts::8 131397 # Per bank write bursts -system.physmem.perBankRdBursts::9 133514 # Per bank write bursts -system.physmem.perBankRdBursts::10 132084 # Per bank write bursts -system.physmem.perBankRdBursts::11 133304 # Per bank write bursts -system.physmem.perBankRdBursts::12 133248 # Per bank write bursts -system.physmem.perBankRdBursts::13 133365 # Per bank write bursts -system.physmem.perBankRdBursts::14 129309 # Per bank write bursts -system.physmem.perBankRdBursts::15 129545 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 962724 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 127279 # Per bank write bursts +system.physmem.perBankRdBursts::1 124661 # Per bank write bursts +system.physmem.perBankRdBursts::2 121601 # Per bank write bursts +system.physmem.perBankRdBursts::3 123659 # Per bank write bursts +system.physmem.perBankRdBursts::4 122620 # Per bank write bursts +system.physmem.perBankRdBursts::5 122678 # Per bank write bursts +system.physmem.perBankRdBursts::6 123247 # Per bank write bursts +system.physmem.perBankRdBursts::7 123768 # Per bank write bursts +system.physmem.perBankRdBursts::8 131395 # Per bank write bursts +system.physmem.perBankRdBursts::9 133511 # Per bank write bursts +system.physmem.perBankRdBursts::10 132082 # Per bank write bursts +system.physmem.perBankRdBursts::11 133309 # Per bank write bursts +system.physmem.perBankRdBursts::12 133249 # Per bank write bursts +system.physmem.perBankRdBursts::13 133361 # Per bank write bursts +system.physmem.perBankRdBursts::14 129308 # Per bank write bursts +system.physmem.perBankRdBursts::15 129555 # Per bank write bursts system.physmem.perBankWrBursts::0 66136 # Per bank write bursts system.physmem.perBankWrBursts::1 64410 # Per bank write bursts system.physmem.perBankWrBursts::2 62576 # Per bank write bursts @@ -71,25 +71,25 @@ system.physmem.perBankWrBursts::3 63006 # Pe system.physmem.perBankWrBursts::4 63000 # Per bank write bursts system.physmem.perBankWrBursts::5 63100 # Per bank write bursts system.physmem.perBankWrBursts::6 64443 # Per bank write bursts -system.physmem.perBankWrBursts::7 65436 # Per bank write bursts -system.physmem.perBankWrBursts::8 67310 # Per bank write bursts -system.physmem.perBankWrBursts::9 67797 # Per bank write bursts -system.physmem.perBankWrBursts::10 67549 # Per bank write bursts +system.physmem.perBankWrBursts::7 65435 # Per bank write bursts +system.physmem.perBankWrBursts::8 67311 # Per bank write bursts +system.physmem.perBankWrBursts::9 67795 # Per bank write bursts +system.physmem.perBankWrBursts::10 67548 # Per bank write bursts system.physmem.perBankWrBursts::11 67882 # Per bank write bursts -system.physmem.perBankWrBursts::12 67326 # Per bank write bursts +system.physmem.perBankWrBursts::12 67328 # Per bank write bursts system.physmem.perBankWrBursts::13 67793 # Per bank write bursts -system.physmem.perBankWrBursts::14 66482 # Per bank write bursts +system.physmem.perBankWrBursts::14 66483 # Per bank write bursts system.physmem.perBankWrBursts::15 65854 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1116865575000 # Total gap between requests +system.physmem.totGap 1116860484000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2046591 # Read request sizes (log2) +system.physmem.readPktSize::6 2046592 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,8 +97,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1050123 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1916631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1916633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128632 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 86 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see @@ -193,54 +193,53 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1910448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.693777 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.830782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.503425 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1485607 77.76% 77.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305343 15.98% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1910141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.711749 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.835384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.555895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1485377 77.76% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305179 15.98% 93.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 52494 2.75% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20883 1.09% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13429 0.70% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7609 0.40% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5497 0.29% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5095 0.27% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14491 0.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1910448 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61128 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.415767 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.633753 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61083 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 20 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::384-511 21040 1.10% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13364 0.70% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7561 0.40% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5492 0.29% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5154 0.27% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14480 0.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1910141 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61138 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.410579 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 159.595244 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61092 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 21 0.03% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61128 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61128 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.178707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.143614 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.099153 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 26983 44.14% 44.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1095 1.79% 45.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28688 46.93% 92.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3942 6.45% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 361 0.59% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 49 0.08% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 8 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61138 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61138 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.175897 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.140866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.098115 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27038 44.22% 44.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1118 1.83% 46.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28658 46.87% 92.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3907 6.39% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 362 0.59% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 47 0.08% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 6 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61128 # Writes before turning the bus around for reads -system.physmem.totQLat 38113681000 # Total ticks spent queuing -system.physmem.totMemAccLat 76462418500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10226330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18635.07 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 61138 # Writes before turning the bus around for reads +system.physmem.totQLat 38118822750 # Total ticks spent queuing +system.physmem.totMemAccLat 76467879000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10226415000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18637.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37385.07 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 37387.43 # Average memory access latency per DRAM burst system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s @@ -250,46 +249,46 @@ system.physmem.busUtil 1.39 # Da system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing -system.physmem.readRowHits 773150 # Number of row buffer hits during reads -system.physmem.writeRowHits 411758 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.80 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.21 # Row buffer hit rate for writes -system.physmem.avgGap 360661.52 # Average gap between requests -system.physmem.pageHitRate 38.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7040439000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3841509375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7717788000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ) +system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing +system.physmem.readRowHits 773327 # Number of row buffer hits during reads +system.physmem.writeRowHits 411912 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.23 # Row buffer hit rate for writes +system.physmem.avgGap 360659.76 # Average gap between requests +system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7038745560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3840585375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7718170200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3318446880 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 420410239110 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 301335056250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 816611331495 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.167175 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 498591665750 # Time in different power states +system.physmem_0.actBackEnergy 420695682570 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301084680000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 816644156985 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.196552 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 498171573500 # Time in different power states system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 580976292250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 581394006750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7402532760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4039080375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8234920200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 7401920400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4038746250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8234982600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3486201120 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 429557025690 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 293311559250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 818979159315 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.287251 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 485194866750 # Time in different power states +system.physmem_1.actBackEnergy 429157184085 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 293662305750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 818929186605 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.242498 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 485776924250 # Time in different power states system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 594372992750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 593789084750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 239639075 # Number of BP lookups -system.cpu.branchPred.condPredicted 186342287 # Number of conditional branches predicted +system.cpu.branchPred.lookups 239639085 # Number of BP lookups +system.cpu.branchPred.condPredicted 186342301 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14526140 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 130646101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122079387 # Number of BTB hits +system.cpu.branchPred.BTBLookups 130646105 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122079391 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 93.442809 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15657029 # Number of times the RAS was used to get a target. @@ -412,68 +411,68 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2233731339 # number of cpu cycles simulated +system.cpu.numCycles 2233721157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41470082 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41470128 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446190 # CPI: cycles per instruction -system.cpu.ipc 0.691472 # IPC: instructions per cycle -system.cpu.tickCycles 1834124286 # Number of cycles that the object actually ticked -system.cpu.idleCycles 399607053 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9221039 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.616235 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624218894 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9225135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.665015 # Average number of references to valid blocks. +system.cpu.cpi 1.446183 # CPI: cycles per instruction +system.cpu.ipc 0.691475 # IPC: instructions per cycle +system.cpu.tickCycles 1834122800 # Number of cycles that the object actually ticked +system.cpu.idleCycles 399598357 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9221041 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.616187 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624218895 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9225137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.665000 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616235 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616187 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 253 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 245 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276841917 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276841917 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453887722 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453887722 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331049 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331049 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276841907 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276841907 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453887715 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453887715 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331057 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331057 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624218771 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624218771 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624218772 # number of overall hits -system.cpu.dcache.overall_hits::total 624218772 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7334497 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7334497 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254998 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254998 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624218772 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624218772 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624218773 # number of overall hits +system.cpu.dcache.overall_hits::total 624218773 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7334498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7334498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254990 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254990 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9589495 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9589495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9589497 # number of overall misses -system.cpu.dcache.overall_misses::total 9589497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 190935436500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 190935436500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060065500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109060065500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 299995502000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 299995502000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 299995502000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 299995502000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461222219 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461222219 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9589488 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9589488 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9589490 # number of overall misses +system.cpu.dcache.overall_misses::total 9589490 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 190927662500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 190927662500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109073789000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109073789000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 300001451500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 300001451500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 300001451500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 300001451500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461222213 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461222213 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -482,10 +481,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633808266 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633808266 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633808269 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633808269 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 633808260 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633808260 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633808263 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633808263 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses @@ -496,14 +495,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26032.519544 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26032.519544 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48363.708305 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48363.708305 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31283.764369 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31283.764369 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31283.757845 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31283.757845 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.456072 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.456072 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48369.965720 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48369.965720 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31284.407624 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31284.407624 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31284.401100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31284.401100 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -512,36 +511,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3684564 # number of writebacks -system.cpu.dcache.writebacks::total 3684564 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3684566 # number of writebacks +system.cpu.dcache.writebacks::total 3684566 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364146 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364146 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364361 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364361 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364361 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364361 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334282 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7334282 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890852 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890852 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364137 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 364137 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364352 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364352 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364352 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364352 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334283 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7334283 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890853 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890853 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9225134 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9225134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9225135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9225135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183595384500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 183595384500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84757207500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84757207500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9225136 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9225136 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9225137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9225137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183587623500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 183587623500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84772423500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84772423500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268352592000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 268352592000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268352666000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 268352666000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268360047000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 268360047000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268360121000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 268360121000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -552,24 +551,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25032.495955 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25032.495955 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44824.876564 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44824.876564 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.434361 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.434361 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44832.900019 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44832.900019 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29089.289326 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29089.289326 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29089.294195 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29089.294195 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.091138 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.091138 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.096006 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.096006 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.385274 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 465281545 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 661.384835 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 465281420 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567416.518293 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567416.365854 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.385274 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 661.384835 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.322942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.322942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id @@ -577,44 +576,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 32 system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 930565550 # Number of tag accesses -system.cpu.icache.tags.data_accesses 930565550 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 465281545 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 465281545 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 465281545 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 465281545 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 465281545 # number of overall hits -system.cpu.icache.overall_hits::total 465281545 # number of overall hits +system.cpu.icache.tags.tag_accesses 930565300 # Number of tag accesses +system.cpu.icache.tags.data_accesses 930565300 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 465281420 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 465281420 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 465281420 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 465281420 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 465281420 # number of overall hits +system.cpu.icache.overall_hits::total 465281420 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses system.cpu.icache.overall_misses::total 820 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62174000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62174000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62174000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62174000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62174000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62174000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 465282365 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 465282365 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 465282365 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 465282365 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 465282365 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 465282365 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62291000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62291000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62291000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62291000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62291000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62291000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 465282240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 465282240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465282240 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465282240 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465282240 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465282240 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75821.951220 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75821.951220 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75821.951220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75821.951220 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75964.634146 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75964.634146 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75964.634146 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75964.634146 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75964.634146 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75964.634146 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -623,129 +622,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 29 # number of writebacks +system.cpu.icache.writebacks::total 29 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61354000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 61354000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61354000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 61354000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61354000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 61354000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61471000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 61471000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61471000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 61471000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61471000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61471000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74821.951220 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74821.951220 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74964.634146 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74964.634146 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74964.634146 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74964.634146 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74964.634146 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74964.634146 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2013890 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31258.297879 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14509190 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2043665 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.099593 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2013920 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31258.306174 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14509192 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.099490 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14832.420356 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588666 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.288857 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.452650 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000811 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.500467 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14832.753669 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.505297 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.047209 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.452660 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.500459 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.953928 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1251 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15557 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 151497949 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 151497949 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 3684564 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3684564 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1089697 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1089697 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 32 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 32 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7179327 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7179359 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7179327 # number of overall hits -system.cpu.l2cache.overall_hits::total 7179359 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 801155 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 801155 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87524.246114 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75833.121827 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87524.246114 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87915.750182 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87915.750182 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76231.847134 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76231.847134 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87284.057083 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87284.057083 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76231.847134 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87531.433973 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87527.099864 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76231.847134 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87531.433973 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87527.099864 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -766,120 +771,121 @@ system.cpu.l2cache.demand_mshr_hits::total 5 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158608712000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 158660583000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 784 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2045808 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2046592 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 784 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2045808 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2046592 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62422904500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62422904500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 51986500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 51986500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96191610000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96191610000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51986500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158614514500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158666501000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51986500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158614514500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158666501000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423701 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423701 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.959756 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956098 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956098 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169703 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169703 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956098 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956098 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77899.615555 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77899.615555 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65909.783990 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65909.783990 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77290.099859 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77290.099859 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77915.750182 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77915.750182 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66309.311224 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66309.311224 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77284.125886 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77284.125886 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66309.311224 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77531.476316 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77527.177376 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66309.311224 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77531.476316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77527.177376 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 18447023 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221080 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 18447027 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1287 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1281 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4734687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6498677 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890852 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890852 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7335104 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4734689 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6498678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 820 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334283 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1669 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27669715 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27671384 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 826273216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2013890 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20460913 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000220 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.014837 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27669721 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27671390 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 826275328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2013920 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11239877 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.016091 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 20456426 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4481 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11236984 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2887 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20460913 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12908075500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11239877 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12908108500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1230499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13837704496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13837707496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1245436 # Transaction distribution -system.membus.trans_dist::Writeback 1050123 # Transaction distribution -system.membus.trans_dist::CleanEvict 962723 # Transaction distribution -system.membus.trans_dist::ReadExReq 801155 # Transaction distribution -system.membus.trans_dist::ReadExResp 801155 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1245436 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106028 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6106028 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1245433 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution +system.membus.trans_dist::CleanEvict 962724 # Transaction distribution +system.membus.trans_dist::ReadExReq 801159 # Transaction distribution +system.membus.trans_dist::ReadExResp 801159 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1245433 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106031 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6106031 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198189760 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4059437 # Request fanout histogram +system.membus.snoop_fanout::samples 4059439 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4059437 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4059439 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4059437 # Request fanout histogram -system.membus.reqLayer0.occupancy 8662977500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4059439 # Request fanout histogram +system.membus.reqLayer0.occupancy 8663213500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11191643250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11191513500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 09d71d56d..41989d0e2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.770336 # Number of seconds simulated -sim_ticks 770336310500 # Number of ticks simulated -final_tick 770336310500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.767966 # Number of seconds simulated +sim_ticks 767965542000 # Number of ticks simulated +final_tick 767965542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130811 # Simulator instruction rate (inst/s) -host_op_rate 140929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65240720 # Simulator tick rate (ticks/s) -host_mem_usage 314688 # Number of bytes of host memory used -host_seconds 11807.60 # Real time elapsed on the host +host_inst_rate 135762 # Simulator instruction rate (inst/s) +host_op_rate 146263 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67501614 # Simulator tick rate (ticks/s) +host_mem_usage 354608 # Number of bytes of host memory used +host_seconds 11377.00 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 66496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 238054976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63977600 # Number of bytes read from this memory -system.physmem.bytes_read::total 302099072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 66496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 66496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104804160 # Number of bytes written to this memory -system.physmem.bytes_written::total 104804160 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1039 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3719609 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 999650 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4720298 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1637565 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1637565 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 86321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309027334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 83051518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 392165172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 86321 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86321 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136049877 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136049877 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136049877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 86321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309027334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 83051518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 528215049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4720298 # Number of read requests accepted -system.physmem.writeReqs 1637565 # Number of write requests accepted -system.physmem.readBursts 4720298 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1637565 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 301639360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 459712 # Total number of bytes read from write queue -system.physmem.bytesWritten 104801536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 302099072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104804160 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7183 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 296850 # Per bank write bursts -system.physmem.perBankRdBursts::1 294498 # Per bank write bursts -system.physmem.perBankRdBursts::2 288916 # Per bank write bursts -system.physmem.perBankRdBursts::3 292682 # Per bank write bursts -system.physmem.perBankRdBursts::4 290729 # Per bank write bursts -system.physmem.perBankRdBursts::5 289596 # Per bank write bursts -system.physmem.perBankRdBursts::6 284483 # Per bank write bursts -system.physmem.perBankRdBursts::7 281209 # Per bank write bursts -system.physmem.perBankRdBursts::8 297427 # Per bank write bursts -system.physmem.perBankRdBursts::9 303552 # Per bank write bursts -system.physmem.perBankRdBursts::10 295336 # Per bank write bursts -system.physmem.perBankRdBursts::11 302232 # Per bank write bursts -system.physmem.perBankRdBursts::12 303231 # Per bank write bursts -system.physmem.perBankRdBursts::13 302345 # Per bank write bursts -system.physmem.perBankRdBursts::14 297342 # Per bank write bursts -system.physmem.perBankRdBursts::15 292687 # Per bank write bursts -system.physmem.perBankWrBursts::0 104014 # Per bank write bursts -system.physmem.perBankWrBursts::1 101992 # Per bank write bursts -system.physmem.perBankWrBursts::2 99263 # Per bank write bursts -system.physmem.perBankWrBursts::3 99947 # Per bank write bursts -system.physmem.perBankWrBursts::4 99433 # Per bank write bursts -system.physmem.perBankWrBursts::5 98879 # Per bank write bursts -system.physmem.perBankWrBursts::6 102579 # Per bank write bursts -system.physmem.perBankWrBursts::7 104318 # Per bank write bursts -system.physmem.perBankWrBursts::8 105363 # Per bank write bursts -system.physmem.perBankWrBursts::9 104471 # Per bank write bursts -system.physmem.perBankWrBursts::10 102169 # Per bank write bursts -system.physmem.perBankWrBursts::11 102930 # Per bank write bursts -system.physmem.perBankWrBursts::12 102920 # Per bank write bursts -system.physmem.perBankWrBursts::13 102581 # Per bank write bursts -system.physmem.perBankWrBursts::14 104115 # Per bank write bursts -system.physmem.perBankWrBursts::15 102550 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 65024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 235466816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63671744 # Number of bytes read from this memory +system.physmem.bytes_read::total 299203584 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104705856 # Number of bytes written to this memory +system.physmem.bytes_written::total 104705856 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1016 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3679169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 994871 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4675056 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1636029 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1636029 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 84670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 306611173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82909637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 389605481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 84670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 84670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136341867 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136341867 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136341867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 84670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 306611173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82909637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 525947348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4675056 # Number of read requests accepted +system.physmem.writeReqs 1636029 # Number of write requests accepted +system.physmem.readBursts 4675056 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1636029 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 298722176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 481408 # Total number of bytes read from write queue +system.physmem.bytesWritten 104702912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299203584 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104705856 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7522 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 3003359 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 301326 # Per bank write bursts +system.physmem.perBankRdBursts::1 298715 # Per bank write bursts +system.physmem.perBankRdBursts::2 284983 # Per bank write bursts +system.physmem.perBankRdBursts::3 287209 # Per bank write bursts +system.physmem.perBankRdBursts::4 287920 # Per bank write bursts +system.physmem.perBankRdBursts::5 285373 # Per bank write bursts +system.physmem.perBankRdBursts::6 281637 # Per bank write bursts +system.physmem.perBankRdBursts::7 277868 # Per bank write bursts +system.physmem.perBankRdBursts::8 293986 # Per bank write bursts +system.physmem.perBankRdBursts::9 298704 # Per bank write bursts +system.physmem.perBankRdBursts::10 291815 # Per bank write bursts +system.physmem.perBankRdBursts::11 297314 # Per bank write bursts +system.physmem.perBankRdBursts::12 299397 # Per bank write bursts +system.physmem.perBankRdBursts::13 298122 # Per bank write bursts +system.physmem.perBankRdBursts::14 294010 # Per bank write bursts +system.physmem.perBankRdBursts::15 289155 # Per bank write bursts +system.physmem.perBankWrBursts::0 103823 # Per bank write bursts +system.physmem.perBankWrBursts::1 101759 # Per bank write bursts +system.physmem.perBankWrBursts::2 99255 # Per bank write bursts +system.physmem.perBankWrBursts::3 99822 # Per bank write bursts +system.physmem.perBankWrBursts::4 99277 # Per bank write bursts +system.physmem.perBankWrBursts::5 98671 # Per bank write bursts +system.physmem.perBankWrBursts::6 102768 # Per bank write bursts +system.physmem.perBankWrBursts::7 104279 # Per bank write bursts +system.physmem.perBankWrBursts::8 105369 # Per bank write bursts +system.physmem.perBankWrBursts::9 104220 # Per bank write bursts +system.physmem.perBankWrBursts::10 102032 # Per bank write bursts +system.physmem.perBankWrBursts::11 102651 # Per bank write bursts +system.physmem.perBankWrBursts::12 102828 # Per bank write bursts +system.physmem.perBankWrBursts::13 102619 # Per bank write bursts +system.physmem.perBankWrBursts::14 104194 # Per bank write bursts +system.physmem.perBankWrBursts::15 102416 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 770336158500 # Total gap between requests +system.physmem.totGap 767965500500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4720298 # Read request sizes (log2) +system.physmem.readPktSize::6 4675056 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1637565 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2783946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1045590 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 328353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 232144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 151285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 83614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 38578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1636029 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2763524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1029428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 325669 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 231653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 149305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 81525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18003 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 753 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 60100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 75642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 106708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 111119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 114322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 105421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 73176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 109521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 111161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 101092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,114 +197,123 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4289513 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.751761 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.903148 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 101.431882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3416049 79.64% 79.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 675171 15.74% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96645 2.25% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35451 0.83% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 23003 0.54% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12074 0.28% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6995 0.16% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5025 0.12% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19100 0.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4289513 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98662 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.769871 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 32.372187 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 98.540692 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 96215 97.52% 97.52% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1195 1.21% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 729 0.74% 99.47% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 403 0.41% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 87 0.09% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 4 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 4 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98662 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98662 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.597312 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.563431 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.103098 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 72815 73.80% 73.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1780 1.80% 75.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18354 18.60% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3927 3.98% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 986 1.00% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 404 0.41% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 201 0.20% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 116 0.12% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 44 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 22 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 12 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98662 # Writes before turning the bus around for reads -system.physmem.totQLat 131160021238 # Total ticks spent queuing -system.physmem.totMemAccLat 219530927488 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23565575000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27828.73 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 4246279 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 95.006264 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.933304 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.667614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3382951 79.67% 79.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 666013 15.68% 95.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94842 2.23% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35210 0.83% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22787 0.54% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12374 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7276 0.17% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5157 0.12% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19669 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4246279 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97783 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.733256 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.725873 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 93691 95.82% 95.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1680 1.72% 97.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-383 798 0.82% 98.35% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 374 0.38% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 374 0.38% 99.11% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 340 0.35% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 220 0.22% 99.69% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 159 0.16% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 76 0.08% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 37 0.04% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 11 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 7 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1663 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1664-1791 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2176-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2431 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3200-3327 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3712-3839 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3840-3967 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97783 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97783 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.730751 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.687620 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.251075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 68399 69.95% 69.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 2006 2.05% 72.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18369 18.79% 90.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5745 5.88% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1950 1.99% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 718 0.73% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 317 0.32% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 149 0.15% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 75 0.08% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 33 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 10 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97783 # Writes before turning the bus around for reads +system.physmem.totQLat 128413030932 # Total ticks spent queuing +system.physmem.totMemAccLat 215929293432 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23337670000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27511.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46578.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 391.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 136.05 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 392.17 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.05 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46261.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 388.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 136.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 389.61 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.12 # Data bus utilization in percentage -system.physmem.busUtilRead 3.06 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing -system.physmem.readRowHits 1707273 # Number of row buffer hits during reads -system.physmem.writeRowHits 353841 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.61 # Row buffer hit rate for writes -system.physmem.avgGap 121162.75 # Average gap between requests -system.physmem.pageHitRate 32.46 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16082924760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8775405375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18087474600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5251508640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50314383600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 409609386630 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 102893262750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 611014346355 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.182199 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 168633417027 # Time in different power states -system.physmem_0.memoryStateTime::REF 25723100000 # Time in different power states +system.physmem.busUtil 4.10 # Data bus utilization in percentage +system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.89 # Average write queue length when enqueuing +system.physmem.readRowHits 1709654 # Number of row buffer hits during reads +system.physmem.writeRowHits 347571 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.25 # Row buffer hit rate for writes +system.physmem.avgGap 121685.18 # Average gap between requests +system.physmem.pageHitRate 32.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15953799960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8704950375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 17977486800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5246246880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50159272800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 414403163865 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 97263315750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 609708236430 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.934243 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 159282861364 # Time in different power states +system.physmem_0.memoryStateTime::REF 25643800000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 575976400473 # Time in different power states +system.physmem_0.memoryStateTime::ACT 583033093643 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16345687680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8918778000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18674323200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5359543200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50314383600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 410844304170 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 101810001750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 612267021600 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.808347 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 166829398639 # Time in different power states -system.physmem_1.memoryStateTime::REF 25723100000 # Time in different power states +system.physmem_1.actEnergy 16147600560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8810694750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18427445400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5354300880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50159272800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 410341742010 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100825962000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 610067018400 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.401440 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165241048217 # Time in different power states +system.physmem_1.memoryStateTime::REF 25643800000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 577780670361 # Time in different power states +system.physmem_1.memoryStateTime::ACT 577073869783 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286278310 # Number of BP lookups -system.cpu.branchPred.condPredicted 223407435 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14630059 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158227088 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150348964 # Number of BTB hits +system.cpu.branchPred.lookups 286290965 # Number of BP lookups +system.cpu.branchPred.condPredicted 223414875 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14630075 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157650249 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150360830 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.021002 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16641238 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 95.376208 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16641594 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -424,128 +433,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1540672622 # number of cpu cycles simulated +system.cpu.numCycles 1535931085 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13926355 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067514794 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286278310 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166990202 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1512022873 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29284737 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 188 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1021 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656940964 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 966 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1540592805 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.437738 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13926236 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067547876 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286290965 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 167002424 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1507284638 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29284969 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 196 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 917 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656963855 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 927 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1535854471 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.442200 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228202 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 458181319 29.74% 29.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465421558 30.21% 59.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101422593 6.58% 66.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515567335 33.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 453416615 29.52% 29.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465436740 30.30% 59.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101431033 6.60% 66.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515570083 33.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1540592805 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185814 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.341956 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74646858 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 543216907 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849967493 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58119883 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14641664 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42201795 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 757 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037179352 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52470113 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14641664 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139717275 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 462450514 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13916 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837848883 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 85920553 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976355004 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26745374 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45156757 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125486 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1486003 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25049006 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985823032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128033727 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432836892 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 151 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1535854471 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.186396 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.346120 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74705927 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 538395080 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849912555 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58199125 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14641784 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42202960 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 740 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037254051 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52495885 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14641784 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139801946 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 457449218 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13751 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837842602 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86105170 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976447004 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26743472 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45311241 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126368 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1599527 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25035305 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985923292 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128451044 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432959840 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 125 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310924087 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 156 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 148 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111428528 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542554069 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199305704 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26941972 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29270810 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947933260 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 215 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857474146 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13497185 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283901059 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647116126 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1540592805 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.205688 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150881 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 311024347 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 154 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 145 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111506310 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542573483 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199309856 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26973622 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29535518 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1948030100 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 211 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857442950 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13480165 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283997895 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647563158 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1535854471 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.209387 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150580 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 587702275 38.15% 38.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325996808 21.16% 59.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378232244 24.55% 83.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219639231 14.26% 98.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29016078 1.88% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6169 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 582872858 37.95% 37.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326140941 21.24% 59.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378202799 24.62% 83.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219661262 14.30% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28970430 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6181 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1540592805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1535854471 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166081126 41.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1996 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191505284 47.27% 88.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47530605 11.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166043738 41.02% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1958 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191460391 47.30% 88.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47270881 11.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138242397 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801060 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138255914 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800916 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -567,90 +576,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 32 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 28 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532116023 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186314612 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532080715 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186305355 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857474146 # Type of FU issued -system.cpu.iq.rate 1.205625 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405119011 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218102 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5674157044 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231847189 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805703414 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 266 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262593018 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17811740 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857442950 # Type of FU issued +system.cpu.iq.rate 1.209327 # Inst issue rate +system.cpu.iq.fu_busy_cnt 404776968 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.217922 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5668997271 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2232041055 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805706922 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 233 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 216 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262219787 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 131 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17802666 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84247735 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66708 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13149 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24458659 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84267149 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66494 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13286 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24462811 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4504401 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4884981 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4478194 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4870766 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14641664 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25329983 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1325123 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947933556 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14641784 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25370881 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1332488 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1948030384 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542554069 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199305704 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 153 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159005 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1165002 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13149 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7699177 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8705456 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16404633 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827812064 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516937908 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29662082 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542573483 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199309856 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 149 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159276 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1171811 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13286 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7699902 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8704078 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16403980 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827785519 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516901938 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29657431 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 81 # number of nop insts executed -system.cpu.iew.exec_refs 698690935 # number of memory reference insts executed -system.cpu.iew.exec_branches 229542500 # Number of branches executed -system.cpu.iew.exec_stores 181753027 # Number of stores executed -system.cpu.iew.exec_rate 1.186373 # Inst execution rate -system.cpu.iew.wb_sent 1808734068 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805703486 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169239698 # num instructions producing a value -system.cpu.iew.wb_consumers 1689624086 # num instructions consuming a value +system.cpu.iew.exec_nop 73 # number of nop insts executed +system.cpu.iew.exec_refs 698651224 # number of memory reference insts executed +system.cpu.iew.exec_branches 229542579 # Number of branches executed +system.cpu.iew.exec_stores 181749286 # Number of stores executed +system.cpu.iew.exec_rate 1.190018 # Inst execution rate +system.cpu.iew.wb_sent 1808742163 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805706990 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169201528 # num instructions producing a value +system.cpu.iew.wb_consumers 1689618558 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.172023 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692012 # average fanout of values written-back +system.cpu.iew.wb_rate 1.175643 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.691991 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 258007667 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 258099025 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14629355 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1501111622 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.108533 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.025633 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14629375 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1496362804 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.112051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.027734 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 920819202 61.34% 61.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250634053 16.70% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110061016 7.33% 85.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55281373 3.68% 89.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29321487 1.95% 91.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34081425 2.27% 93.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24716781 1.65% 94.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18131809 1.21% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58064476 3.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 916038990 61.22% 61.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250656359 16.75% 77.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110050903 7.35% 85.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55261193 3.69% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29363802 1.96% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34102831 2.28% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24718362 1.65% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18151757 1.21% 96.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58018607 3.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1501111622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1496362804 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -696,76 +705,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58064476 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3365086648 # The number of ROB reads -system.cpu.rob.rob_writes 3883566462 # The number of ROB writes -system.cpu.timesIdled 859 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 79817 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58018607 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3360475057 # The number of ROB reads +system.cpu.rob.rob_writes 3883759706 # The number of ROB writes +system.cpu.timesIdled 836 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76614 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.997481 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.997481 # CPI: Total CPI of All Threads -system.cpu.ipc 1.002525 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.002525 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175803949 # number of integer regfile reads -system.cpu.int_regfile_writes 1261568723 # number of integer regfile writes +system.cpu.cpi 0.994411 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.994411 # CPI: Total CPI of All Threads +system.cpu.ipc 1.005620 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.005620 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175771978 # number of integer regfile reads +system.cpu.int_regfile_writes 1261585669 # number of integer regfile writes system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 54 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965710140 # number of cc regfile reads -system.cpu.cc_regfile_writes 551865181 # number of cc regfile writes -system.cpu.misc_regfile_reads 675846539 # number of misc regfile reads +system.cpu.fp_regfile_writes 50 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965626191 # number of cc regfile reads +system.cpu.cc_regfile_writes 551852831 # number of cc regfile writes +system.cpu.misc_regfile_reads 675841321 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17004606 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964973 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638063275 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17005118 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.521838 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 77839500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964973 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 17004065 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964813 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638072070 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17004577 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.523549 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 77932500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964813 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 420 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 416 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335698850 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335698850 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469343498 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469343498 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168719659 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168719659 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335720557 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335720557 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469353506 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469353506 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168718419 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168718419 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638063157 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638063157 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638063157 # number of overall hits -system.cpu.dcache.overall_hits::total 638063157 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17417197 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17417197 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3866388 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3866388 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638071925 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638071925 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638071925 # number of overall hits +system.cpu.dcache.overall_hits::total 638071925 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17418313 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17418313 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3867628 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3867628 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21283585 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21283585 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21283587 # number of overall misses -system.cpu.dcache.overall_misses::total 21283587 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 415522893500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 415522893500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149855935942 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149855935942 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 216000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 565378829442 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 565378829442 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 565378829442 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 565378829442 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486760695 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486760695 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21285941 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21285941 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21285943 # number of overall misses +system.cpu.dcache.overall_misses::total 21285943 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 412331077000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 412331077000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 148962559255 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 148962559255 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 561293636255 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 561293636255 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 561293636255 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 561293636255 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486771819 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486771819 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -774,440 +783,470 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659346742 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659346742 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659346744 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659346744 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035782 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035782 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022403 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022403 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659357866 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659357866 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659357868 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659357868 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022410 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022410 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032280 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032280 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032280 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032280 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23857.047348 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23857.047348 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38758.638797 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38758.638797 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26564.078817 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26564.078817 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26564.076320 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26564.076320 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20755892 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3446894 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 946527 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67143 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.928473 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51.336610 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.032283 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032283 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032283 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032283 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23672.273945 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23672.273945 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.224126 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.224126 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26369.218831 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26369.218831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26369.216353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26369.216353 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20544187 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3409553 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 942936 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67231 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.787467 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50.714001 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4835415 # number of writebacks -system.cpu.dcache.writebacks::total 4835415 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3149636 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3149636 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1128832 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1128832 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17004065 # number of writebacks +system.cpu.dcache.writebacks::total 17004065 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151291 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3151291 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130068 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1130068 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4278468 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4278468 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4278468 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4278468 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267561 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14267561 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737556 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737556 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4281359 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4281359 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4281359 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4281359 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267022 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14267022 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737560 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737560 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17005117 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17005117 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17005118 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17005118 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335383172000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 335383172000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116381847286 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116381847286 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17004582 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17004582 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17004583 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17004583 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331931922000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 331931922000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115721294597 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 115721294597 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451765019286 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 451765019286 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451765087286 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 451765087286 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029311 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447653216597 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 447653216597 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447653284597 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 447653284597 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029309 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025791 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23506.692700 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23506.692700 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42513.047144 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42513.047144 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025790 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025790 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025790 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025790 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23265.676747 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23265.676747 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42271.692528 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42271.692528 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26566.416408 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26566.416408 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26566.418844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26566.418844 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26325.446671 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26325.446671 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26325.449121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26325.449121 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 592 # number of replacements -system.cpu.icache.tags.tagsinuse 446.127099 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656939322 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1080 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 608277.150000 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 587 # number of replacements +system.cpu.icache.tags.tagsinuse 444.617750 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656962266 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1073 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 612266.790308 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 446.127099 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.871342 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.871342 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 444.617750 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.868394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.868394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313883006 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313883006 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656939322 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656939322 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656939322 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656939322 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656939322 # number of overall hits -system.cpu.icache.overall_hits::total 656939322 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1641 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1641 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1641 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1641 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1641 # number of overall misses -system.cpu.icache.overall_misses::total 1641 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 107375484 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 107375484 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 107375484 # 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Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1313928777 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313928777 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656962266 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656962266 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656962266 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656962266 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656962266 # number of overall hits +system.cpu.icache.overall_hits::total 656962266 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1586 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1586 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1586 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1586 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1586 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65432.957952 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65432.957952 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65432.957952 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 18112 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1654 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 192 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.333333 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 165.400000 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62352.135561 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62352.135561 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62352.135561 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62352.135561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62352.135561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62352.135561 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17132 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 145 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 194 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 88.309278 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76771987 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 76771987 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76771987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 76771987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76771987 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 76771987 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 587 # number of writebacks +system.cpu.icache.writebacks::total 587 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 511 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 511 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 511 # 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Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.459894 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.204385 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.984496 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 817 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 599 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 215 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 502 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2347 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1263 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1830 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.049866 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.922180 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 551302751 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 551302751 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 4835415 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 4835415 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1752988 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1752988 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 41 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11483491 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.359662 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.962037 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.962037 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.195130 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.195130 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962037 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.221618 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.221665 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962037 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.221618 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.221665 # 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mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962037 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.218695 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.218743 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962037 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.218695 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356711 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356711 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.946047 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189341 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189341 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216287 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216333 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216287 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.277660 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72781.087835 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95408.043397 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95408.043397 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66550.529355 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66550.529355 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79942.612843 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79942.612843 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66550.529355 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84020.103572 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84015.224275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66550.529355 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84020.103572 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81631.427256 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.283659 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63170.642694 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63170.642694 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16916.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16916.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95071.999541 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95071.999541 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64420.845624 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64420.845624 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79684.970805 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79684.970805 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64420.845624 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83770.483702 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83765.134633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64420.845624 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83770.483702 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63170.642694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78877.066841 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 34011398 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17005208 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21592 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 111772 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 111653 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 14268599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 6472980 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 15222988 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1281199 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1080 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267519 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2748 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993254 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50996002 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397794112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1397863232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 5993561 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 40004959 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.003877 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.062190 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 34010311 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004668 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21296 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2921208 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2902417 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18791 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 14268046 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6464245 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12155140 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5774511 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1435676 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266973 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2731 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50991946 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50994677 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 105984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2175190848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2175296832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 8846223 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 25851874 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.114549 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.320751 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 39849994 99.61% 99.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 154846 0.39% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 119 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22909361 88.62% 88.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2923722 11.31% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 18791 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 40004959 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 21841114998 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1620000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25851874 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34009808017 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 10525 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1610997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25507681990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25506872492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3739654 # Transaction distribution -system.membus.trans_dist::Writeback 1637565 # Transaction distribution -system.membus.trans_dist::CleanEvict 3065415 # Transaction distribution -system.membus.trans_dist::ReadExReq 980644 # Transaction distribution -system.membus.trans_dist::ReadExResp 980644 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3739654 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14143576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14143576 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406903232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 406903232 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3698381 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1636029 # Transaction distribution +system.membus.trans_dist::CleanEvict 3003353 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 976674 # Transaction distribution +system.membus.trans_dist::ReadExResp 976674 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3698382 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13989505 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13989505 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403909376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 403909376 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9423278 # Request fanout histogram +system.membus.snoop_fanout::samples 9314444 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9423278 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9314444 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9423278 # Request fanout histogram -system.membus.reqLayer0.occupancy 17318873513 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25673835894 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9314444 # Request fanout histogram +system.membus.reqLayer0.occupancy 17663480706 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 25423271236 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 3fad64f8d..02c08f292 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.363368 # Number of seconds simulated -sim_ticks 2363368369500 # Number of ticks simulated -final_tick 2363368369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.377030 # Number of seconds simulated +sim_ticks 2377029670500 # Number of ticks simulated +final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1008024 # Simulator instruction rate (inst/s) -host_op_rate 1086287 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1548215415 # Simulator tick rate (ticks/s) -host_mem_usage 315828 # Number of bytes of host memory used -host_seconds 1526.51 # Real time elapsed on the host +host_inst_rate 970948 # Simulator instruction rate (inst/s) +host_op_rate 1046333 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1499891883 # Simulator tick rate (ticks/s) +host_mem_usage 316204 # Number of bytes of host memory used +host_seconds 1584.80 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124870144 # Number of bytes read from this memory -system.physmem.bytes_read::total 124909568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory +system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951096 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1951712 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52835667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52852348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27652112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27652112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27652112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52835667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80504461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4726736739 # number of cpu cycles simulated +system.cpu.numCycles 4754059341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759602 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 633153380 # nu system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4726736738.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 213462427 # Number of branches fetched @@ -215,19 +215,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.732103 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164683500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732103 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses @@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143052931500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143052931500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57408921000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57408921000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200461852500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200461852500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200461852500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200461852500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.738027 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.738027 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.773464 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.773464 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.956598 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21991.956598 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.954185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21991.954185 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135826845500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 135826845500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55519772000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 55519772000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191346617500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191346617500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191346671500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191346671500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60994614000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 60994614000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 205003612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 205003673500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -334,26 +334,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.738027 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.738027 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.773464 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.773464 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.956598 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.956598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.960219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.960219 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.003151 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.003151 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.251466 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.251466 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id @@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34234000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34234000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34234000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34234000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34234000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34234000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38540000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38540000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38540000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38540000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38540000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38540000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses @@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53658.307210 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53658.307210 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53658.307210 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53658.307210 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60407.523511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,93 +405,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 7 # number of writebacks +system.cpu.icache.writebacks::total 7 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33596000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33596000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33596000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33596000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33596000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33596000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37902000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37902000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37902000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37902000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37902000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37902000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52658.307210 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52658.307210 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1919018 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31008.199290 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14386233 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1948786 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.382151 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 150067869000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15515.970631 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734659 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494001 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.473510 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000724 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.472061 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.946295 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1919027 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15485.424786 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.473115 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000722 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.472578 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.946414 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1084 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1732 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26839 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1085 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1728 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149644895 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149644895 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 3681379 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3681379 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1107017 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107017 # number of ReadExReq hits +system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1107015 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1107015 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6057123 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 6057123 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7164140 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7164162 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7164138 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7164160 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7164140 # number of overall hits -system.cpu.l2cache.overall_hits::total 7164162 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 782132 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 782132 # number of ReadExReq misses +system.cpu.l2cache.overall_hits::cpu.data 7164138 # number of overall hits +system.cpu.l2cache.overall_hits::total 7164160 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 782134 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 782134 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 616 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 616 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168964 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 1168964 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1951096 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1951712 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1951098 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1951714 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1951096 # number of overall misses -system.cpu.l2cache.overall_misses::total 1951712 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41062370000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41062370000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 32383000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 32383000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386933500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386933500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32383000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 102449303500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 102481686500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32383000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 102449303500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 102481686500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 3681379 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3681379 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1951098 # number of overall misses +system.cpu.l2cache.overall_misses::total 1951714 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46537233000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46537233000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 36689000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 36689000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69569093500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 69569093500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36689000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 116106326500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 116143015500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36689000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 116106326500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 116143015500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3681379 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3681379 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 638 # number of ReadCleanReq accesses(hits+misses) @@ -504,30 +510,30 @@ system.cpu.l2cache.demand_accesses::total 9115874 # n system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414013 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.414013 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414014 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.414014 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.965517 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161770 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161770 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.214048 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214100 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214101 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214048 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214100 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.562565 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.562565 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52569.805195 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52569.805195 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.964074 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.964074 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52508.611158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52508.611158 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.214101 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.332424 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.332424 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59560.064935 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59560.064935 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59513.461065 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59513.461065 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59508.214574 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,58 +544,58 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks system.cpu.l2cache.writebacks::total 1021127 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 226 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 226 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782132 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782132 # number of ReadExReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168964 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168964 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1951096 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1951712 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1951098 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1951714 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1951096 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1951712 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33241050000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33241050000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26223000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26223000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697293500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697293500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26223000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938343500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 82964566500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26223000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938343500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 82964566500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1951098 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1951714 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38715893000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38715893000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 30529000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 30529000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57879453500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57879453500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30529000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96595346500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 96625875500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30529000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96595346500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 96625875500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414013 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414013 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214100 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.562565 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.562565 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42569.805195 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42569.805195 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.964074 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.964074 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -598,8 +604,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4702506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6326508 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6326510 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution @@ -607,51 +614,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27340461 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27341744 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 819024192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919018 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20146039 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919027 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 20142667 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3372 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20146039 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12794889500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) system.membus.trans_dist::ReadResp 1169580 # Transaction distribution -system.membus.trans_dist::Writeback 1021127 # Transaction distribution -system.membus.trans_dist::CleanEvict 897054 # Transaction distribution -system.membus.trans_dist::ReadExReq 782132 # Transaction distribution -system.membus.trans_dist::ReadExResp 782132 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution +system.membus.trans_dist::CleanEvict 897056 # Transaction distribution +system.membus.trans_dist::ReadExReq 782134 # Transaction distribution +system.membus.trans_dist::ReadExResp 782134 # Transaction distribution system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5821605 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190261696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3870264 # Request fanout histogram +system.membus.snoop_fanout::samples 3869897 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3870264 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3870264 # Request fanout histogram -system.membus.reqLayer0.occupancy 7969342268 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3869897 # Request fanout histogram +system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9772290268 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index c34bcec93..d16f022eb 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.882285 # Number of seconds simulated -sim_ticks 5882284743500 # Number of ticks simulated -final_tick 5882284743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.895948 # Number of seconds simulated +sim_ticks 5895947852500 # Number of ticks simulated +final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 704974 # Simulator instruction rate (inst/s) -host_op_rate 1098413 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1378571885 # Simulator tick rate (ticks/s) -host_mem_usage 317252 # Number of bytes of host memory used -host_seconds 4266.94 # Real time elapsed on the host +host_inst_rate 730138 # Simulator instruction rate (inst/s) +host_op_rate 1137621 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1431096811 # Simulator tick rate (ticks/s) +host_mem_usage 317400 # Number of bytes of host memory used +host_seconds 4119.88 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124876416 # Number of bytes read from this memory -system.physmem.bytes_read::total 124919616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory +system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65426432 # Number of bytes written to this memory -system.physmem.bytes_written::total 65426432 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory +system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951194 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1951869 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1022288 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1022288 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 21229237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 21236581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11122622 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11122622 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11122622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 21229237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 32359203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 1951195 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1951870 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1022289 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1022289 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 21180052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 21187379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11764569487 # number of cpu cycles simulated +system.cpu.numCycles 11791895705 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed @@ -60,7 +60,7 @@ system.cpu.num_mem_refs 1677713084 # nu system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11764569486.998001 # Number of busy cycles +system.cpu.num_busy_cycles 11791895704.997999 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 248500691 # Number of branches fetched @@ -100,19 +100,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction system.cpu.dcache.tags.replacements 9108581 # number of replacements -system.cpu.dcache.tags.tagsinuse 4084.586459 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 58853917500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4084.586459 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997213 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997213 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses @@ -133,14 +133,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 142985038000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 142985038000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57429949000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57429949000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200414987000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200414987000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200414987000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200414987000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151166404000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151166404000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62906975000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62906975000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 214073379000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 214073379000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 214073379000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 214073379000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) @@ -157,14 +157,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.207591 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.207591 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.998041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.998041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21992.987022 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21992.987022 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21992.987022 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21992.987022 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20928.913656 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20928.913656 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33287.160677 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33287.160677 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23491.821229 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23491.821229 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,8 +173,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3682721 # number of writebacks -system.cpu.dcache.writebacks::total 3682721 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks +system.cpu.dcache.writebacks::total 3682716 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses @@ -183,14 +183,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135762188000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 135762188000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55540122000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 55540122000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191302310000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191302310000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191302310000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191302310000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143943554000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 143943554000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61017148000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61017148000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204960702000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 204960702000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204960702000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 204960702000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses @@ -199,24 +199,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.207591 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.207591 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.998041 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.998041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20992.987022 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20992.987022 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20992.987022 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20992.987022 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10 # number of replacements -system.cpu.icache.tags.tagsinuse 555.701425 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 555.701425 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.271339 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.271339 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id @@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37142500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37142500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37142500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37142500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37142500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37142500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41859500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41859500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41859500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41859500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41859500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41859500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses @@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55025.925926 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55025.925926 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55025.925926 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55025.925926 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55025.925926 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55025.925926 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62014.074074 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62014.074074 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62014.074074 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62014.074074 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -267,89 +267,95 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 10 # number of writebacks +system.cpu.icache.writebacks::total 10 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36467500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36467500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36467500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36467500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36467500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36467500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41184500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41184500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41184500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41184500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41184500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41184500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54025.925926 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54025.925926 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54025.925926 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54025.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54025.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54025.925926 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1919162 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31136.006197 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14382006 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1948945 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.379380 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 340768623000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15266.348436 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.605704 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15844.052057 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.465892 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000781 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.483522 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.950196 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1919169 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15850.035379 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.465750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000780 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.483705 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.950234 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 997 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 743 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27920 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149614316 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149614316 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 3682721 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3682721 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054089 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6054089 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7161483 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7161483 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7161483 # number of overall hits -system.cpu.l2cache.overall_hits::total 7161483 # number of overall hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054088 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6054088 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 7161482 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7161482 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7161482 # number of overall hits +system.cpu.l2cache.overall_hits::total 7161482 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 782433 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 782433 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168761 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1168761 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168762 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1168762 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1951194 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1951869 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1951195 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1951870 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1951194 # number of overall misses -system.cpu.l2cache.overall_misses::total 1951869 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41077744500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41077744500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 35453500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 35453500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61359978500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 61359978500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35453500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 102437723000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 102473176500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35453500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 102437723000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 102473176500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 3682721 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3682721 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1951195 # number of overall misses +system.cpu.l2cache.overall_misses::total 1951870 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46554770500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46554770500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40170500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 40170500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69541354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 69541354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 40170500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 116096124500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 116136295000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 40170500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 116096124500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 116136295000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3682716 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3682716 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses) @@ -366,26 +372,26 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161814 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161814 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161815 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161815 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.015337 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.015337 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52523.703704 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52523.703704 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.022246 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.022246 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52523.703704 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.019475 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.027666 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52523.703704 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.019475 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.027666 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.008946 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.008946 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.851852 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.851852 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.012834 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.012834 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.015370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.015370 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,60 +400,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1022288 # number of writebacks -system.cpu.l2cache.writebacks::total 1022288 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 218 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 218 # number of CleanEvict MSHR misses +system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks +system.cpu.l2cache.writebacks::total 1022289 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 212 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168761 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168761 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168762 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168762 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1951194 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1951869 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1951195 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1951870 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1951194 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1951869 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33253414500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33253414500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28703500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28703500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49672368500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49672368500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28703500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82925783000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 82954486500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28703500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82925783000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 82954486500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1951195 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1951870 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38730440500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38730440500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 33420500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 33420500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57853734000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57853734000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33420500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96584174500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 96617595000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33420500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96584174500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 96617595000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161814 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161814 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161815 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161815 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.015337 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.015337 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42523.703704 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42523.703704 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.022246 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.022246 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42523.703704 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42523.703704 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.008946 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.008946 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.851852 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.851852 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.012834 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.012834 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -456,8 +462,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4705009 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6322744 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution @@ -465,53 +472,53 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818948672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919162 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20141105 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000050 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.007053 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 818948992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919169 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11032521 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000091 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.009530 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 20140103 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1002 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11031519 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1002 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20141105 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12793692500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1169436 # Transaction distribution -system.membus.trans_dist::Writeback 1022288 # Transaction distribution +system.membus.trans_dist::ReadResp 1169437 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution system.membus.trans_dist::CleanEvict 896090 # Transaction distribution system.membus.trans_dist::ReadExReq 782433 # Transaction distribution system.membus.trans_dist::ReadExResp 782433 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1169436 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5822116 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190346048 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5822119 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190346176 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3870262 # Request fanout histogram +system.membus.snoop_fanout::samples 3870249 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3870262 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3870249 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3870262 # Request fanout histogram -system.membus.reqLayer0.occupancy 7959418124 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3870249 # Request fanout histogram +system.membus.reqLayer0.occupancy 7959407000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9759348624 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9759350000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |