diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
| commit | d2b57a7473768e8aff3707916b40b264cab6821c (patch) | |
| tree | f4e64db0a8bb23dd26a1c8f1ec5b887be346f625 /tests/long/se/60.bzip2/ref | |
| parent | 7c55464aac2bcab15699e563f18a7d3d565d949a (diff) | |
| download | gem5-d2b57a7473768e8aff3707916b40b264cab6821c.tar.xz | |
Stats: Update stats to reflect SimpleMemory bandwidth
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
Diffstat (limited to 'tests/long/se/60.bzip2/ref')
3 files changed, 1238 insertions, 1238 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index def42a9fe..0d873282b 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.996061 # Number of seconds simulated -sim_ticks 996061088500 # Number of ticks simulated -final_tick 996061088500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.996063 # Number of seconds simulated +sim_ticks 996062814500 # Number of ticks simulated +final_tick 996062814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139633 # Simulator instruction rate (inst/s) -host_op_rate 139633 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76428343 # Simulator tick rate (ticks/s) -host_mem_usage 218940 # Number of bytes of host memory used -host_seconds 13032.61 # Real time elapsed on the host +host_inst_rate 142352 # Simulator instruction rate (inst/s) +host_op_rate 142352 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 77916645 # Simulator tick rate (ticks/s) +host_mem_usage 219096 # Number of bytes of host memory used +host_seconds 12783.70 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -24,32 +24,32 @@ system.physmem.num_reads::total 2150541 # Nu system.physmem.num_writes::writebacks 1048516 # Number of write requests responded to by this memory system.physmem.num_writes::total 1048516 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 55193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 138123705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138178898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 138123466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138178659 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 55193 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 55193 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 67370390 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 67370390 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 67370390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 67370273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 67370273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 67370273 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 55193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 138123705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 205549288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 138123466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 205548932 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444620723 # DTB read hits +system.cpu.dtb.read_hits 444620890 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449517801 # DTB read accesses +system.cpu.dtb.read_accesses 449517968 # DTB read accesses system.cpu.dtb.write_hits 160920434 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 162621738 # DTB write accesses -system.cpu.dtb.data_hits 605541157 # DTB hits +system.cpu.dtb.data_hits 605541324 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612139539 # DTB accesses +system.cpu.dtb.data_accesses 612139706 # DTB accesses system.cpu.itb.fetch_hits 232151959 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1992122178 # number of cpu cycles simulated +system.cpu.numCycles 1992125630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 328832264 # Number of BP lookups @@ -80,9 +80,9 @@ system.cpu.branch_predictor.RASInCorrect 6 # Nu system.cpu.branch_predictor.BTBHitPct 59.382560 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 175107833 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 153724431 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669698374 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 1669698372 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3045900991 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 3045900989 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File @@ -93,16 +93,16 @@ system.cpu.execution_unit.predictedNotTakenIncorrect 12122106 system.cpu.execution_unit.mispredicted 133399918 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 81800180 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 61.988781 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139625101 # Number of Instructions Executed. +system.cpu.execution_unit.executions 1139625100 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1749883167 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1749884347 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7972682 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 415150633 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576971545 # Number of cycles cpu stages are processed. -system.cpu.activity 79.160383 # Percentage of cycles cpu is active +system.cpu.timesIdled 7972692 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 415154081 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576971549 # Number of cycles cpu stages are processed. +system.cpu.activity 79.160246 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -114,34 +114,34 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.094705 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.094707 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.094705 # CPI: Total CPI of All Threads -system.cpu.ipc 0.913488 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.094707 # CPI: Total CPI of All Threads +system.cpu.ipc 0.913487 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.913488 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 801357098 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190765080 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.773697 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1059714238 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932407940 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.804757 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1018188148 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.913487 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 801360547 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190765083 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.773594 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1059717687 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932407943 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.804676 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1018191600 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 973934030 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.889272 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1582467246 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 48.889187 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1582470698 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 409654932 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.563745 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 969329070 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022793108 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.341887 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 20.563710 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 969332524 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022793106 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.341797 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 666.783228 # Cycle average of tags in use +system.cpu.icache.tagsinuse 666.783134 # Cycle average of tags in use system.cpu.icache.total_refs 232150871 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 270257.125728 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 666.783228 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 666.783134 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.325578 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.325578 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 232150871 # number of ReadReq hits @@ -219,39 +219,39 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 55155.995343 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107309 # number of replacements -system.cpu.dcache.tagsinuse 4082.354199 # Cycle average of tags in use -system.cpu.dcache.total_refs 595073835 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111405 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310875 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9107311 # number of replacements +system.cpu.dcache.tagsinuse 4082.354222 # Cycle average of tags in use +system.cpu.dcache.total_refs 595073825 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111407 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.310860 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 12655884000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.354199 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4082.354222 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.996669 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271435 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271435 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157802400 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157802400 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595073835 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595073835 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595073835 # number of overall hits -system.cpu.dcache.overall_hits::total 595073835 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2926102 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2926102 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10250330 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10250330 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10250330 # number of overall misses -system.cpu.dcache.overall_misses::total 10250330 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 166496556500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 166496556500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 130053734500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 130053734500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 296550291000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 296550291000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 296550291000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 296550291000 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 437271433 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437271433 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 157802392 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157802392 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595073825 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 595073825 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 595073825 # number of overall hits +system.cpu.dcache.overall_hits::total 595073825 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7324230 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7324230 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2926110 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2926110 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 10250340 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10250340 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10250340 # number of overall misses +system.cpu.dcache.overall_misses::total 10250340 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 166497124500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 166497124500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 130098294500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 130098294500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 296595419000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 296595419000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 296595419000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 296595419000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -268,48 +268,48 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016934 system.cpu.dcache.demand_miss_rate::total 0.016934 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016934 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016934 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.301138 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.301138 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44446.070062 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44446.070062 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28930.804277 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28930.804277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28930.804277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28930.804277 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 76478500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8150814500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14619 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.372481 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.372481 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44461.176955 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44461.176955 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28935.178638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28935.178638 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 78626000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8150818500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14909 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 208452 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5231.445379 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 39101.637307 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5273.727279 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39101.656496 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3389633 # number of writebacks -system.cpu.dcache.writebacks::total 3389633 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3389635 # number of writebacks +system.cpu.dcache.writebacks::total 3389635 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101948 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 101948 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1036977 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1036977 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1138925 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1138925 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1138925 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1138925 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1036985 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1036985 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1138933 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1138933 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1138933 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1138933 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889125 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1889125 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111405 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111405 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111405 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111405 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 140938235500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 140938235500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71711487500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71711487500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212649723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212649723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212649723000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212649723000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9111407 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111407 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111407 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111407 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 140938792000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 140938792000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71755618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71755618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212694410500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 212694410500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212694410500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 212694410500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -318,38 +318,38 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19514.368800 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19514.368800 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37960.160127 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37960.160127 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23338.850924 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23338.850924 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23338.850924 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23338.850924 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19514.440450 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19514.440450 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37983.520678 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37983.520678 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2133758 # number of replacements -system.cpu.l2cache.tagsinuse 30551.127244 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8448350 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 30551.128505 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8448354 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2163449 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.905038 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 184402684000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14423.839124 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.322166 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16092.965953 # Average occupied blocks per requestor +system.cpu.l2cache.avg_refs 3.905040 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 184403463000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14423.846214 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 34.322158 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16092.960133 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.440181 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001047 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.491118 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.932346 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5860987 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5860987 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3389633 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3389633 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5860989 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5860989 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3389635 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3389635 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1100736 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1100736 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6961723 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6961723 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6961723 # number of overall hits -system.cpu.l2cache.overall_hits::total 6961723 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.data 6961725 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6961725 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6961725 # number of overall hits +system.cpu.l2cache.overall_hits::total 6961725 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 1360852 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 1361711 # number of ReadReq misses @@ -362,29 +362,29 @@ system.cpu.l2cache.overall_misses::cpu.inst 859 # system.cpu.l2cache.overall_misses::cpu.data 2149682 # number of overall misses system.cpu.l2cache.overall_misses::total 2150541 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46160000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71425674500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71471834500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41981087000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41981087000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71427566000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71473726000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42035467500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 42035467500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 46160000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 113406761500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 113452921500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 113463033500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 113509193500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 46160000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 113406761500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 113452921500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 113463033500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 113509193500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7221839 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222698 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3389633 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3389633 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221841 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222700 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3389635 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3389635 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889566 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889566 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111405 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112264 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111407 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112266 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111405 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112264 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111407 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112266 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188436 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.188532 # miss rate for ReadReq accesses @@ -397,21 +397,21 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_miss_rate::cpu.data 0.235933 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.236005 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53736.903376 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52485.997375 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52486.786477 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53219.435113 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53219.435113 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52487.387313 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52488.175538 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53288.373287 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53288.373287 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52755.133783 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52755.525935 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52781.310678 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52781.692374 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52755.133783 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52755.525935 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 3381000 # number of cycles access was blocked +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.310678 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52781.692374 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 3730000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 111 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 142 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 30459.459459 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 26267.605634 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -429,16 +429,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 system.cpu.l2cache.overall_mshr_misses::cpu.data 2149682 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2150541 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35698000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54780311000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54816009000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32410594000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32410594000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54782223000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54817921000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32465310500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32465310500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35698000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87190905000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 87226603000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87247533500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87283231500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35698000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87190905000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 87226603000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87247533500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87283231500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses @@ -451,16 +451,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235933 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.236005 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41557.625146 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40254.422230 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40255.244321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41086.918601 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41086.918601 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40255.827232 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40256.648437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41156.282723 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41156.282723 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40559.908396 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40560.306918 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40559.908396 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40560.306918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 24a60df2f..693f470b9 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.621255 # Number of seconds simulated -sim_ticks 621254733000 # Number of ticks simulated -final_tick 621254733000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.621337 # Number of seconds simulated +sim_ticks 621337354500 # Number of ticks simulated +final_tick 621337354500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 206958 # Simulator instruction rate (inst/s) -host_op_rate 206958 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74061263 # Simulator tick rate (ticks/s) -host_mem_usage 219968 # Number of bytes of host memory used -host_seconds 8388.39 # Real time elapsed on the host +host_inst_rate 185902 # Simulator instruction rate (inst/s) +host_op_rate 185902 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66535120 # Simulator tick rate (ticks/s) +host_mem_usage 220128 # Number of bytes of host memory used +host_seconds 9338.49 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138177216 # Number of bytes read from this memory -system.physmem.bytes_read::total 138239104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67208512 # Number of bytes written to this memory -system.physmem.bytes_written::total 67208512 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2159019 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2159986 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050133 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050133 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 99618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 222416359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 222515977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 99618 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 99618 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 108181891 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 108181891 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 108181891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 99618 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 222416359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 330697869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 62208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138182080 # Number of bytes read from this memory +system.physmem.bytes_read::total 138244288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 62208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 62208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67208384 # Number of bytes written to this memory +system.physmem.bytes_written::total 67208384 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 972 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2159095 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2160067 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050131 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050131 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 100120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 222394612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 222494732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 100120 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 100120 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 108167300 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 108167300 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 108167300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 100120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 222394612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 330662032 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 614267388 # DTB read hits -system.cpu.dtb.read_misses 10994218 # DTB read misses +system.cpu.dtb.read_hits 614254083 # DTB read hits +system.cpu.dtb.read_misses 10995703 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625261606 # DTB read accesses -system.cpu.dtb.write_hits 208720588 # DTB write hits -system.cpu.dtb.write_misses 6852950 # DTB write misses +system.cpu.dtb.read_accesses 625249786 # DTB read accesses +system.cpu.dtb.write_hits 208699163 # DTB write hits +system.cpu.dtb.write_misses 6860235 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 215573538 # DTB write accesses -system.cpu.dtb.data_hits 822987976 # DTB hits -system.cpu.dtb.data_misses 17847168 # DTB misses +system.cpu.dtb.write_accesses 215559398 # DTB write accesses +system.cpu.dtb.data_hits 822953246 # DTB hits +system.cpu.dtb.data_misses 17855938 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 840835144 # DTB accesses -system.cpu.itb.fetch_hits 402675877 # ITB hits -system.cpu.itb.fetch_misses 58 # ITB misses +system.cpu.dtb.data_accesses 840809184 # DTB accesses +system.cpu.itb.fetch_hits 402673269 # ITB hits +system.cpu.itb.fetch_misses 61 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 402675935 # ITB accesses +system.cpu.itb.fetch_accesses 402673330 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,145 +67,145 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1242509467 # number of cpu cycles simulated +system.cpu.numCycles 1242674710 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 383372990 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 295235565 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19006052 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 268408458 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 264104025 # Number of BTB hits +system.cpu.BPredUnit.lookups 383387811 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 295251517 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 19004234 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 268604084 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 264111879 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25197943 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6076 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 414160425 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3172269212 # Number of instructions fetch has processed -system.cpu.fetch.Branches 383372990 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 289301968 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 579083206 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 137694854 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 132940581 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1360 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 402675877 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10477889 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1238022002 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.562369 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.158541 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25192938 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6291 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 414146940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3172273422 # Number of instructions fetch has processed +system.cpu.fetch.Branches 383387811 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 289304817 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 579090604 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 137696439 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 133107618 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1380 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 402673269 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10484478 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1238186640 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.562032 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.158458 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 658938796 53.23% 53.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43587849 3.52% 56.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22400320 1.81% 58.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 41027424 3.31% 61.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 127967453 10.34% 72.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63937343 5.16% 77.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40820174 3.30% 80.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30420264 2.46% 83.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 208922379 16.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 659096036 53.23% 53.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43594264 3.52% 56.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22394894 1.81% 58.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 41029945 3.31% 61.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127979061 10.34% 72.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63938505 5.16% 77.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40814246 3.30% 80.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30412222 2.46% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 208927467 16.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1238022002 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.308547 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.553115 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 444879640 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 117490931 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 546452553 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17363359 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 111835519 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60534072 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 962 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3092225969 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2145 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 111835519 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 466447238 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 65379308 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5467 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 540801711 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53552759 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3009893694 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 588891 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2795172 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 47908313 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2251120190 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3888621958 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3887220740 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1401218 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1238186640 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.308518 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.552779 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 444874368 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 117661314 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 546409633 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17402131 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 111839194 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 60535765 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 960 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3092199728 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2107 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 111839194 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 466426212 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 65454708 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5539 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 540814331 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53646656 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3009948527 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 590628 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2809331 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 47992017 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2251177447 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3888711604 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3887318453 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1393151 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 874917227 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 215 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 214 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112891088 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679356489 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 252372715 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 62271668 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36485662 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2703868851 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 183 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2499086402 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3468008 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 959949757 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 407382923 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 154 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1238022002 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.018612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.960549 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 874974484 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 208 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 207 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112977902 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679363507 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 252361148 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 62396219 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36704407 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2703896552 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 180 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2499071963 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3469199 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 959964040 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 407445563 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 151 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1238186640 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.018332 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.960312 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 396920026 32.06% 32.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203237579 16.42% 48.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185771607 15.01% 63.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153281748 12.38% 75.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 136530779 11.03% 86.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79975547 6.46% 93.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 62882805 5.08% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14212604 1.15% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5209307 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 396950099 32.06% 32.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203265879 16.42% 48.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185984424 15.02% 63.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153264847 12.38% 75.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 136492690 11.02% 86.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79936535 6.46% 93.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 62863067 5.08% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14221934 1.15% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5207165 0.42% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1238022002 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1238186640 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1901972 10.18% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12247269 65.56% 75.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4530432 24.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1904668 10.20% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12253005 65.59% 75.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4524321 24.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1633606519 65.37% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 96 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1633622343 65.37% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 295 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 168 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 36 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 285 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 166 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 37 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.37% # Type of FU issued @@ -228,84 +228,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.37% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 642839630 25.72% 91.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 222639616 8.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 642829515 25.72% 91.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 222619482 8.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2499086402 # Type of FU issued -system.cpu.iq.rate 2.011322 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18679673 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007475 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6256352202 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3662566047 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2395383662 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1990285 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1357397 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 872084 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2516787863 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 978212 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57513083 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2499071963 # Type of FU issued +system.cpu.iq.rate 2.011043 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18681994 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007476 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6256498920 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3662616880 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2395384352 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1982839 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1348326 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 869815 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2516779289 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 974668 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57504336 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234760826 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 254713 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 106352 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 91644213 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234767844 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 254077 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 105937 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 91632646 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 271 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 267185 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 220 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 267187 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 111835519 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23640124 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1166146 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2847163562 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17865598 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679356489 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 252372715 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 183 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 265739 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14899 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 106352 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13291147 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8879247 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22170394 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2446896238 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625263073 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 52190164 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 111839194 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23661056 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1167024 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2847195647 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17872608 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679363507 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 252361148 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 180 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 266250 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15108 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 105937 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13288388 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8880688 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22169076 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2446901289 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625251329 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 52170674 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 143294528 # number of nop insts executed -system.cpu.iew.exec_refs 840836661 # number of memory reference insts executed -system.cpu.iew.exec_branches 299907540 # Number of branches executed -system.cpu.iew.exec_stores 215573588 # Number of stores executed -system.cpu.iew.exec_rate 1.969318 # Inst execution rate -system.cpu.iew.wb_sent 2424978134 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2396255746 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1371174091 # num instructions producing a value -system.cpu.iew.wb_consumers 1736703047 # num instructions consuming a value +system.cpu.iew.exec_nop 143298915 # number of nop insts executed +system.cpu.iew.exec_refs 840810767 # number of memory reference insts executed +system.cpu.iew.exec_branches 299911480 # Number of branches executed +system.cpu.iew.exec_stores 215559438 # Number of stores executed +system.cpu.iew.exec_rate 1.969060 # Inst execution rate +system.cpu.iew.wb_sent 2424991603 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2396254167 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1371180261 # num instructions producing a value +system.cpu.iew.wb_consumers 1736709964 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.928561 # insts written-back per cycle +system.cpu.iew.wb_rate 1.928304 # insts written-back per cycle system.cpu.iew.wb_fanout 0.789527 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 793041487 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 793091861 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19005172 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1126186483 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.615878 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.496171 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 19003362 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1126347446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.615647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.496030 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 601057240 53.37% 53.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181431262 16.11% 69.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90818871 8.06% 77.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53582935 4.76% 82.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36462614 3.24% 85.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28190767 2.50% 88.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22584019 2.01% 90.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22816288 2.03% 92.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 89242487 7.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 601147369 53.37% 53.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 181479999 16.11% 69.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 90892282 8.07% 77.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53587955 4.76% 82.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36442488 3.24% 85.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28128451 2.50% 88.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22594945 2.01% 90.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22821835 2.03% 92.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89252122 7.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1126186483 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1126347446 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 89242487 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 89252122 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3563986409 # The number of ROB reads -system.cpu.rob.rob_writes 5337596119 # The number of ROB writes -system.cpu.timesIdled 386257 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4487465 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3564188111 # The number of ROB reads +system.cpu.rob.rob_writes 5337700893 # The number of ROB writes +system.cpu.timesIdled 386272 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4488070 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.715713 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.715713 # CPI: Total CPI of All Threads -system.cpu.ipc 1.397208 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.397208 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3289961910 # number of integer regfile reads -system.cpu.int_regfile_writes 1921843103 # number of integer regfile writes -system.cpu.fp_regfile_reads 52840 # number of floating regfile reads -system.cpu.fp_regfile_writes 576 # number of floating regfile writes +system.cpu.cpi 0.715808 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.715808 # CPI: Total CPI of All Threads +system.cpu.ipc 1.397022 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.397022 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3289961218 # number of integer regfile reads +system.cpu.int_regfile_writes 1921862672 # number of integer regfile writes +system.cpu.fp_regfile_reads 50916 # number of floating regfile reads +system.cpu.fp_regfile_writes 565 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 769.288412 # Cycle average of tags in use -system.cpu.icache.total_refs 402674417 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 967 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 416416.149948 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 773.343215 # Cycle average of tags in use +system.cpu.icache.total_refs 402671818 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 972 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 414271.417695 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 769.288412 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.375629 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.375629 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 402674417 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 402674417 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 402674417 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 402674417 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 402674417 # number of overall hits -system.cpu.icache.overall_hits::total 402674417 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1460 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1460 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1460 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1460 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1460 # number of overall misses -system.cpu.icache.overall_misses::total 1460 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51984000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51984000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51984000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51984000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51984000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51984000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 402675877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 402675877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 402675877 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 402675877 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 402675877 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 402675877 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 773.343215 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.377609 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.377609 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 402671818 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 402671818 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 402671818 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 402671818 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 402671818 # number of overall hits +system.cpu.icache.overall_hits::total 402671818 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1451 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1451 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1451 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1451 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1451 # number of overall misses +system.cpu.icache.overall_misses::total 1451 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 52415500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 52415500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 52415500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 52415500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 52415500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 52415500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 402673269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 402673269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 402673269 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 402673269 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35605.479452 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35605.479452 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35605.479452 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36123.707788 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36123.707788 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36123.707788 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36123.707788 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36123.707788 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36123.707788 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,301 +388,301 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 493 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 493 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 493 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 493 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 493 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 493 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 967 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 967 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 967 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 967 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 967 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 967 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36487500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36487500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36487500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36487500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36487500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36487500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 479 # 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mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37732.678387 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37732.678387 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37732.678387 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37732.678387 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37732.678387 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37732.678387 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37965.534979 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37965.534979 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37965.534979 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37965.534979 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37965.534979 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37965.534979 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9177386 # number of replacements -system.cpu.dcache.tagsinuse 4086.021231 # Cycle average of tags in use -system.cpu.dcache.total_refs 702056589 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9181482 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.464408 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9177741 # number of replacements +system.cpu.dcache.tagsinuse 4086.022558 # Cycle average of tags in use +system.cpu.dcache.total_refs 702049039 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9181837 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 76.460630 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5710472000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.021231 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4086.022558 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997564 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997564 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 546233301 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 546233301 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155823284 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155823284 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 702056585 # 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number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 702049036 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 702049036 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 702049036 # number of overall hits +system.cpu.dcache.overall_hits::total 702049036 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10364055 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10364055 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4905420 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4905420 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15266394 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15266394 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15266394 # number of overall misses -system.cpu.dcache.overall_misses::total 15266394 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 211386484000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 211386484000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 166231514528 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 166231514528 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 71000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 377617998528 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 377617998528 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 377617998528 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 377617998528 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 556594477 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 556594477 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 15269475 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15269475 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15269475 # number of overall misses +system.cpu.dcache.overall_misses::total 15269475 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 211607642000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 211607642000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 166442600009 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 166442600009 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 65000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 65000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 378050242009 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 378050242009 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 378050242009 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 378050242009 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 556590009 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 556590009 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 717322979 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 717322979 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 717322979 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 717322979 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018615 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.018615 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030519 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.030519 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021282 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021282 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021282 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20401.784894 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20401.784894 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33888.710864 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33888.710864 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24735.245175 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24735.245175 # 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number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 717318511 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 717318511 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 717318511 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018621 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.018621 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030520 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.030520 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.400000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.400000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021287 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021287 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021287 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021287 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20417.456488 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20417.456488 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33930.346435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33930.346435 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24758.561903 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24758.561903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24758.561903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24758.561903 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 705064541 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1696790500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 102448 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65121 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6882.169891 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26055.965050 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3417165 # number of writebacks -system.cpu.dcache.writebacks::total 3417165 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3063278 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3063278 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3021635 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3021635 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3417249 # number of writebacks +system.cpu.dcache.writebacks::total 3417249 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3065881 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3065881 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3021758 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3021758 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6084913 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6084913 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53824994530 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9181836 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9181836 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9181836 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9181836 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97342451000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 97342451000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53846535513 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53846535513 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 40500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 40500 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3417249 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3417249 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883671 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883671 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 972 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9181837 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9182809 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 972 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9181837 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9182809 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188629 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.188737 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415389 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.415389 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188640 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.188748 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415341 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.415341 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.235149 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.235230 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.235148 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.235229 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.235149 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.235230 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36320.579111 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35578.270048 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35578.791123 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36358.951220 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36358.951220 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36320.579111 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35861.188006 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 35861.393670 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36320.579111 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35861.188006 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 35861.393670 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 7205426 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.235148 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.235229 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36570.473251 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35668.945014 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35669.581063 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36380.095498 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36380.095498 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36570.473251 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35926.636296 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 35926.926014 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36570.473251 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35926.636296 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 35926.926014 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 7260431 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 811 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 813 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8884.618989 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8930.419434 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050133 # number of writebacks -system.cpu.l2cache.writebacks::total 1050133 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 967 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376593 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1377560 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782426 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782426 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 967 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2159019 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2159986 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 967 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2159019 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2159986 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32063500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44633307000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44665370500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26000882433 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26000882433 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32063500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 70634189433 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 70666252933 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32063500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 70634189433 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 70666252933 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1050131 # number of writebacks +system.cpu.l2cache.writebacks::total 1050131 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 972 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376729 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1377701 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782366 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782366 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 972 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2159095 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2160067 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 972 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2159095 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2160067 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32474500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44762602000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44795076500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26015406452 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26015406452 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32474500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 70778008452 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 70810482952 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32474500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 70778008452 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 70810482952 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188629 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188737 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415389 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188640 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188748 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415341 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415341 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235149 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235230 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235148 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.235229 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235149 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.235230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33157.704240 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32423.023363 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32423.539084 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33231.107393 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33231.107393 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33157.704240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32715.872085 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32716.069888 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33157.704240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32715.872085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32716.069888 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235148 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.235229 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33409.979424 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32513.735092 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32514.367414 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33252.220127 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33252.220127 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33409.979424 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32781.331276 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32781.614159 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33409.979424 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32781.331276 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32781.614159 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 13d5bc965..7bf311873 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.479151 # Number of seconds simulated -sim_ticks 479150606000 # Number of ticks simulated -final_tick 479150606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.479223 # Number of seconds simulated +sim_ticks 479223482000 # Number of ticks simulated +final_tick 479223482000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 194711 # Simulator instruction rate (inst/s) -host_op_rate 217215 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60402792 # Simulator tick rate (ticks/s) -host_mem_usage 234724 # Number of bytes of host memory used -host_seconds 7932.59 # Real time elapsed on the host +host_inst_rate 194014 # Simulator instruction rate (inst/s) +host_op_rate 216437 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60195599 # Simulator tick rate (ticks/s) +host_mem_usage 234776 # Number of bytes of host memory used +host_seconds 7961.11 # Real time elapsed on the host sim_insts 1544563028 # Number of instructions simulated sim_ops 1723073840 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156296384 # Number of bytes read from this memory -system.physmem.bytes_read::total 156344896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71934976 # Number of bytes written to this memory -system.physmem.bytes_written::total 71934976 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2442131 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2442889 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1123984 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1123984 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 101246 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 326194691 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 326295937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 101246 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 101246 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 150130199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 150130199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 150130199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 101246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 326194691 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 476426136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 48448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156331072 # Number of bytes read from this memory +system.physmem.bytes_read::total 156379520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71949824 # Number of bytes written to this memory +system.physmem.bytes_written::total 71949824 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2442673 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2443430 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1124216 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1124216 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 101097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 326217470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 326318567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 150138352 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 150138352 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 150138352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 326217470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 476456920 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,141 +77,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 958301213 # number of cpu cycles simulated +system.cpu.numCycles 958446965 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 302333500 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 248015603 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16105989 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 168718741 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 157776197 # Number of BTB hits +system.cpu.BPredUnit.lookups 302424004 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 248121310 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16111337 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 166375993 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 157791713 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18362417 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 295110918 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2170236667 # Number of instructions fetch has processed -system.cpu.fetch.Branches 302333500 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 176138614 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 431684517 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 85621855 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 155290774 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 58 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 285908690 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5538082 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 950817611 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.537566 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.220819 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18325977 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 236 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 295072409 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2170601008 # Number of instructions fetch has processed +system.cpu.fetch.Branches 302424004 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 176117690 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 431730569 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 85674794 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 155376778 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 285867319 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5539236 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 950955907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.537748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.221191 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 519133170 54.60% 54.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23531871 2.47% 57.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38842821 4.09% 61.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47928811 5.04% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 41274787 4.34% 70.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 47187627 4.96% 75.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39143273 4.12% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18340446 1.93% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175434805 18.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 519225507 54.60% 54.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23584051 2.48% 57.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38809935 4.08% 61.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47901977 5.04% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 41256448 4.34% 70.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 47147738 4.96% 75.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39135623 4.12% 79.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18358633 1.93% 81.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175535995 18.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 950817611 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.315489 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.264671 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 327140938 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 132753088 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 402950990 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19241929 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68730666 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46279846 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 704 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2359084469 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2481 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68730666 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 349892865 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 63780880 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14141 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 397813217 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70585842 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2300380626 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 28739 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5556251 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56445912 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2275326533 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10618275091 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10618272387 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2704 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 950955907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.315535 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.264706 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 327119471 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 132830999 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 402990203 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19239879 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 68775355 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46282380 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 697 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2359573845 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2428 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 68775355 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 349888082 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 63823546 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14916 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 397833782 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70620226 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2300864153 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 28671 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5550118 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 56484879 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2275806889 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10620956453 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10620952653 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3800 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319938 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 569006595 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5461 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5458 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 155601466 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 627528670 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 219567806 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 87006993 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68089228 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2199559403 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1526 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2020307102 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5002319 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 472139724 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1101721580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1355 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 950817611 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.124810 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.914497 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 569486951 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5312 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5309 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 155780896 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 627644360 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 219694213 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 87145300 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68089448 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2199982180 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1528 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2020409598 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4999430 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 472571343 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1103696346 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1357 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 950955907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.124609 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.914480 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 272456432 28.65% 28.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 148972541 15.67% 44.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161045064 16.94% 61.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 117808406 12.39% 73.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124487858 13.09% 86.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 74416152 7.83% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38351621 4.03% 98.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10558999 1.11% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2720538 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 272613444 28.67% 28.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 148967706 15.67% 44.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160979511 16.93% 61.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 117706760 12.38% 73.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124599704 13.10% 86.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 74507798 7.84% 94.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38341084 4.03% 98.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10540920 1.11% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2698980 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 950817611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 950955907 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 866703 3.46% 3.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4868 0.02% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18978969 75.82% 79.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5181359 20.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 849524 3.40% 3.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4750 0.02% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18987433 76.01% 79.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5139841 20.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236552318 61.21% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 932322 0.05% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236587791 61.20% 61.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 931138 0.05% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.25% # Type of FU issued @@ -233,90 +233,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.25% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 41 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 64 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 12 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 588904292 29.15% 90.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193918099 9.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 588900248 29.15% 90.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193990319 9.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2020307102 # Type of FU issued -system.cpu.iq.rate 2.108217 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25031899 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012390 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5021465735 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2671886632 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1961215820 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 298 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 520 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2045338849 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 152 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63654285 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2020409598 # Type of FU issued +system.cpu.iq.rate 2.108004 # Inst issue rate +system.cpu.iq.fu_busy_cnt 24981548 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012365 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5021755668 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2672741554 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1961287360 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 413 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 736 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 160 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2045390937 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 209 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63645440 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 141601900 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 294123 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189203 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 44720760 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 141717590 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 292895 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189897 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 44847167 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1137177 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 1141778 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68730666 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28026748 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1485770 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2199569564 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5556141 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 627528670 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 219567806 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1463 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 343326 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56332 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189203 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8602483 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10215552 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18818035 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1990553449 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574287819 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29753653 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 68775355 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28059003 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1485687 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2199992043 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5558489 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 627644360 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 219694213 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 343629 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 56102 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189897 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8602375 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10226115 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18828490 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1990642810 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574277068 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29766788 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 8635 # number of nop insts executed -system.cpu.iew.exec_refs 765252053 # number of memory reference insts executed -system.cpu.iew.exec_branches 238421113 # Number of branches executed -system.cpu.iew.exec_stores 190964234 # Number of stores executed -system.cpu.iew.exec_rate 2.077169 # Inst execution rate -system.cpu.iew.wb_sent 1970075771 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1961215932 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296581898 # num instructions producing a value -system.cpu.iew.wb_consumers 2068899277 # num instructions consuming a value +system.cpu.iew.exec_nop 8335 # number of nop insts executed +system.cpu.iew.exec_refs 765299887 # number of memory reference insts executed +system.cpu.iew.exec_branches 238409980 # Number of branches executed +system.cpu.iew.exec_stores 191022819 # Number of stores executed +system.cpu.iew.exec_rate 2.076946 # Inst execution rate +system.cpu.iew.wb_sent 1970153008 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1961287520 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296694675 # num instructions producing a value +system.cpu.iew.wb_consumers 2069023421 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.046555 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626701 # average fanout of values written-back +system.cpu.iew.wb_rate 2.046318 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626718 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 476570852 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 476993558 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 171 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16105557 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 882086946 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.953406 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.727739 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16110924 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 882180553 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.953199 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.727625 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 391458685 44.38% 44.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 194911052 22.10% 66.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73858259 8.37% 74.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35176751 3.99% 78.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19156374 2.17% 81.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30712442 3.48% 84.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19230333 2.18% 86.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11318069 1.28% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106264981 12.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 391561558 44.39% 44.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 194873977 22.09% 66.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73868669 8.37% 74.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35208101 3.99% 78.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19136047 2.17% 81.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30738627 3.48% 84.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19218397 2.18% 86.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11310881 1.28% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106264296 12.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 882086946 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 882180553 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563046 # Number of instructions committed system.cpu.commit.committedOps 1723073858 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -327,70 +327,70 @@ system.cpu.commit.branches 213462364 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941845 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106264981 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106264296 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2975466076 # The number of ROB reads -system.cpu.rob.rob_writes 4468185114 # The number of ROB writes -system.cpu.timesIdled 802459 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7483602 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2975983074 # The number of ROB reads +system.cpu.rob.rob_writes 4469074827 # The number of ROB writes +system.cpu.timesIdled 802305 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7491058 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563028 # Number of Instructions Simulated system.cpu.committedOps 1723073840 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563028 # Number of Instructions Simulated -system.cpu.cpi 0.620435 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.620435 # CPI: Total CPI of All Threads -system.cpu.ipc 1.611772 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.611772 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9971004084 # number of integer regfile reads -system.cpu.int_regfile_writes 1941069131 # number of integer regfile writes -system.cpu.fp_regfile_reads 114 # number of floating regfile reads -system.cpu.fp_regfile_writes 123 # number of floating regfile writes -system.cpu.misc_regfile_reads 2910834876 # number of misc regfile reads +system.cpu.cpi 0.620530 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.620530 # CPI: Total CPI of All Threads +system.cpu.ipc 1.611527 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.611527 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9971495260 # number of integer regfile reads +system.cpu.int_regfile_writes 1941105565 # number of integer regfile writes +system.cpu.fp_regfile_reads 174 # number of floating regfile reads +system.cpu.fp_regfile_writes 178 # number of floating regfile writes +system.cpu.misc_regfile_reads 2911260843 # number of misc regfile reads system.cpu.misc_regfile_writes 126 # number of misc regfile writes -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 634.471646 # Cycle average of tags in use -system.cpu.icache.total_refs 285907562 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 789 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 362366.998733 # Average number of references to valid blocks. +system.cpu.icache.replacements 26 # number of replacements +system.cpu.icache.tagsinuse 632.958434 # Cycle average of tags in use +system.cpu.icache.total_refs 285866178 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 790 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 361855.921519 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 634.471646 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.309801 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.309801 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 285907562 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 285907562 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 285907562 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 285907562 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 285907562 # number of overall hits -system.cpu.icache.overall_hits::total 285907562 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1128 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1128 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1128 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1128 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1128 # number of overall misses -system.cpu.icache.overall_misses::total 1128 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40115500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40115500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40115500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40115500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40115500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40115500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 285908690 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 285908690 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 285908690 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 285908690 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 285908690 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 285908690 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 632.958434 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.309062 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.309062 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 285866178 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 285866178 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 285866178 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 285866178 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 285866178 # number of overall hits +system.cpu.icache.overall_hits::total 285866178 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses +system.cpu.icache.overall_misses::total 1141 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 40467500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 40467500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 40467500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 40467500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 40467500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 40467500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 285867319 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 285867319 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 285867319 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 285867319 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 285867319 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 285867319 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35563.386525 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35563.386525 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35563.386525 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35563.386525 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35563.386525 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35563.386525 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35466.695881 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35466.695881 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35466.695881 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35466.695881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35466.695881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35466.695881 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,256 +399,256 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 339 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 339 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 339 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 339 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 339 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 789 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 789 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 789 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 789 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 789 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 789 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28841500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28841500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28841500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28841500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28841500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28841500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 351 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 351 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 351 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 351 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 790 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 790 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 790 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 790 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 790 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28839000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28839000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28839000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28839000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28839000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28839000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36554.499366 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36554.499366 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36554.499366 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36554.499366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36554.499366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36554.499366 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36505.063291 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36505.063291 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36505.063291 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36505.063291 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36505.063291 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36505.063291 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9617864 # number of replacements -system.cpu.dcache.tagsinuse 4087.822620 # Cycle average of tags in use -system.cpu.dcache.total_refs 661858061 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9621960 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.786200 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3369466000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.822620 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998004 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998004 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 494463197 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 494463197 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167394718 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167394718 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 84 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 84 # number of LoadLockedReq hits +system.cpu.dcache.replacements 9619162 # number of replacements +system.cpu.dcache.tagsinuse 4087.804839 # Cycle average of tags in use +system.cpu.dcache.total_refs 661851236 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9623258 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.776212 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3371932000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.804839 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997999 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997999 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 494456426 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 494456426 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167394662 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167394662 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 86 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 86 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 62 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 62 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 661857915 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 661857915 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 661857915 # number of overall hits -system.cpu.dcache.overall_hits::total 661857915 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10787388 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10787388 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5191329 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5191329 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 661851088 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 661851088 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 661851088 # number of overall hits +system.cpu.dcache.overall_hits::total 661851088 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10788938 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10788938 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5191385 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5191385 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15978717 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15978717 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15978717 # number of overall misses -system.cpu.dcache.overall_misses::total 15978717 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 258680588500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 258680588500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 196204904993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 196204904993 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 15980323 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15980323 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15980323 # number of overall misses +system.cpu.dcache.overall_misses::total 15980323 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 258868265000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 258868265000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 196333546730 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 196333546730 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 118500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 118500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 454885493493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 454885493493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 454885493493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 454885493493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 505250585 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 505250585 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 455201811730 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 455201811730 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 455201811730 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 455201811730 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 505245364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 505245364 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 87 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 87 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 89 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 89 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 62 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 62 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 677836632 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 677836632 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 677836632 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 677836632 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021351 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021351 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 677831411 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 677831411 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 677831411 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 677831411 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021354 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021354 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030080 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.030080 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034483 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034483 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023573 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023573 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023573 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023573 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23979.909548 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23979.909548 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37794.735220 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37794.735220 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033708 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033708 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023576 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023576 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023576 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023576 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23993.859729 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23993.859729 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37819.107373 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37819.107373 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 39500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 39500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28468.211402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28468.211402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28468.211402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28468.211402 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2516165984 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 147500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 424894 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5921.867534 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16388.888889 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28485.144620 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28485.144620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28485.144620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28485.144620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2522668245 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 141500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 425263 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5932.019115 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23583.333333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3474501 # number of writebacks -system.cpu.dcache.writebacks::total 3474501 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3059372 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3059372 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3297385 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3297385 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3474615 # number of writebacks +system.cpu.dcache.writebacks::total 3474615 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3059553 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3059553 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3297512 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3297512 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6356757 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6356757 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6356757 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6356757 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7728016 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7728016 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893944 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893944 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9621960 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9621960 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9621960 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9621960 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 124261380000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 124261380000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91432769312 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91432769312 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215694149312 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215694149312 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215694149312 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215694149312 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015295 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015295 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 6357065 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6357065 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6357065 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6357065 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729385 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7729385 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893873 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893873 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9623258 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9623258 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9623258 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9623258 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 124446584000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 124446584000 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33015.171504 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33826.602835 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33826.351057 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33015.171504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33826.602835 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33826.351057 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 757 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611893 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1612650 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830780 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 830780 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 757 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2442673 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2443430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 757 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2442673 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2443430 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25045000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 52994170500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53019215500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 30019129886 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 30019129886 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25045000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 83013300386 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 83038345386 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25045000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 83013300386 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 83038345386 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208541 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208618 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438667 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438667 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253830 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.253888 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253830 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.253888 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33084.544254 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32876.977876 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32877.075311 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36133.669426 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36133.669426 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33084.544254 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33984.614554 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33984.335703 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33084.544254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33984.614554 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33984.335703 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |