diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:49 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:49 -0400 |
| commit | 08f7a8bc005507117ffda41f283adecf7e4d24f2 (patch) | |
| tree | d3588f01b572538601360998b89e23607549934c /tests/long/se/60.bzip2/ref | |
| parent | 93a8423dea8f8194d83df85a5b3043f9beaf0a1e (diff) | |
| download | gem5-08f7a8bc005507117ffda41f283adecf7e4d24f2.tar.xz | |
stats: Update stats to reflect bus retry changes
This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
Diffstat (limited to 'tests/long/se/60.bzip2/ref')
3 files changed, 1216 insertions, 1216 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 4d872659d..6baeed8b3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.993559 # Nu sim_ticks 993559170500 # Number of ticks simulated final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139940 # Simulator instruction rate (inst/s) -host_op_rate 139940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76403951 # Simulator tick rate (ticks/s) -host_mem_usage 449176 # Number of bytes of host memory used -host_seconds 13004.03 # Real time elapsed on the host +host_inst_rate 90803 # Simulator instruction rate (inst/s) +host_op_rate 90803 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49576515 # Simulator tick rate (ticks/s) +host_mem_usage 449304 # Number of bytes of host memory used +host_seconds 20040.92 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -36,7 +36,7 @@ system.physmem.bw_total::cpu.data 126177745 # To system.physmem.bw_total::total 191811167 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1959688 # Total number of read requests seen system.physmem.writeReqs 1018058 # Total number of write requests seen -system.physmem.cpureqs 2977859 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 2977748 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 125420032 # Total number of bytes read from memory system.physmem.bytesWritten 65155712 # Total number of bytes written to memory system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize() @@ -76,7 +76,7 @@ system.physmem.perBankWrReqs::13 64147 # Tr system.physmem.perBankWrReqs::14 63647 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 64278 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 113 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry system.physmem.totGap 993559118500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index e183c5fce..75aae5e90 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.665771 # Number of seconds simulated -sim_ticks 665770972500 # Number of ticks simulated -final_tick 665770972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.665696 # Number of seconds simulated +sim_ticks 665695988500 # Number of ticks simulated +final_tick 665695988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179472 # Simulator instruction rate (inst/s) -host_op_rate 179472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68827168 # Simulator tick rate (ticks/s) -host_mem_usage 452252 # Number of bytes of host memory used -host_seconds 9673.08 # Real time elapsed on the host +host_inst_rate 147850 # Simulator instruction rate (inst/s) +host_op_rate 147850 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56693787 # Simulator tick rate (ticks/s) +host_mem_usage 452372 # Number of bytes of host memory used +host_seconds 11741.96 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 62016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125796608 # Number of bytes read from this memory -system.physmem.bytes_read::total 125858624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65265344 # Number of bytes written to this memory -system.physmem.bytes_written::total 65265344 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 969 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965572 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966541 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019771 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019771 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 188948772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 189041922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98029723 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98029723 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98029723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 188948772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 287071645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966541 # Total number of read requests seen -system.physmem.writeReqs 1019771 # Total number of write requests seen -system.physmem.cpureqs 2988947 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125858624 # Total number of bytes read from memory -system.physmem.bytesWritten 65265344 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125858624 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65265344 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 566 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125794176 # Number of bytes read from this memory +system.physmem.bytes_read::total 125855680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65263360 # Number of bytes written to this memory +system.physmem.bytes_written::total 65263360 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965534 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966495 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019740 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019740 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 188966402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 189058793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98037785 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98037785 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98037785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 188966402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 287096578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966495 # Total number of read requests seen +system.physmem.writeReqs 1019740 # Total number of write requests seen +system.physmem.cpureqs 2986251 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125855680 # Total number of bytes read from memory +system.physmem.bytesWritten 65263360 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125855680 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65263360 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 570 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 122314 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 122187 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 124202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122594 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 122637 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 122329 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 122200 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 124178 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123636 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122601 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 120701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 121432 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121606 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 121460 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 123481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 125598 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 124291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 123180 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 124411 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63480 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 62406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63107 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63843 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 64137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63874 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63470 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63464 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 63489 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63362 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64287 # Track writes on a per bank basis +system.physmem.perBankRdReqs::7 121425 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121612 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122268 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 121458 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 123448 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 125589 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 124287 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 123163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 124393 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63486 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 62408 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63108 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 64141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63880 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63465 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63456 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 63488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63819 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63352 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 64238 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64665 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64277 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 63760 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64350 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64358 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2635 # Number of times wr buffer was full causing retry -system.physmem.totGap 665770904000 # Total gap between requests +system.physmem.numWrRetry 16 # Number of times wr buffer was full causing retry +system.physmem.totGap 665695920000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966541 # Categorize read packet sizes +system.physmem.readPktSize::6 1966495 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1019771 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1625771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 234883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 77503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27794 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019740 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1625686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 234777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 77588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -124,88 +124,88 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 43943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44298 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see -system.physmem.totQLat 34478547500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 102599787500 # Sum of mem lat for all requests -system.physmem.totBusLat 9829875000 # Total cycles spent in databus access -system.physmem.totBankLat 58291365000 # Total cycles spent in bank access -system.physmem.avgQLat 17537.63 # Average queueing delay per request -system.physmem.avgBankLat 29650.10 # Average bank access latency per request +system.physmem.totQLat 34438847000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 102566423250 # Sum of mem lat for all requests +system.physmem.totBusLat 9829625000 # Total cycles spent in databus access +system.physmem.totBankLat 58297951250 # Total cycles spent in bank access +system.physmem.avgQLat 17517.88 # Average queueing delay per request +system.physmem.avgBankLat 29654.21 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52187.74 # Average memory access latency -system.physmem.avgRdBW 189.04 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 98.03 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 189.04 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 98.03 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 52172.09 # Average memory access latency +system.physmem.avgRdBW 189.06 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 98.04 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 189.06 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 98.04 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.24 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.14 # Average write queue length over time -system.physmem.readRowHits 776350 # Number of row buffer hits during reads -system.physmem.writeRowHits 285987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.04 # Row buffer hit rate for writes -system.physmem.avgGap 222940.84 # Average gap between requests -system.cpu.branchPred.lookups 381390262 # Number of BP lookups -system.cpu.branchPred.condPredicted 296397889 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16086653 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262140629 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259559256 # Number of BTB hits +system.physmem.avgWrQLen 10.61 # Average write queue length over time +system.physmem.readRowHits 776012 # Number of row buffer hits during reads +system.physmem.writeRowHits 286087 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.05 # Row buffer hit rate for writes +system.physmem.avgGap 222921.48 # Average gap between requests +system.cpu.branchPred.lookups 381386947 # Number of BP lookups +system.cpu.branchPred.condPredicted 296385810 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16088637 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262415494 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259543645 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.015272 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24699160 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3055 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.905610 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24703591 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3035 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613788534 # DTB read hits -system.cpu.dtb.read_misses 11249325 # DTB read misses +system.cpu.dtb.read_hits 613791968 # DTB read hits +system.cpu.dtb.read_misses 11248781 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625037859 # DTB read accesses -system.cpu.dtb.write_hits 212245958 # DTB write hits -system.cpu.dtb.write_misses 7142739 # DTB write misses +system.cpu.dtb.read_accesses 625040749 # DTB read accesses +system.cpu.dtb.write_hits 212266069 # DTB write hits +system.cpu.dtb.write_misses 7139950 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219388697 # DTB write accesses -system.cpu.dtb.data_hits 826034492 # DTB hits -system.cpu.dtb.data_misses 18392064 # DTB misses +system.cpu.dtb.write_accesses 219406019 # DTB write accesses +system.cpu.dtb.data_hits 826058037 # DTB hits +system.cpu.dtb.data_misses 18388731 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844426556 # DTB accesses -system.cpu.itb.fetch_hits 390787767 # ITB hits -system.cpu.itb.fetch_misses 43 # ITB misses +system.cpu.dtb.data_accesses 844446768 # DTB accesses +system.cpu.itb.fetch_hits 390789739 # ITB hits +system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 390787810 # ITB accesses +system.cpu.itb.fetch_accesses 390789783 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,138 +219,138 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1331541946 # number of cpu cycles simulated +system.cpu.numCycles 1331391978 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402238482 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3159760476 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381390262 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284258416 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574242721 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140320135 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 173885771 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1317 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 44 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 390787767 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8065204 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1266865295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494157 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152669 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402247693 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3159701831 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381386947 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284247236 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574240478 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140323731 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 173777898 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1315 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 390789739 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8060023 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1266766339 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494305 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152696 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 692622574 54.67% 54.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42615431 3.36% 58.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21758353 1.72% 59.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39697295 3.13% 62.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129259260 10.20% 73.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61526950 4.86% 77.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38544819 3.04% 80.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28129154 2.22% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212711459 16.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 692525861 54.67% 54.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42625697 3.36% 58.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21759185 1.72% 59.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39691714 3.13% 62.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129252182 10.20% 73.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61534262 4.86% 77.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38544537 3.04% 80.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28127846 2.22% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212705055 16.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1266865295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286428 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.373009 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 433949818 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 155380202 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542435049 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18604092 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116496134 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58311036 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 855 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3087126857 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2089 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116496134 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 456815247 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 101557658 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5194 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535499027 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56492035 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3005134049 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 566488 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1739616 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 50408333 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2246840239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3897438135 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3896197591 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1240544 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1266766339 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.286457 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.373232 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433937783 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 155286584 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542483654 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18560300 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116498018 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58313191 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 862 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3087105649 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2059 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116498018 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 456816204 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 101540810 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6220 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535489445 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56415642 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3005086963 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 566623 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1738834 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 50324811 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2246778226 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3897347889 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3896105158 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1242731 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 870637276 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 168 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 870575263 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 167 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 166 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121366950 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679350790 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255350759 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67967300 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37114772 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2723579625 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 126 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2508981641 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3091159 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 978310045 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 415071720 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 97 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1266865295 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.980464 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.972855 # Number of insts issued each cycle +system.cpu.rename.skidInsts 121265991 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679360736 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255356957 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68007624 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36872048 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2723554804 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 129 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2508984537 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3092752 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 978311226 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 415025058 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 100 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1266766339 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.980621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.972970 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 426523141 33.67% 33.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201951837 15.94% 49.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185492394 14.64% 64.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153160708 12.09% 76.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133131866 10.51% 86.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 81031270 6.40% 93.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65244416 5.15% 98.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15224722 1.20% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5104941 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 426534847 33.67% 33.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201890440 15.94% 49.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185333352 14.63% 64.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153215856 12.10% 76.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133163574 10.51% 86.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81070069 6.40% 93.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65235911 5.15% 98.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15218602 1.20% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5103688 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1266865295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1266766339 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2143481 11.64% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11871999 64.46% 76.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4401590 23.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2143232 11.63% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11878025 64.46% 76.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4404432 23.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643559437 65.51% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 106 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643533281 65.51% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 99 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 261 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 268 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 31 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 192 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 26 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.51% # Type of FU issued @@ -373,84 +373,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.51% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641411468 25.56% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224010136 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641423714 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224026917 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2508981641 # Type of FU issued -system.cpu.iq.rate 1.884268 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18417070 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007340 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6304440735 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3700781380 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2412589185 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1896071 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1214370 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 849902 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2526461544 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 937167 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62583251 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2508984537 # Type of FU issued +system.cpu.iq.rate 1.884482 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18425689 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007344 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6304354052 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3700755338 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2412575558 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1899802 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1217218 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 851053 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2526471243 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 938983 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62590757 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234755127 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263530 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107682 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94622257 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234765073 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 264281 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 108176 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94628455 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 167 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1505929 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 156 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1505453 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116496134 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 45259128 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1153276 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2865598045 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8882954 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679350790 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255350759 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 126 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 296462 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17110 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107682 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10363121 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8561161 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18924282 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2461596227 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625038408 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47385414 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116498018 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 45291754 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1153048 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2865571059 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8871235 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679360736 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255356957 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 129 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 296395 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17051 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 108176 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10360108 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8562955 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18923063 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2461579211 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625041270 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47405326 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142018294 # number of nop insts executed -system.cpu.iew.exec_refs 844427141 # number of memory reference insts executed -system.cpu.iew.exec_branches 300792164 # Number of branches executed -system.cpu.iew.exec_stores 219388733 # Number of stores executed -system.cpu.iew.exec_rate 1.848681 # Inst execution rate -system.cpu.iew.wb_sent 2441396740 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413439087 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388573479 # num instructions producing a value -system.cpu.iew.wb_consumers 1764243384 # num instructions consuming a value +system.cpu.iew.exec_nop 142016126 # number of nop insts executed +system.cpu.iew.exec_refs 844447329 # number of memory reference insts executed +system.cpu.iew.exec_branches 300798489 # Number of branches executed +system.cpu.iew.exec_stores 219406059 # Number of stores executed +system.cpu.iew.exec_rate 1.848876 # Inst execution rate +system.cpu.iew.wb_sent 2441376362 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413426611 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388583006 # num instructions producing a value +system.cpu.iew.wb_consumers 1764301470 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.812515 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.787065 # average fanout of values written-back +system.cpu.iew.wb_rate 1.812709 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.787044 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 824671147 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 824638318 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16085857 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1150369161 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.581910 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.512649 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16087839 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1150268321 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.582048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.512804 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 636844570 55.36% 55.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174611268 15.18% 70.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86171312 7.49% 78.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53631613 4.66% 82.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34569452 3.01% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25367501 2.21% 87.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21831937 1.90% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22907604 1.99% 91.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94433904 8.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 636823398 55.36% 55.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174498580 15.17% 70.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86188355 7.49% 78.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53663047 4.67% 82.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34548846 3.00% 85.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25343487 2.20% 87.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21850232 1.90% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22917524 1.99% 91.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94434852 8.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1150369161 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1150268321 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,189 +461,189 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94433904 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94434852 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3614607330 # The number of ROB reads -system.cpu.rob.rob_writes 5405498913 # The number of ROB writes -system.cpu.timesIdled 817784 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64676651 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3614472713 # The number of ROB reads +system.cpu.rob.rob_writes 5405435258 # The number of ROB writes +system.cpu.timesIdled 818038 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64625639 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.766998 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.766998 # CPI: Total CPI of All Threads -system.cpu.ipc 1.303785 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.303785 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3317361939 # number of integer regfile reads -system.cpu.int_regfile_writes 1931707111 # number of integer regfile writes -system.cpu.fp_regfile_reads 30073 # number of floating regfile reads -system.cpu.fp_regfile_writes 529 # number of floating regfile writes +system.cpu.cpi 0.766912 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.766912 # CPI: Total CPI of All Threads +system.cpu.ipc 1.303931 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.303931 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3317336179 # number of integer regfile reads +system.cpu.int_regfile_writes 1931663734 # number of integer regfile writes +system.cpu.fp_regfile_reads 30582 # number of floating regfile reads +system.cpu.fp_regfile_writes 562 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 776.168102 # Cycle average of tags in use -system.cpu.icache.total_refs 390786293 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 969 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 403288.228070 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 772.833210 # Cycle average of tags in use +system.cpu.icache.total_refs 390788277 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 406647.530697 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 776.168102 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.378988 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.378988 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 390786293 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 390786293 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 390786293 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 390786293 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 390786293 # number of overall hits -system.cpu.icache.overall_hits::total 390786293 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1474 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1474 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1474 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1474 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1474 # number of overall misses -system.cpu.icache.overall_misses::total 1474 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 87004499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 87004499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 87004499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 87004499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 87004499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 87004499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 390787767 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 390787767 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 390787767 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 390787767 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 390787767 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 390787767 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 772.833210 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.377360 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.377360 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 390788277 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 390788277 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 390788277 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 390788277 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 390788277 # number of overall hits +system.cpu.icache.overall_hits::total 390788277 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1461 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1461 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1461 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1461 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1461 # 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miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61254.942768 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75750.557143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75738.864874 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74942.639840 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74942.639840 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61254.942768 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75431.964545 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75425.036423 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61254.942768 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75431.964545 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75425.036423 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -652,180 +652,180 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019771 # number of writebacks -system.cpu.l2cache.writebacks::total 1019771 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 969 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190438 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191407 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775134 # 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number of replacements -system.cpu.dcache.tagsinuse 4087.525084 # Cycle average of tags in use -system.cpu.dcache.total_refs 694351222 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180133 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.636292 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9176040 # number of replacements +system.cpu.dcache.tagsinuse 4087.524129 # Cycle average of tags in use +system.cpu.dcache.total_refs 694346796 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180136 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.635785 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5069314000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.525084 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4087.524129 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997931 # 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number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710713347 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710713347 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710713347 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710713347 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020510 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020510 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031620 # 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miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023023 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023023 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023023 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023023 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26167.913100 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26167.913100 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44085.212756 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44085.212756 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31718.737826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31718.737826 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12309965 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5809756 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 734892 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.750713 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 89.196979 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31732.644407 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31732.644407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31732.644407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31732.644407 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12246964 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5806156 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 735074 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.660859 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 89.140339 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3724718 # number of writebacks -system.cpu.dcache.writebacks::total 3724718 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3983366 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3983366 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198630 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3198630 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7181996 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7181996 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7181996 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7181996 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296577 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296577 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883555 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883555 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3724734 # number of writebacks +system.cpu.dcache.writebacks::total 3724734 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3984427 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3984427 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198422 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3198422 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7182849 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7182849 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7182849 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7182849 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296563 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296563 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883572 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883572 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180132 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180132 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180132 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180132 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159251608500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 159251608500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71602703007 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71602703007 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159317479500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 159317479500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71504257401 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71504257401 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 47500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 47500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230854311507 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 230854311507 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230854311507 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 230854311507 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230821736901 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230821736901 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230821736901 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230821736901 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013267 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013267 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.522913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.522913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38014.660048 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38014.660048 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21834.592465 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21834.592465 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37962.051571 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37962.051571 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 47500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 47500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25143.610296 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25143.610296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25143.610296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25143.610296 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 8f6283962..765d31514 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517371 # Number of seconds simulated -sim_ticks 517371024000 # Number of ticks simulated -final_tick 517371024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517386 # Number of seconds simulated +sim_ticks 517386284000 # Number of ticks simulated +final_tick 517386284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139447 # Simulator instruction rate (inst/s) -host_op_rate 155563 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46709499 # Simulator tick rate (ticks/s) -host_mem_usage 485516 # Number of bytes of host memory used -host_seconds 11076.36 # Real time elapsed on the host +host_inst_rate 116249 # Simulator instruction rate (inst/s) +host_op_rate 129685 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38940374 # Simulator tick rate (ticks/s) +host_mem_usage 515484 # Number of bytes of host memory used +host_seconds 13286.63 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143734144 # Number of bytes read from this memory -system.physmem.bytes_read::total 143782208 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70446784 # Number of bytes written to this memory -system.physmem.bytes_written::total 70446784 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245846 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246597 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100731 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100731 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 277816378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 277909279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136162987 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136162987 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136162987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 277816378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 414072265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246597 # Total number of read requests seen -system.physmem.writeReqs 1100731 # Total number of write requests seen -system.physmem.cpureqs 3350452 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143782208 # Total number of bytes read from memory -system.physmem.bytesWritten 70446784 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143782208 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70446784 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 642 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143753728 # Number of bytes read from this memory +system.physmem.bytes_read::total 143802048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70452928 # Number of bytes written to this memory +system.physmem.bytes_written::total 70452928 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2246152 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246907 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100827 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100827 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 277846036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 277939428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93393 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93393 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136170846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136170846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136170846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 277846036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 414110274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246907 # Total number of read requests seen +system.physmem.writeReqs 1100827 # Total number of write requests seen +system.physmem.cpureqs 3347751 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143802048 # Total number of bytes read from memory +system.physmem.bytesWritten 70452928 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143802048 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70452928 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 626 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 141495 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 139690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 141603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 141749 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 142295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 140068 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 141091 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 140693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 138519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 136203 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 140693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 141066 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 139208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 139271 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 141669 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69094 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 68448 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 69468 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 69338 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 68952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 69046 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 67828 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 66957 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 69534 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 69263 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 69109 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 68653 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 68505 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 68959 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 141345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 139694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 141615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 141701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 142344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 140081 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 141241 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 140671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 138680 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 136252 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140704 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 140722 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 141030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 139261 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 139241 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 141699 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69025 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 68435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 69463 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 69359 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 69032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68404 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 67870 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 66992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 69579 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 69317 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 69127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 68645 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 68513 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 68932 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3124 # Number of times wr buffer was full causing retry -system.physmem.totGap 517370944500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times wr buffer was full causing retry +system.physmem.totGap 517386204500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246597 # Categorize read packet sizes +system.physmem.readPktSize::6 2246907 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1100731 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1563680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 451075 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 162592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100827 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1563682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 451240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,68 +124,68 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 44125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 44008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see -system.physmem.totQLat 51812524750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 131293078500 # Sum of mem lat for all requests -system.physmem.totBusLat 11229775000 # Total cycles spent in databus access -system.physmem.totBankLat 68250778750 # Total cycles spent in bank access -system.physmem.avgQLat 23069.26 # Average queueing delay per request -system.physmem.avgBankLat 30388.31 # Average bank access latency per request +system.physmem.totQLat 51773260500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 131271366750 # Sum of mem lat for all requests +system.physmem.totBusLat 11231405000 # Total cycles spent in databus access +system.physmem.totBankLat 68266701250 # Total cycles spent in bank access +system.physmem.avgQLat 23048.43 # Average queueing delay per request +system.physmem.avgBankLat 30390.99 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58457.57 # Average memory access latency -system.physmem.avgRdBW 277.91 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 136.16 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 277.91 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 136.16 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 58439.42 # Average memory access latency +system.physmem.avgRdBW 277.94 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 136.17 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 277.94 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 136.17 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.23 # Data bus utilization in percentage +system.physmem.busUtil 3.24 # Data bus utilization in percentage system.physmem.avgRdQLen 0.25 # Average read queue length over time -system.physmem.avgWrQLen 10.92 # Average write queue length over time -system.physmem.readRowHits 827855 # Number of row buffer hits during reads -system.physmem.writeRowHits 271156 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 24.63 # Row buffer hit rate for writes -system.physmem.avgGap 154562.37 # Average gap between requests -system.cpu.branchPred.lookups 303290873 # Number of BP lookups -system.cpu.branchPred.condPredicted 249488582 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15222231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 174596633 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161469311 # Number of BTB hits +system.physmem.avgWrQLen 10.87 # Average write queue length over time +system.physmem.readRowHits 827731 # Number of row buffer hits during reads +system.physmem.writeRowHits 271594 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 24.67 # Row buffer hit rate for writes +system.physmem.avgGap 154548.18 # Average gap between requests +system.cpu.branchPred.lookups 303270186 # Number of BP lookups +system.cpu.branchPred.condPredicted 249470609 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15218764 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 173872286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161453824 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.481343 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17557313 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 202 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.857711 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17556602 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 209 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,99 +229,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1034742049 # number of cpu cycles simulated +system.cpu.numCycles 1034772569 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 298209547 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2186343540 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303290873 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 179026624 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435120674 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 87852250 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 155399906 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 380 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 288562414 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5732154 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 958634216 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.523474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.213325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 298199766 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2186256801 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303270186 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179010426 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435094842 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 87837458 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 155394915 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 268 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 288550611 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5724997 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 958581863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.523504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.213349 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 523513675 54.61% 54.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25518990 2.66% 57.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39095186 4.08% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48349741 5.04% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43010158 4.49% 70.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46440341 4.84% 75.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38425121 4.01% 79.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18710957 1.95% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175570047 18.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 523487088 54.61% 54.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25513973 2.66% 57.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39086986 4.08% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48352591 5.04% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43006673 4.49% 70.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46441362 4.84% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38409512 4.01% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18721015 1.95% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175562663 18.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 958634216 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.293108 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.112936 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 329763250 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 133666994 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405221512 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20079412 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69903048 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46058380 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2367190993 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2433 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69903048 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 353304996 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 63447183 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15614 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400231748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71731627 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2304653779 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 133097 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5040028 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58589233 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2280042978 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10643127773 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10643124880 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2893 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 958581863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.293079 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.112790 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 329745900 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 133661747 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405202825 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20079986 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69891405 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46059780 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 688 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2367115109 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2459 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69891405 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 353286700 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 63436503 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16572 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400214250 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71736433 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2304580712 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 133421 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5040530 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58596294 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2279975350 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10642754356 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10642751444 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2912 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 573723048 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 497 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 494 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 158827938 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624515157 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220983969 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86332349 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 71315853 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2201513470 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 522 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018112827 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4002858 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 473886256 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1126241029 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 958634216 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.105196 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906381 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 573655420 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 616 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 613 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 158838581 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624481317 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220982521 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86134760 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71220480 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2201443562 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 640 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018130110 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4002265 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 473800004 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1125761712 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 470 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 958581863 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.105329 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906457 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 277594004 28.96% 28.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151404549 15.79% 44.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161201477 16.82% 61.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119812250 12.50% 74.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123999377 12.94% 87.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73820536 7.70% 94.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38419650 4.01% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9808498 1.02% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2573875 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 277596353 28.96% 28.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151362321 15.79% 44.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161174547 16.81% 61.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119755421 12.49% 74.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124050787 12.94% 87.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73850082 7.70% 94.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38416449 4.01% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9807044 1.02% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2568859 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 958634216 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 958581863 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 872312 3.66% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5645 0.02% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 872338 3.65% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5545 0.02% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available @@ -349,13 +349,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18268766 76.62% 80.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4697940 19.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18290184 76.58% 80.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4715401 19.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236677496 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 926030 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236676135 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925418 0.05% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -377,90 +377,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 33 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 42 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587482532 29.11% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193026708 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587478696 29.11% 90.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193049790 9.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018112827 # Type of FU issued -system.cpu.iq.rate 1.950354 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23844663 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011815 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5022707128 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2675590256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957438118 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 556 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2041957357 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64629974 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018130110 # Type of FU issued +system.cpu.iq.rate 1.950313 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23883468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011834 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5022727533 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2675434216 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957455216 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 283 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 532 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 114 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042013436 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 142 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64634043 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138588388 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 271831 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192988 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46136924 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138554548 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 275107 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 193018 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46135476 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4659196 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4656763 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69903048 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28888784 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1501235 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2201514122 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6139547 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624515157 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220983969 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 460 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 475783 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 89669 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192988 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8156378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9617829 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17774207 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988116656 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573901246 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29996171 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69891405 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28868892 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1502139 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2201444330 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6139194 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624481317 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220982521 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 578 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 475852 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 89903 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 193018 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8153538 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9615023 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17768561 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988122287 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573893211 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30007823 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 130 # number of nop insts executed -system.cpu.iew.exec_refs 764045166 # number of memory reference insts executed -system.cpu.iew.exec_branches 238330373 # Number of branches executed -system.cpu.iew.exec_stores 190143920 # Number of stores executed -system.cpu.iew.exec_rate 1.921365 # Inst execution rate -system.cpu.iew.wb_sent 1965882705 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957438221 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296419261 # num instructions producing a value -system.cpu.iew.wb_consumers 2061223018 # num instructions consuming a value +system.cpu.iew.exec_nop 128 # number of nop insts executed +system.cpu.iew.exec_refs 764057589 # number of memory reference insts executed +system.cpu.iew.exec_branches 238332739 # Number of branches executed +system.cpu.iew.exec_stores 190164378 # Number of stores executed +system.cpu.iew.exec_rate 1.921313 # Inst execution rate +system.cpu.iew.wb_sent 1965900634 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957455330 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296412413 # num instructions producing a value +system.cpu.iew.wb_consumers 2061187346 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.891716 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.628956 # average fanout of values written-back +system.cpu.iew.wb_rate 1.891677 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.628964 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 478537797 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 478468669 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15221576 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 888731168 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.938802 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.727796 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15218100 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 888690458 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.938891 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.727933 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 401249220 45.15% 45.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192209497 21.63% 66.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72554391 8.16% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35214687 3.96% 78.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19001350 2.14% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30768614 3.46% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20079948 2.26% 86.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11444333 1.29% 88.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106209128 11.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 401243318 45.15% 45.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192174198 21.62% 66.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72553521 8.16% 74.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35226900 3.96% 78.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18988678 2.14% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30770684 3.46% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20065099 2.26% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11431293 1.29% 88.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106236767 11.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 888731168 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 888690458 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -471,70 +471,70 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106209128 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106236767 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2984133091 # The number of ROB reads -system.cpu.rob.rob_writes 4473274350 # The number of ROB writes -system.cpu.timesIdled 1017651 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76107833 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2983995614 # The number of ROB reads +system.cpu.rob.rob_writes 4473124072 # The number of ROB writes +system.cpu.timesIdled 1018062 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76190706 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.669925 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.669925 # CPI: Total CPI of All Threads -system.cpu.ipc 1.492703 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.492703 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956233395 # number of integer regfile reads -system.cpu.int_regfile_writes 1937436072 # number of integer regfile writes -system.cpu.fp_regfile_reads 98 # number of floating regfile reads -system.cpu.fp_regfile_writes 104 # number of floating regfile writes -system.cpu.misc_regfile_reads 737527238 # number of misc regfile reads +system.cpu.cpi 0.669945 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.669945 # CPI: Total CPI of All Threads +system.cpu.ipc 1.492659 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.492659 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956292181 # number of integer regfile reads +system.cpu.int_regfile_writes 1937433329 # number of integer regfile writes +system.cpu.fp_regfile_reads 115 # number of floating regfile reads +system.cpu.fp_regfile_writes 119 # number of floating regfile writes +system.cpu.misc_regfile_reads 737551848 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.icache.replacements 22 # number of replacements -system.cpu.icache.tagsinuse 625.709575 # Cycle average of tags in use -system.cpu.icache.total_refs 288561231 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 370425.200257 # Average number of references to valid blocks. +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.tagsinuse 627.796190 # Cycle average of tags in use +system.cpu.icache.total_refs 288549428 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 783 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 368517.787995 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 625.709575 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.305522 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.305522 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 288561231 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 288561231 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 288561231 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 288561231 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 288561231 # number of overall hits -system.cpu.icache.overall_hits::total 288561231 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 627.796190 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.306541 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.306541 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 288549428 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 288549428 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 288549428 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 288549428 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 288549428 # number of overall hits +system.cpu.icache.overall_hits::total 288549428 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1183 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1183 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1183 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1183 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1183 # number of overall misses system.cpu.icache.overall_misses::total 1183 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 68862000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 68862000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 68862000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 68862000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 68862000 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.184218 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436572 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.436572 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.233916 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.233976 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.233916 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.233976 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60273.809524 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80148.534524 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80137.955277 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85268.415762 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85268.415762 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60273.809524 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82032.807532 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82025.486478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60273.809524 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82032.807532 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82025.486478 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -665,187 +665,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1100731 # number of writebacks -system.cpu.l2cache.writebacks::total 1100731 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1100827 # number of writebacks +system.cpu.l2cache.writebacks::total 1100827 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60228963949 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60228963949 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 36118599 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156391540883 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 156427659482 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36118599 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156391540883 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 156427659482 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184085 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184164 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436562 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436562 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233869 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.233929 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233869 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.233929 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48094.006658 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67758.632500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67748.231996 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72858.822201 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72858.822201 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48094.006658 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48094.006658 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 755 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419496 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1420251 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826656 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 826656 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2246152 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2246907 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2246152 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2246907 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35881848 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96143549144 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96179430992 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60227207126 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60227207126 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35881848 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156370756270 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 156406638118 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35881848 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156370756270 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 156406638118 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964240 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184137 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184216 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436572 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436572 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964240 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233975 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964240 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233975 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47525.626490 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67730.764401 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67720.023427 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72856.432574 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72856.432574 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47525.626490 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69617.174737 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69609.751591 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47525.626490 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69617.174737 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69609.751591 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9598898 # number of replacements -system.cpu.dcache.tagsinuse 4088.019682 # Cycle average of tags in use -system.cpu.dcache.total_refs 656099070 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9602994 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.322345 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9598332 # number of replacements +system.cpu.dcache.tagsinuse 4088.019917 # Cycle average of tags in use +system.cpu.dcache.total_refs 656091291 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9602428 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.325562 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 3440663000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4088.019682 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4088.019917 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.998052 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 489051603 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 489051603 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167047341 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167047341 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 489044261 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489044261 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167046906 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167046906 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656098944 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656098944 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656098944 # number of overall hits -system.cpu.dcache.overall_hits::total 656098944 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11478513 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11478513 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5538706 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5538706 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656091167 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656091167 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656091167 # number of overall hits +system.cpu.dcache.overall_hits::total 656091167 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11476352 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11476352 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5539141 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5539141 # 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number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 552631798218 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 552631798218 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 552631798218 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 552631798218 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500530116 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500530116 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17015493 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17015493 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17015493 # number of overall misses +system.cpu.dcache.overall_misses::total 17015493 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 322799095500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 322799095500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 229643990242 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 229643990242 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 608000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 608000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 552443085742 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 552443085742 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 552443085742 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 552443085742 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500520613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500520613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 66 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 66 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673116163 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673116163 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673116163 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673116163 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032092 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025281 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025281 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025281 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025281 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28139.570735 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28139.570735 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41459.389561 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41459.389561 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 141166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 141166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32474.859624 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32474.859624 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 26343962 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1054966 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1182360 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64552 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.280830 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16.342886 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673106660 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673106660 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673106660 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673106660 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022929 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022929 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032095 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045455 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045455 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025279 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025279 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025279 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025279 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28127.326131 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28127.326131 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41458.412097 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41458.412097 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 202666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 202666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32467.063149 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32467.063149 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32467.063149 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32467.063149 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26333844 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1054452 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1182092 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64550 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.277322 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16.335430 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781695 # number of writebacks -system.cpu.dcache.writebacks::total 3781695 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3769070 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3769070 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645155 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3645155 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3781376 # number of writebacks +system.cpu.dcache.writebacks::total 3781376 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767440 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3767440 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3645625 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7414225 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7414225 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7414225 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7414225 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709443 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7709443 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893551 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893551 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9602994 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9602994 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9602994 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9602994 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186232562000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 186232562000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83589909224 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83589909224 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269822471224 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 269822471224 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269822471224 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 269822471224 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7413065 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7413065 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7413065 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7413065 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708912 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708912 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893516 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893516 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602428 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602428 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602428 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602428 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186208076000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 186208076000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83587939217 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83587939217 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269796015217 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 269796015217 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269796015217 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 269796015217 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015402 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015402 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.014266 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014266 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24156.422455 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24156.422455 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44144.524876 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44144.524876 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24154.910057 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24154.910057 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44144.300453 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44144.300453 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28096.645475 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28096.645475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28096.645475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28096.645475 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |