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authorNilay Vaish <nilay@cs.wisc.edu>2012-12-30 12:45:52 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2012-12-30 12:45:52 -0600
commit1945f9963d95cdd244a4540519f3d9d1b9597767 (patch)
treed5529f750767024c58f00417d2dbb824a89fa9fc /tests/long/se/60.bzip2/ref
parente9fa54de58846a8726b9320d6b10809ff65ccecf (diff)
downloadgem5-1945f9963d95cdd244a4540519f3d9d1b9597767.tar.xz
x86 regressions: stats update due to new x87 instructions
Diffstat (limited to 'tests/long/se/60.bzip2/ref')
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout6
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt60
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini47
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout6
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt70
8 files changed, 102 insertions, 101 deletions
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 66b4a9e4a..3e10b88db 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -68,13 +68,13 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -91,7 +91,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[3]
@@ -129,9 +129,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
index ac4ad20a5..f5691fd64 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
index 7e9cf379d..f8f83dcd3 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atom
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:29:07
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:35:30
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@@ -26,4 +26,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2846007226500 because target called exit()
+Exiting @ tick 2846007227000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 292417104..15cf58882 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.846007 # Number of seconds simulated
-sim_ticks 2846007226500 # Number of ticks simulated
-final_tick 2846007226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 2846007227000 # Number of ticks simulated
+final_tick 2846007227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1027178 # Simulator instruction rate (inst/s)
-host_op_rate 1600436 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 971834142 # Simulator tick rate (ticks/s)
-host_mem_usage 265228 # Number of bytes of host memory used
-host_seconds 2928.49 # Real time elapsed on the host
+host_inst_rate 1003542 # Simulator instruction rate (inst/s)
+host_op_rate 1563610 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 949472024 # Simulator tick rate (ticks/s)
+host_mem_usage 267592 # Number of bytes of host memory used
+host_seconds 2997.46 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
-sim_ops 4686862594 # Number of ops (including micro ops) simulated
+sim_ops 4686862595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5023868343 # Number of bytes read from this memory
system.physmem.bytes_read::total 37129731399 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 1544656790 # Number of bytes written to this memory
-system.physmem.bytes_written::total 1544656790 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory
+system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1239184745 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5252417627 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 438528337 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 438528337 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 11281019513 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 11281019511 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 13046253380 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 11281019513 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 11281019513 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 542745210 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 542745210 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 11281019513 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2307979077 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13588998590 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total 13046253378 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 11281019511 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 11281019511 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 11281019511 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 13588998589 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 5692014454 # number of cpu cycles simulated
+system.cpu.numCycles 5692014455 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081022 # Number of instructions committed
-system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses
+system.cpu.committedOps 4686862595 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4686862525 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4686862523 # number of integer instructions
+system.cpu.num_int_insts 4686862525 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 11915474418 # number of times the integer registers were read
-system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written
+system.cpu.num_int_register_reads 11915474423 # number of times the integer registers were read
+system.cpu.num_int_register_writes 5355771936 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1677713082 # number of memory refs
+system.cpu.num_mem_refs 1677713083 # number of memory refs
system.cpu.num_load_insts 1239184745 # Number of load instructions
-system.cpu.num_store_insts 438528337 # Number of store instructions
+system.cpu.num_store_insts 438528338 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 5692014454 # Number of busy cycles
+system.cpu.num_busy_cycles 5692014455 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index bb8d06fce..514c208bd 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -61,21 +61,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=262144
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -90,7 +91,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[3]
@@ -99,21 +100,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=131072
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -122,7 +124,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -139,30 +141,31 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -172,10 +175,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -185,7 +188,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
+cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
egid=100
env=
errout=cerr
@@ -213,9 +216,9 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
index ac4ad20a5..f5691fd64 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index 9df33af9d..e7934dc80 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:29:08
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:38:11
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@@ -26,4 +26,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 5901048883000 because target called exit()
+Exiting @ tick 5882580525000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index 21fe18ab3..8918bba84 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 5.882581 # Number of seconds simulated
-sim_ticks 5882580524000 # Number of ticks simulated
-final_tick 5882580524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 5882580525000 # Number of ticks simulated
+final_tick 5882580525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 472403 # Simulator instruction rate (inst/s)
-host_op_rate 736047 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 923827707 # Simulator tick rate (ticks/s)
-host_mem_usage 227772 # Number of bytes of host memory used
-host_seconds 6367.62 # Real time elapsed on the host
+host_inst_rate 506721 # Simulator instruction rate (inst/s)
+host_op_rate 789517 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 990939541 # Simulator tick rate (ticks/s)
+host_mem_usage 276172 # Number of bytes of host memory used
+host_seconds 5936.37 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
-sim_ops 4686862594 # Number of ops (including micro ops) simulated
+sim_ops 4686862595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory
system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory
@@ -35,26 +35,26 @@ system.physmem.bw_total::cpu.inst 7344 # To
system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 11765161048 # number of cpu cycles simulated
+system.cpu.numCycles 11765161050 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081022 # Number of instructions committed
-system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses
+system.cpu.committedOps 4686862595 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4686862525 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4686862523 # number of integer instructions
+system.cpu.num_int_insts 4686862525 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 11915474418 # number of times the integer registers were read
-system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written
+system.cpu.num_int_register_reads 11915474423 # number of times the integer registers were read
+system.cpu.num_int_register_writes 5355771936 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1677713082 # number of memory refs
+system.cpu.num_mem_refs 1677713083 # number of memory refs
system.cpu.num_load_insts 1239184745 # Number of load instructions
-system.cpu.num_store_insts 438528337 # Number of store instructions
+system.cpu.num_store_insts 438528338 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 11765161048 # Number of busy cycles
+system.cpu.num_busy_cycles 11765161050 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 10 # number of replacements
@@ -137,21 +137,21 @@ system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9108581 # number of replacements
system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks.
+system.cpu.dcache.total_refs 1668600406 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 58853920000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 58853921000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1668600405 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1668600405 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1668600405 # number of overall hits
-system.cpu.dcache.overall_hits::total 1668600405 # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1668600406 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1668600406 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1668600406 # number of overall hits
+system.cpu.dcache.overall_hits::total 1668600406 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
@@ -170,12 +170,12 @@ system.cpu.dcache.overall_miss_latency::cpu.data 200710756000
system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1677713082 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1677713082 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1677713082 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1677713082 # number of overall (read+write) accesses
+system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1677713083 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1677713083 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1677713083 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1677713083 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
@@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1926197 # number of replacements
-system.cpu.l2cache.tagsinuse 31136.249390 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 31136.249384 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 340768633000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 15396.795539 # Average occupied blocks per requestor
+system.cpu.l2cache.warmup_cycle 340768634000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 15396.795536 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 15713.812836 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 15713.812833 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy