diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
| commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
| tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/long/se/60.bzip2/ref | |
| parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
| download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz | |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/long/se/60.bzip2/ref')
6 files changed, 1898 insertions, 1901 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 0d873282b..9df6e0f0a 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.996063 # Number of seconds simulated -sim_ticks 996062814500 # Number of ticks simulated -final_tick 996062814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.983203 # Number of seconds simulated +sim_ticks 983202553500 # Number of ticks simulated +final_tick 983202553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142352 # Simulator instruction rate (inst/s) -host_op_rate 142352 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 77916645 # Simulator tick rate (ticks/s) -host_mem_usage 219096 # Number of bytes of host memory used -host_seconds 12783.70 # Real time elapsed on the host +host_inst_rate 94547 # Simulator instruction rate (inst/s) +host_op_rate 94547 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51082649 # Simulator tick rate (ticks/s) +host_mem_usage 219392 # Number of bytes of host memory used +host_seconds 19247.29 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137579648 # Number of bytes read from this memory -system.physmem.bytes_read::total 137634624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137579776 # Number of bytes read from this memory +system.physmem.bytes_read::total 137634752 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67105024 # Number of bytes written to this memory -system.physmem.bytes_written::total 67105024 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67105088 # Number of bytes written to this memory +system.physmem.bytes_written::total 67105088 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2149682 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2150541 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048516 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048516 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 138123466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138178659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55193 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55193 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 67370273 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 67370273 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 67370273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 138123466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 205548932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 2149684 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2150543 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048517 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048517 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 55915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 139930247 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139986162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 68251540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 68251540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 68251540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 139930247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 208237702 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444620890 # DTB read hits +system.cpu.dtb.read_hits 444615529 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449517968 # DTB read accesses -system.cpu.dtb.write_hits 160920434 # DTB write hits +system.cpu.dtb.read_accesses 449512607 # DTB read accesses +system.cpu.dtb.write_hits 160920414 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162621738 # DTB write accesses -system.cpu.dtb.data_hits 605541324 # DTB hits +system.cpu.dtb.write_accesses 162621718 # DTB write accesses +system.cpu.dtb.data_hits 605535943 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612139706 # DTB accesses -system.cpu.itb.fetch_hits 232151959 # ITB hits +system.cpu.dtb.data_accesses 612134325 # DTB accesses +system.cpu.itb.fetch_hits 232170189 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232151981 # ITB accesses +system.cpu.itb.fetch_accesses 232170211 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1992125630 # number of cpu cycles simulated +system.cpu.numCycles 1966405108 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 328832264 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 253784019 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 139998376 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 232594122 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 138120343 # Number of BTB hits +system.cpu.branch_predictor.lookups 328916467 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 253806684 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 140065896 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 232656738 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 138122512 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 59.382560 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 175107833 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 153724431 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669698372 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 59.367510 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 175157469 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 153758998 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1669786412 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3045900989 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3045989029 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 236 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651085046 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617993265 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 121277812 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 12122106 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133399918 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81800180 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.988781 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139625100 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 581 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 650997764 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617989099 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 121287494 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 12179944 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133467438 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81732764 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.020127 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139628962 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1749884347 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1746556255 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7972692 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 415154081 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576971549 # Number of cycles cpu stages are processed. -system.cpu.activity 79.160246 # Percentage of cycles cpu is active +system.cpu.timesIdled 7516835 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 389335212 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1577069896 # Number of cycles cpu stages are processed. +system.cpu.activity 80.200661 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.094707 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.080573 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.094707 # CPI: Total CPI of All Threads -system.cpu.ipc 0.913487 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.080573 # CPI: Total CPI of All Threads +system.cpu.ipc 0.925435 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.913487 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 801360547 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190765083 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.773594 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1059717687 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932407943 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.804676 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1018191600 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973934030 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.889187 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1582470698 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409654932 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.563710 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 969332524 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022793106 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.341797 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.925435 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 775560339 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190844769 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.559483 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1034052370 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932352738 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 47.414072 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 992429233 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 973975875 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.530784 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1556696076 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409709032 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.835434 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 943449824 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022955284 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.021594 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 666.783134 # Cycle average of tags in use -system.cpu.icache.total_refs 232150871 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 666.559426 # Cycle average of tags in use +system.cpu.icache.total_refs 232169108 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270257.125728 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270278.356228 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 666.783134 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325578 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325578 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232150871 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232150871 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232150871 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232150871 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232150871 # number of overall hits -system.cpu.icache.overall_hits::total 232150871 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1085 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1085 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1085 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1085 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1085 # number of overall misses -system.cpu.icache.overall_misses::total 1085 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60468000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60468000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60468000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60468000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60468000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60468000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232151956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232151956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232151956 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232151956 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232151956 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232151956 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 666.559426 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325468 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325468 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 232169108 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232169108 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232169108 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232169108 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232169108 # number of overall hits +system.cpu.icache.overall_hits::total 232169108 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1077 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1077 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1077 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1077 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1077 # number of overall misses +system.cpu.icache.overall_misses::total 1077 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58736500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58736500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58736500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58736500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58736500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58736500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232170185 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232170185 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232170185 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232170185 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232170185 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232170185 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55730.875576 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55730.875576 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55730.875576 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55730.875576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55730.875576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55730.875576 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54537.140204 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54537.140204 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54537.140204 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54537.140204 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 114500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 105000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 22900 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 26250 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 226 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 226 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 226 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 226 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 218 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 218 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 218 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 218 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 218 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47379000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47379000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47379000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47379000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47379000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47379000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47121000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47121000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47121000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47121000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47121000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47121000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55155.995343 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55155.995343 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54855.646100 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54855.646100 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54855.646100 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54855.646100 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54855.646100 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54855.646100 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107311 # number of replacements -system.cpu.dcache.tagsinuse 4082.354222 # Cycle average of tags in use -system.cpu.dcache.total_refs 595073825 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111407 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310860 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12655884000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.354222 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996669 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271433 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271433 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157802392 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157802392 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595073825 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595073825 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595073825 # number of overall hits -system.cpu.dcache.overall_hits::total 595073825 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324230 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324230 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2926110 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2926110 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10250340 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10250340 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10250340 # number of overall misses -system.cpu.dcache.overall_misses::total 10250340 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 166497124500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 166497124500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 130098294500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 130098294500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 296595419000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 296595419000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 296595419000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 296595419000 # number of overall miss cycles +system.cpu.dcache.replacements 9107371 # number of replacements +system.cpu.dcache.tagsinuse 4082.143149 # Cycle average of tags in use +system.cpu.dcache.total_refs 595063275 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111467 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.309272 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12675157000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.143149 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996617 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996617 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437271434 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437271434 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 157791841 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157791841 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595063275 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 595063275 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 595063275 # number of overall hits +system.cpu.dcache.overall_hits::total 595063275 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7324229 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7324229 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2936661 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2936661 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 10260890 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10260890 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10260890 # number of overall misses +system.cpu.dcache.overall_misses::total 10260890 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 153812326500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 153812326500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 102755788500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 102755788500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 256568115000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 256568115000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 256568115000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 256568115000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -262,54 +262,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018205 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.018205 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016934 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016934 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016934 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016934 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.372481 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.372481 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44461.176955 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44461.176955 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28935.178638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28935.178638 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 78626000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8150818500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14909 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 208452 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5273.727279 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 39101.656496 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.018271 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21000.480255 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21000.480255 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34990.687893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34990.687893 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25004.469885 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25004.469885 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26428500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7896367000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4352 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 208446 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6072.725184 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 37882.074974 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3389635 # number of writebacks -system.cpu.dcache.writebacks::total 3389635 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101948 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101948 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1036985 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1036985 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1138933 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1138933 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1138933 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1138933 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889125 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889125 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111407 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111407 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111407 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111407 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 140938792000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 140938792000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71755618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71755618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212694410500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212694410500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212694410500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212694410500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3389692 # number of writebacks +system.cpu.dcache.writebacks::total 3389692 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101949 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101949 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1047474 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1047474 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1149423 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1149423 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1149423 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1149423 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889187 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889187 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111467 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111467 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111467 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111467 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137359214000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 137359214000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55152222500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 55152222500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192511436500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 192511436500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 192511436500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 192511436500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -318,149 +318,149 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19514.440450 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19514.440450 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37983.520678 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37983.520678 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19018.815942 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19018.815942 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29193.628000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29193.628000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21128.478707 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21128.478707 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21128.478707 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21128.478707 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2133758 # number of replacements -system.cpu.l2cache.tagsinuse 30551.128505 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8448354 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 30529.573479 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8448408 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2163449 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.905040 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 184403463000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14423.846214 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.322158 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16092.960133 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440181 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001047 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.491118 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.932346 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5860989 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5860989 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3389635 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3389635 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1100736 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1100736 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6961725 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6961725 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6961725 # number of overall hits -system.cpu.l2cache.overall_hits::total 6961725 # number of overall hits +system.cpu.l2cache.avg_refs 3.905065 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 182812071500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14439.033310 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 34.753993 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16055.786176 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440644 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001061 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.489984 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.931689 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5860987 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5860987 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3389692 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3389692 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1100796 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1100796 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6961783 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6961783 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6961783 # number of overall hits +system.cpu.l2cache.overall_hits::total 6961783 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1360852 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1361711 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 788830 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 788830 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1360851 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1361710 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 788833 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 788833 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2149682 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2150541 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2149684 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2150543 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2149682 # number of overall misses -system.cpu.l2cache.overall_misses::total 2150541 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46160000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71427566000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71473726000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42035467500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 42035467500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 46160000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 113463033500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 113509193500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 46160000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 113463033500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 113509193500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 2149684 # number of overall misses +system.cpu.l2cache.overall_misses::total 2150543 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46256500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71433605500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71479862000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42030855000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 42030855000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 46256500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 113464460500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 113510717000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 46256500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 113464460500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 113510717000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7221841 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222700 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3389635 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3389635 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889566 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889566 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221838 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222697 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3389692 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3389692 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889629 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889629 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111407 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112266 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111467 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112326 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111407 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112266 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111467 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112326 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188436 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.188532 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417466 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.417466 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417454 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.417454 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.235933 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.236005 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.235932 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.236004 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.235933 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.236005 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53736.903376 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52487.387313 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52488.175538 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53288.373287 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53288.373287 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52781.310678 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52781.692374 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.310678 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52781.692374 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 3730000 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.235932 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.236004 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53849.243306 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52491.863915 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52492.720183 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53282.323382 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53282.323382 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52782.351713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52782.351713 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 540500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 142 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 26267.605634 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 12869.047619 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1048516 # number of writebacks -system.cpu.l2cache.writebacks::total 1048516 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1048517 # number of writebacks +system.cpu.l2cache.writebacks::total 1048517 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360852 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1361711 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788830 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 788830 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360851 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1361710 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788833 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 788833 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2149682 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2150541 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2149684 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2150543 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2149682 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2150541 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35698000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54782223000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54817921000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32465310500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32465310500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35698000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87247533500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 87283231500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35698000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87247533500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 87283231500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 2149684 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2150543 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35788000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54811327000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54847115000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32423383500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32423383500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35788000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87234710500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87270498500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35788000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87234710500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87270498500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417466 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417454 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417454 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235933 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.236005 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235933 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.236005 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41557.625146 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40255.827232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40256.648437 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41156.282723 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41156.282723 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41662.398137 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40277.243431 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40278.117220 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41102.975535 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41102.975535 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41662.398137 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40580.248306 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40580.680554 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41662.398137 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40580.248306 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40580.680554 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 693f470b9..b5afab091 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.621337 # Number of seconds simulated -sim_ticks 621337354500 # Number of ticks simulated -final_tick 621337354500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.601884 # Number of seconds simulated +sim_ticks 601884201500 # Number of ticks simulated +final_tick 601884201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185902 # Simulator instruction rate (inst/s) -host_op_rate 185902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66535120 # Simulator tick rate (ticks/s) -host_mem_usage 220128 # Number of bytes of host memory used -host_seconds 9338.49 # Real time elapsed on the host +host_inst_rate 130981 # Simulator instruction rate (inst/s) +host_op_rate 130981 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45411041 # Simulator tick rate (ticks/s) +host_mem_usage 220420 # Number of bytes of host memory used +host_seconds 13254.14 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 62208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138182080 # Number of bytes read from this memory -system.physmem.bytes_read::total 138244288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67208384 # Number of bytes written to this memory -system.physmem.bytes_written::total 67208384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 972 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2159095 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2160067 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050131 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050131 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 100120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 222394612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 222494732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 100120 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100120 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 108167300 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 108167300 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 108167300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 100120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 222394612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 330662032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138169152 # Number of bytes read from this memory +system.physmem.bytes_read::total 138230976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67208000 # Number of bytes written to this memory +system.physmem.bytes_written::total 67208000 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2158893 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2159859 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050125 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050125 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 102717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 229561021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 229663739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 102717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 102717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 111662675 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 111662675 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 111662675 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 102717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 229561021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 341326414 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 614254083 # DTB read hits -system.cpu.dtb.read_misses 10995703 # DTB read misses +system.cpu.dtb.read_hits 610881152 # DTB read hits +system.cpu.dtb.read_misses 10794363 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625249786 # DTB read accesses -system.cpu.dtb.write_hits 208699163 # DTB write hits -system.cpu.dtb.write_misses 6860235 # DTB write misses +system.cpu.dtb.read_accesses 621675515 # DTB read accesses +system.cpu.dtb.write_hits 207421516 # DTB write hits +system.cpu.dtb.write_misses 6613595 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 215559398 # DTB write accesses -system.cpu.dtb.data_hits 822953246 # DTB hits -system.cpu.dtb.data_misses 17855938 # DTB misses +system.cpu.dtb.write_accesses 214035111 # DTB write accesses +system.cpu.dtb.data_hits 818302668 # DTB hits +system.cpu.dtb.data_misses 17407958 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 840809184 # DTB accesses -system.cpu.itb.fetch_hits 402673269 # ITB hits -system.cpu.itb.fetch_misses 61 # ITB misses +system.cpu.dtb.data_accesses 835710626 # DTB accesses +system.cpu.itb.fetch_hits 399285601 # ITB hits +system.cpu.itb.fetch_misses 63 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 402673330 # ITB accesses +system.cpu.itb.fetch_accesses 399285664 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,245 +67,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1242674710 # number of cpu cycles simulated +system.cpu.numCycles 1203768404 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 383387811 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 295251517 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19004234 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 268604084 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 264111879 # Number of BTB hits +system.cpu.BPredUnit.lookups 378661928 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 290874773 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18850616 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 264881962 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 260540807 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25192938 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6291 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 414146940 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3172273422 # Number of instructions fetch has processed -system.cpu.fetch.Branches 383387811 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 289304817 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 579090604 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 137696439 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133107618 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1380 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 402673269 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10484478 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1238186640 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.562032 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.158458 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25136701 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6159 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 410735894 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3138932224 # Number of instructions fetch has processed +system.cpu.fetch.Branches 378661928 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 285677508 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 572729793 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 132567804 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 108566970 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1302 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 399285601 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10259418 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1199047347 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.617855 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.169243 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 659096036 53.23% 53.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43594264 3.52% 56.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22394894 1.81% 58.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 41029945 3.31% 61.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 127979061 10.34% 72.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63938505 5.16% 77.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40814246 3.30% 80.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30412222 2.46% 83.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 208927467 16.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 626317554 52.23% 52.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42572057 3.55% 55.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22209930 1.85% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40806426 3.40% 61.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 126340363 10.54% 71.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63640386 5.31% 76.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40565082 3.38% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30197237 2.52% 82.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 206398312 17.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1238186640 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.308518 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.552779 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 444874368 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 117661314 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 546409633 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17402131 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 111839194 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60535765 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 960 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3092199728 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2107 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 111839194 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 466426212 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 65454708 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5539 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 540814331 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53646656 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3009948527 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 590628 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2809331 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 47992017 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2251177447 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3888711604 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3887318453 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1393151 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1199047347 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.314564 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.607588 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438876145 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95310008 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542739947 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15108786 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 107012461 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 60159953 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 978 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3060008107 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2177 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 107012461 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 459450274 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50562010 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5044 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 536182540 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45835018 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2978218339 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 422353 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1724352 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 41499068 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2227532255 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3846059420 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3844664884 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1394536 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 874974484 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 208 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 207 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112977902 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679363507 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 252361148 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 62396219 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36704407 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2703896552 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 180 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2499071963 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3469199 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 959964040 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 407445563 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 151 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1238186640 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.018332 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.960312 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 851329292 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 212 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 95534350 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 674543157 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 250165929 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 60031674 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 34641501 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2674307937 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2477606155 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3178446 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 927538702 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 394492556 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1199047347 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.066312 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.969260 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 396950099 32.06% 32.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203265879 16.42% 48.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185984424 15.02% 63.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153264847 12.38% 75.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 136492690 11.02% 86.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79936535 6.46% 93.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 62863067 5.08% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14221934 1.15% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5207165 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 374590988 31.24% 31.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 190702947 15.90% 47.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 181537142 15.14% 62.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153695699 12.82% 75.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 136730734 11.40% 86.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80190081 6.69% 93.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 61698536 5.15% 98.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14532490 1.21% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5368730 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1238186640 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1199047347 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1904668 10.20% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12253005 65.59% 75.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4524321 24.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2248592 11.88% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12188219 64.39% 76.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4492341 23.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1633622343 65.37% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 285 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 166 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 37 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 642829515 25.72% 91.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 222619482 8.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1617099394 65.27% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 161 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 639262195 25.80% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 221243949 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2499071963 # Type of FU issued -system.cpu.iq.rate 2.011043 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18681994 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007476 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6256498920 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3662616880 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2395384352 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1982839 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1348326 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 869815 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2516779289 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 974668 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57504336 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2477606155 # Type of FU issued +system.cpu.iq.rate 2.058208 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18929152 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007640 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6174384179 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3600600502 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2375948293 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1983076 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1349305 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 869249 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2495560681 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 974626 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 56273066 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234767844 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 254077 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 105937 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 91632646 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 229947494 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 250240 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 104617 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 89437427 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 220 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 267187 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 223 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 81293 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 111839194 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23661056 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1167024 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2847195647 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17872608 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679363507 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 252361148 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 180 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 266250 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15108 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 105937 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13288388 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8880688 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22169076 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2446901289 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625251329 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 52170674 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 107012461 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18493719 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 964338 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2816222496 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17539215 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 674543157 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 250165929 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 222443 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13054 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 104617 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13266110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8853005 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22119115 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2426782897 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 621677051 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 50823258 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 143298915 # number of nop insts executed -system.cpu.iew.exec_refs 840810767 # number of memory reference insts executed -system.cpu.iew.exec_branches 299911480 # Number of branches executed -system.cpu.iew.exec_stores 215559438 # Number of stores executed -system.cpu.iew.exec_rate 1.969060 # Inst execution rate -system.cpu.iew.wb_sent 2424991603 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2396254167 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1371180261 # num instructions producing a value -system.cpu.iew.wb_consumers 1736709964 # num instructions consuming a value +system.cpu.iew.exec_nop 141914378 # number of nop insts executed +system.cpu.iew.exec_refs 835712197 # number of memory reference insts executed +system.cpu.iew.exec_branches 297017404 # Number of branches executed +system.cpu.iew.exec_stores 214035146 # Number of stores executed +system.cpu.iew.exec_rate 2.015988 # Inst execution rate +system.cpu.iew.wb_sent 2405357276 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2376817542 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1361466858 # num instructions producing a value +system.cpu.iew.wb_consumers 1724557006 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.928304 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789527 # average fanout of values written-back +system.cpu.iew.wb_rate 1.974481 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789459 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 793091861 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 756599351 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19003362 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1126347446 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.615647 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.496030 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 18849719 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1092034886 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.666412 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.514594 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 601147369 53.37% 53.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181479999 16.11% 69.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90892282 8.07% 77.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53587955 4.76% 82.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36442488 3.24% 85.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28128451 2.50% 88.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22594945 2.01% 90.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22821835 2.03% 92.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 89252122 7.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 565812226 51.81% 51.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 181963708 16.66% 68.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 91431923 8.37% 76.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53287438 4.88% 81.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36685843 3.36% 85.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28834990 2.64% 87.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22491649 2.06% 89.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22994830 2.11% 91.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 88532279 8.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1126347446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1092034886 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 89252122 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 88532279 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3564188111 # The number of ROB reads -system.cpu.rob.rob_writes 5337700893 # The number of ROB writes -system.cpu.timesIdled 386272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4488070 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3494102884 # The number of ROB reads +system.cpu.rob.rob_writes 5259875951 # The number of ROB writes +system.cpu.timesIdled 272602 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4721057 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.715808 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.715808 # CPI: Total CPI of All Threads -system.cpu.ipc 1.397022 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.397022 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3289961218 # number of integer regfile reads -system.cpu.int_regfile_writes 1921862672 # number of integer regfile writes -system.cpu.fp_regfile_reads 50916 # number of floating regfile reads -system.cpu.fp_regfile_writes 565 # number of floating regfile writes +system.cpu.cpi 0.693397 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.693397 # CPI: Total CPI of All Threads +system.cpu.ipc 1.442174 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.442174 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3262431101 # number of integer regfile reads +system.cpu.int_regfile_writes 1906790236 # number of integer regfile writes +system.cpu.fp_regfile_reads 51143 # number of floating regfile reads +system.cpu.fp_regfile_writes 554 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 773.343215 # Cycle average of tags in use -system.cpu.icache.total_refs 402671818 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 972 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 414271.417695 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 770.355491 # Cycle average of tags in use +system.cpu.icache.total_refs 399284112 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 966 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 413337.590062 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 773.343215 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.377609 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.377609 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 402671818 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 402671818 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 402671818 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 402671818 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 402671818 # number of overall hits -system.cpu.icache.overall_hits::total 402671818 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1451 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1451 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1451 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1451 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1451 # number of overall misses -system.cpu.icache.overall_misses::total 1451 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 52415500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 52415500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 52415500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 52415500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 52415500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 52415500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 402673269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 402673269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 402673269 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 402673269 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 402673269 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 402673269 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 770.355491 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.376150 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.376150 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 399284112 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 399284112 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 399284112 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 399284112 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 399284112 # number of overall hits +system.cpu.icache.overall_hits::total 399284112 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1489 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1489 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1489 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1489 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1489 # number of overall misses +system.cpu.icache.overall_misses::total 1489 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51254000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51254000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51254000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51254000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51254000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51254000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 399285601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 399285601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 399285601 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 399285601 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 399285601 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 399285601 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36123.707788 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36123.707788 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36123.707788 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36123.707788 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36123.707788 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36123.707788 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34421.759570 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34421.759570 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34421.759570 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34421.759570 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34421.759570 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34421.759570 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,301 +388,299 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 479 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 479 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 479 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 479 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 479 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 479 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 972 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 972 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 972 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 972 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 972 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 972 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36902500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36902500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36902500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36902500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36902500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36902500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 523 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 523 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 523 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 523 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 523 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 523 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36312000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36312000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36312000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36312000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36312000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36312000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37965.534979 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37965.534979 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37965.534979 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37965.534979 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37965.534979 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37965.534979 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37590.062112 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37590.062112 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37590.062112 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37590.062112 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37590.062112 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37590.062112 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9177741 # number of replacements -system.cpu.dcache.tagsinuse 4086.022558 # Cycle average of tags in use -system.cpu.dcache.total_refs 702049039 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9181837 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.460630 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5710472000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.022558 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997564 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997564 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 546225954 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 546225954 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155823082 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155823082 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 702049036 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 702049036 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 702049036 # number of overall hits -system.cpu.dcache.overall_hits::total 702049036 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10364055 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10364055 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4905420 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4905420 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15269475 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15269475 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15269475 # number of overall misses -system.cpu.dcache.overall_misses::total 15269475 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 211607642000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 211607642000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 166442600009 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 166442600009 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 65000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 65000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 378050242009 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 378050242009 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 378050242009 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 378050242009 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 556590009 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 556590009 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 9176158 # number of replacements +system.cpu.dcache.tagsinuse 4085.718246 # Cycle average of tags in use +system.cpu.dcache.total_refs 700542179 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180254 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 76.309673 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5701764000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4085.718246 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997490 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997490 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 544702732 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 544702732 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155839442 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155839442 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 700542174 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 700542174 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 700542174 # number of overall hits +system.cpu.dcache.overall_hits::total 700542174 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9892344 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9892344 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4889060 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4889060 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 14781404 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 14781404 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 14781404 # number of overall misses +system.cpu.dcache.overall_misses::total 14781404 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 135375372000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 135375372000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128493017298 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128493017298 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 42500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 42500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 263868389298 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 263868389298 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 263868389298 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 263868389298 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 554595076 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 554595076 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 717318511 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 717318511 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 717318511 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 717318511 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018621 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.018621 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030520 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.030520 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.400000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.400000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021287 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021287 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021287 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021287 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20417.456488 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20417.456488 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33930.346435 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33930.346435 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24758.561903 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24758.561903 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24758.561903 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24758.561903 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 705064541 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1696790500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 102448 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65121 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6882.169891 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26055.965050 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 715323578 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 715323578 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 715323578 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 715323578 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017837 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017837 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030418 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.030418 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.020664 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.020664 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.020664 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.020664 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13684.862961 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13684.862961 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26281.742768 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26281.742768 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 42500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 42500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17851.375235 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17851.375235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17851.375235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17851.375235 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 54186258 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2148410500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 10025 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65117 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5405.113017 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 32993.081684 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3417249 # number of writebacks -system.cpu.dcache.writebacks::total 3417249 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3065881 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3065881 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3021758 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3021758 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6087639 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6087639 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6087639 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6087639 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7298174 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7298174 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883662 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883662 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3416507 # number of writebacks +system.cpu.dcache.writebacks::total 3416507 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2595838 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2595838 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3005313 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3005313 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 5601151 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5601151 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5601151 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5601151 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296506 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296506 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883747 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883747 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9181836 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9181836 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9181836 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9181836 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97342451000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 97342451000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53846535513 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53846535513 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180253 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180253 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180253 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180253 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63651885000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 63651885000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 32596175026 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 32596175026 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 40500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 40500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151188986513 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151188986513 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151188986513 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151188986513 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013112 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96248060026 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 96248060026 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96248060026 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 96248060026 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013156 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012800 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012800 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012800 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012800 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.918636 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.918636 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28586.092151 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28586.092151 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012834 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012834 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012834 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012834 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8723.611685 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8723.611685 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17303.902820 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17303.902820 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 40500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 40500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16466.095290 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16466.095290 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16466.095290 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16466.095290 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10484.249184 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10484.249184 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10484.249184 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10484.249184 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2143649 # number of replacements -system.cpu.l2cache.tagsinuse 30911.087928 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8542511 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2173346 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.930580 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 109479230000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14438.028494 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 30.254344 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16442.805090 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440614 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.501795 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.943332 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5921437 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5921437 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3417249 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3417249 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1101305 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1101305 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7022742 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7022742 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7022742 # number of overall hits -system.cpu.l2cache.overall_hits::total 7022742 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 972 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1376729 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1377701 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 782366 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 782366 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 972 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2159095 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2160067 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 972 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2159095 # number of overall misses -system.cpu.l2cache.overall_misses::total 2160067 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35546500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49106471000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 49142017500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 28462549794 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 28462549794 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35546500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 77569020794 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 77604567294 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35546500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 77569020794 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 77604567294 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 972 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7298166 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7299138 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3417249 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3417249 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883671 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883671 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 972 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9181837 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9182809 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 972 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9181837 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9182809 # number of overall (read+write) accesses +system.cpu.l2cache.replacements 2143403 # number of replacements +system.cpu.l2cache.tagsinuse 30886.044156 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8540338 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2173098 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.930029 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 106236291500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14425.723577 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 30.926005 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16429.394573 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440238 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000944 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.501385 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.942567 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5920206 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5920206 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3416507 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3416507 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1101155 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1101155 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7021361 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7021361 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7021361 # number of overall hits +system.cpu.l2cache.overall_hits::total 7021361 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 966 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1376292 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1377258 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 782601 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 782601 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 966 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2158893 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2159859 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 966 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2158893 # number of overall misses +system.cpu.l2cache.overall_misses::total 2159859 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35332000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49455599500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 49490931500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 28985235156 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 28985235156 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35332000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 78440834656 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 78476166656 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35332000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 78440834656 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 78476166656 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 966 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7296498 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7297464 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3416507 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3416507 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883756 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883756 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 966 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180254 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181220 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 966 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180254 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181220 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188640 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.188748 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415341 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.415341 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188624 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.188731 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415447 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.415447 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.235148 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.235229 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.235167 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.235247 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.235148 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.235229 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36570.473251 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35668.945014 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35669.581063 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36380.095498 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36380.095498 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36570.473251 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35926.636296 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 35926.926014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36570.473251 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35926.636296 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 35926.926014 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 7260431 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.235167 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.235247 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36575.569358 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35933.943887 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35934.393919 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37037.053564 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37037.053564 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36575.569358 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36333.822314 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36333.930435 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36575.569358 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36333.822314 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36333.930435 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 23861689 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 813 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 3922 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8930.419434 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6084.061448 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050131 # number of writebacks -system.cpu.l2cache.writebacks::total 1050131 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 972 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376729 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1377701 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782366 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782366 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 972 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2159095 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2160067 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 972 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2159095 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2160067 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32474500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44762602000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44795076500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26015406452 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26015406452 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32474500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 70778008452 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 70810482952 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32474500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 70778008452 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 70810482952 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1050125 # number of writebacks +system.cpu.l2cache.writebacks::total 1050125 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376292 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1377258 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782601 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782601 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2158893 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2159859 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2158893 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2159859 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32266500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 45051953000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 45084219500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26472928656 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26472928656 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32266500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 71524881656 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 71557148156 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32266500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 71524881656 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 71557148156 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188640 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188748 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415341 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415341 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188624 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188731 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415447 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415447 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235148 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235229 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235167 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.235247 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235148 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.235229 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33409.979424 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32513.735092 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32514.367414 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33252.220127 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33252.220127 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33409.979424 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32781.331276 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32781.614159 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33409.979424 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32781.331276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32781.614159 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235167 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.235247 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33402.173913 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32734.298390 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32734.766834 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33826.852580 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33826.852580 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33402.173913 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33130.350442 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33130.472015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33402.173913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33130.350442 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33130.472015 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 15b5a360c..78e7b43f1 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.642008 # Number of seconds simulated -sim_ticks 2642007987000 # Number of ticks simulated -final_tick 2642007987000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.631385 # Number of seconds simulated +sim_ticks 2631384990000 # Number of ticks simulated +final_tick 2631384990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1913242 # Simulator instruction rate (inst/s) -host_op_rate 1913242 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2777698581 # Simulator tick rate (ticks/s) -host_mem_usage 217920 # Number of bytes of host memory used -host_seconds 951.15 # Real time elapsed on the host +host_inst_rate 1011793 # Simulator instruction rate (inst/s) +host_op_rate 1011793 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1463043658 # Simulator tick rate (ticks/s) +host_mem_usage 219388 # Number of bytes of host memory used +host_seconds 1798.57 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 2149692 # Nu system.physmem.num_reads::total 2150494 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1048525 # Number of write requests responded to by this memory system.physmem.num_writes::total 1048525 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52074138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52093565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19428 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19428 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 25399469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 25399469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 25399469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52074138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77493034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 19506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52284363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52303869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19506 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19506 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 25502008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 25502008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 25502008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52284363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77805877 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5284015974 # number of cpu cycles simulated +system.cpu.numCycles 5262769980 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5284015974 # Number of busy cycles +system.cpu.num_busy_cycles 5262769980 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 612.519467 # Cycle average of tags in use +system.cpu.icache.tagsinuse 612.470356 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 612.519467 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.299082 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.299082 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 612.470356 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.299058 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.299058 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45149000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45149000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45149000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45149000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45149000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45149000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44120000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44120000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44120000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44120000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44120000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44120000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56295.511222 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56295.511222 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56295.511222 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56295.511222 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56295.511222 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56295.511222 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55012.468828 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55012.468828 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55012.468828 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55012.468828 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42743000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42743000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42743000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42743000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42743000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42743000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42516000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42516000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53295.511222 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53295.511222 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53295.511222 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53295.511222 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53295.511222 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53295.511222 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53012.468828 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53012.468828 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.tagsinuse 4079.366966 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.313701 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40989979000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4079.366966 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995939 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995939 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 40977019000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4079.313701 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995926 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995926 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 158759423000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 158759423000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 59584620000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 59584620000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 218344043000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 218344043000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 218344043000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 218344043000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151059345000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151059345000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57691387000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57691387000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 208750732000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 208750732000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 208750732000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 208750732000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21981.490261 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21981.490261 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31537.600830 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31537.600830 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23962.951838 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23962.951838 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23962.951838 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23962.951838 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20915.353925 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20915.353925 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30535.529714 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30535.529714 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22910.099439 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22910.099439 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22910.099439 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22910.099439 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137092181000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 137092181000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53916660000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53916660000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191008841000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191008841000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191008841000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191008841000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136614517000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 136614517000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53912747000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53912747000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190527264000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 190527264000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190527264000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 190527264000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18981.490261 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18981.490261 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28537.600830 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28537.600830 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20962.951838 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20962.951838 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20962.951838 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20962.951838 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18915.353925 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18915.353925 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28535.529714 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.529714 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20910.099439 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20910.099439 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20910.099439 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20910.099439 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2133721 # number of replacements -system.cpu.l2cache.tagsinuse 30166.534681 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30159.988647 # Cycle average of tags in use system.cpu.l2cache.total_refs 8449191 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2163414 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 3.905490 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 498438853000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14372.614424 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 37.649566 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15756.270691 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.438617 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001149 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.480843 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.920610 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 496965874000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14375.657027 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 37.778500 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15746.553119 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.438710 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001153 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.480547 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.920410 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 5861531 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5861531 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3389919 # number of Writeback hits @@ -301,17 +301,17 @@ system.cpu.l2cache.demand_misses::total 2150494 # nu system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2149692 # number of overall misses system.cpu.l2cache.overall_misses::total 2150494 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41704000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70765916000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 70807620000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41018068000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41018068000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 41704000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111783984000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 111825688000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 41704000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111783984000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 111825688000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41714000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70776793000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 70818507000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41018317000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41018317000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 41714000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 111795110000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 111836824000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 41714000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 111795110000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 111836824000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses) @@ -336,17 +336,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.235993 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.235926 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.235993 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52012.468828 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.992605 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52007.995241 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.315666 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.315666 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52012.468828 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.175625 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52005.178345 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52012.468828 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.175625 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52005.178345 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -368,17 +368,17 @@ system.cpu.l2cache.demand_mshr_misses::total 2150494 system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2149692 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2150494 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54435320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54467400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31552360000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31552360000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85987680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 86019760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85987680000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86019760000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32090000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54446197000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54478287000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31552609000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31552609000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32090000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85998806000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 86030896000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32090000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85998806000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 86030896000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188425 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188515 # mshr miss rate for ReadReq accesses @@ -390,17 +390,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.235993 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.235993 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40012.468828 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.992605 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40007.995241 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.315666 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.315666 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40012.468828 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.175625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.178345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40012.468828 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.175625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.178345 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 14d5fad91..620901a70 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.479173 # Number of seconds simulated -sim_ticks 479173106500 # Number of ticks simulated -final_tick 479173106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.454220 # Number of seconds simulated +sim_ticks 454219906500 # Number of ticks simulated +final_tick 454219906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135351 # Simulator instruction rate (inst/s) -host_op_rate 150994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41990206 # Simulator tick rate (ticks/s) -host_mem_usage 229432 # Number of bytes of host memory used -host_seconds 11411.54 # Real time elapsed on the host -sim_insts 1544563038 # Number of instructions simulated -sim_ops 1723073850 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156363136 # Number of bytes read from this memory -system.physmem.bytes_read::total 156411648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71949056 # Number of bytes written to this memory -system.physmem.bytes_written::total 71949056 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2443174 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2443932 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1124204 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1124204 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 101241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 326318681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 326419922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 101241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 101241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 150152534 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 150152534 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 150152534 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 101241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 326318681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 476572456 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 138720 # Simulator instruction rate (inst/s) +host_op_rate 154753 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40794382 # Simulator tick rate (ticks/s) +host_mem_usage 234840 # Number of bytes of host memory used +host_seconds 11134.37 # Real time elapsed on the host +sim_insts 1544563043 # Number of instructions simulated +sim_ops 1723073855 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 47808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156313408 # Number of bytes read from this memory +system.physmem.bytes_read::total 156361216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71943232 # Number of bytes written to this memory +system.physmem.bytes_written::total 71943232 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 747 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2442397 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2443144 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1124113 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1124113 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 105253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 344135970 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 344241223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 105253 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 105253 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 158388549 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 158388549 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 158388549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 105253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 344135970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 502629772 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,320 +77,319 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 958346214 # number of cpu cycles simulated +system.cpu.numCycles 908439814 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 302436824 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 248070487 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16102737 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 165612861 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 157810575 # Number of BTB hits +system.cpu.BPredUnit.lookups 299293350 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 245165786 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16042294 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 167415927 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155291115 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18381050 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 257 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 295095953 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2169970618 # Number of instructions fetch has processed -system.cpu.fetch.Branches 302436824 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 176191625 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 431629876 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 85633501 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 155381037 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 18349808 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 218 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 291155231 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2147464853 # Number of instructions fetch has processed +system.cpu.fetch.Branches 299293350 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 173640923 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 427083963 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 82022952 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 117971766 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 95 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 285890160 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5533233 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 950851132 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.536857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.220630 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 81 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 282205512 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5329978 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 901954385 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.649183 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.246512 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 519221373 54.61% 54.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23554787 2.48% 57.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38911325 4.09% 61.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47909996 5.04% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 41216698 4.33% 70.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 47160592 4.96% 75.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39133251 4.12% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18348533 1.93% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175394577 18.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 474870538 52.65% 52.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 22740626 2.52% 55.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38702218 4.29% 59.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47644255 5.28% 64.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40322718 4.47% 69.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46782649 5.19% 74.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38980366 4.32% 78.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18009770 2.00% 80.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 173901245 19.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 950851132 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.315582 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.264287 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 327095784 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 132835494 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 402923516 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19252859 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68743479 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46256582 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 721 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2358824481 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2518 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68743479 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 349861256 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 63822770 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14217 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 397782583 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70626827 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2300352404 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 28571 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5556438 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56486754 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 21 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2275431187 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10618596825 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10618592524 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4301 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319954 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 569111233 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1538 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1535 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 155721257 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 627567306 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 219602180 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 87405609 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68407559 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2199673736 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1543 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2020179794 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4995947 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 472270317 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1103060101 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1370 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 950851132 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.124602 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.914321 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 901954385 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.329459 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.363904 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 319244517 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 99044104 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 402843645 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15079439 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 65742680 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46017167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 685 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2336575701 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2448 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 65742680 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 340277658 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 45082178 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13877 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 395714637 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55123355 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2280505483 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18602 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4635517 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42073464 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2255238182 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10526656383 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10526652098 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4285 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 548918220 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1694 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1690 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 127506095 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 622196847 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 217942695 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85227601 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 65382931 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2181344295 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1719 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2010119502 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4796816 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 454085036 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1056260113 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1545 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 901954385 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.228627 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.927984 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 272421375 28.65% 28.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 149099949 15.68% 44.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161022280 16.93% 61.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 117844218 12.39% 73.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124393177 13.08% 86.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 74467059 7.83% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38344308 4.03% 98.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10541348 1.11% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2717418 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 241738453 26.80% 26.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 133353594 14.78% 41.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 156367006 17.34% 58.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 115954647 12.86% 71.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125581942 13.92% 85.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75899476 8.42% 94.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39722592 4.40% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10686145 1.18% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2650530 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 950851132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 901954385 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 857125 3.43% 3.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4796 0.02% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18987474 76.03% 79.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5123425 20.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 695241 2.77% 2.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4797 0.02% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19085015 76.16% 78.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5273410 21.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236499214 61.21% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 932103 0.05% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 78 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 35 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 18 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 588851338 29.15% 90.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193897003 9.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1230459115 61.21% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 930103 0.05% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 33 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 585119298 29.11% 90.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193610861 9.63% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2020179794 # Type of FU issued -system.cpu.iq.rate 2.107985 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24972820 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012362 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5021178993 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2672131610 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1961102368 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 494 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 800 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 185 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2045152363 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 251 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63608304 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2010119502 # Type of FU issued +system.cpu.iq.rate 2.212716 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25058463 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012466 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4952048213 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2635615257 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1952750313 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 455 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 782 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2035177734 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63595770 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 141640534 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 283255 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189454 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 44755132 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 136270074 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 285522 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 187812 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 43095646 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1142386 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 118212 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68743479 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28058898 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1485147 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2199675446 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5559671 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 627567306 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 219602180 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1479 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 343072 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56281 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189454 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8595611 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10221674 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18817285 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1990434220 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574229120 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29745574 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 65742680 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 20161039 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1080033 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2181346094 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5536242 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 622196847 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 217942695 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1653 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 177278 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 42353 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 187812 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8595145 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10187661 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18782806 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1980860321 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 570725685 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29259181 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 167 # number of nop insts executed -system.cpu.iew.exec_refs 765174747 # number of memory reference insts executed -system.cpu.iew.exec_branches 238396251 # Number of branches executed -system.cpu.iew.exec_stores 190945627 # Number of stores executed -system.cpu.iew.exec_rate 2.076947 # Inst execution rate -system.cpu.iew.wb_sent 1969970289 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1961102553 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296676707 # num instructions producing a value -system.cpu.iew.wb_consumers 2069059836 # num instructions consuming a value +system.cpu.iew.exec_nop 80 # number of nop insts executed +system.cpu.iew.exec_refs 761335906 # number of memory reference insts executed +system.cpu.iew.exec_branches 237528825 # Number of branches executed +system.cpu.iew.exec_stores 190610221 # Number of stores executed +system.cpu.iew.exec_rate 2.180508 # Inst execution rate +system.cpu.iew.wb_sent 1961779173 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1952750482 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1293463699 # num instructions producing a value +system.cpu.iew.wb_consumers 2065510739 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.046340 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626699 # average fanout of values written-back +system.cpu.iew.wb_rate 2.149565 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626220 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 476677558 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 173 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16102047 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 882107654 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.953360 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.727618 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 458335863 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16041632 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 836211706 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.060571 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.763665 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 391464028 44.38% 44.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 194903618 22.10% 66.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73864004 8.37% 74.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35187525 3.99% 78.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19179450 2.17% 81.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30712235 3.48% 84.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19231414 2.18% 86.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11310832 1.28% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106254548 12.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 346444317 41.43% 41.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193987468 23.20% 64.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73877669 8.83% 73.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35342489 4.23% 77.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18524109 2.22% 79.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30984795 3.71% 83.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19692342 2.35% 85.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10738999 1.28% 87.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106619518 12.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 882107654 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563056 # Number of instructions committed -system.cpu.commit.committedOps 1723073868 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 836211706 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563061 # Number of instructions committed +system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773820 # Number of memory references committed -system.cpu.commit.loads 485926772 # Number of loads committed +system.cpu.commit.refs 660773822 # Number of memory references committed +system.cpu.commit.loads 485926773 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462429 # Number of branches committed +system.cpu.commit.branches 213462430 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106254548 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106619518 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2975603933 # The number of ROB reads -system.cpu.rob.rob_writes 4468410288 # The number of ROB writes -system.cpu.timesIdled 802202 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7495082 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563038 # Number of Instructions Simulated -system.cpu.committedOps 1723073850 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563038 # Number of Instructions Simulated -system.cpu.cpi 0.620464 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.620464 # CPI: Total CPI of All Threads -system.cpu.ipc 1.611696 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.611696 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9970442228 # number of integer regfile reads -system.cpu.int_regfile_writes 1940974329 # number of integer regfile writes -system.cpu.fp_regfile_reads 200 # number of floating regfile reads -system.cpu.fp_regfile_writes 218 # number of floating regfile writes -system.cpu.misc_regfile_reads 2910515379 # number of misc regfile reads -system.cpu.misc_regfile_writes 130 # number of misc regfile writes -system.cpu.icache.replacements 28 # number of replacements -system.cpu.icache.tagsinuse 630.233308 # Cycle average of tags in use -system.cpu.icache.total_refs 285889001 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 361427.308470 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2911001325 # The number of ROB reads +system.cpu.rob.rob_writes 4428720797 # The number of ROB writes +system.cpu.timesIdled 678798 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6485429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563043 # Number of Instructions Simulated +system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated +system.cpu.cpi 0.588153 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.588153 # CPI: Total CPI of All Threads +system.cpu.ipc 1.700237 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.700237 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9924440864 # number of integer regfile reads +system.cpu.int_regfile_writes 1932829114 # number of integer regfile writes +system.cpu.fp_regfile_reads 176 # number of floating regfile reads +system.cpu.fp_regfile_writes 197 # number of floating regfile writes +system.cpu.misc_regfile_reads 2885564305 # number of misc regfile reads +system.cpu.misc_regfile_writes 132 # number of misc regfile writes +system.cpu.icache.replacements 18 # number of replacements +system.cpu.icache.tagsinuse 627.769502 # Cycle average of tags in use +system.cpu.icache.total_refs 282204371 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 777 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 363197.388674 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 630.233308 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.307731 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.307731 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 285889001 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 285889001 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 285889001 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 285889001 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 285889001 # number of overall hits -system.cpu.icache.overall_hits::total 285889001 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1159 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1159 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1159 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1159 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1159 # number of overall misses -system.cpu.icache.overall_misses::total 1159 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40537500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40537500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40537500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40537500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40537500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40537500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 285890160 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 285890160 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 285890160 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 285890160 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 285890160 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 285890160 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 627.769502 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.306528 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.306528 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 282204371 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 282204371 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 282204371 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 282204371 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 282204371 # number of overall hits +system.cpu.icache.overall_hits::total 282204371 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses +system.cpu.icache.overall_misses::total 1141 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38891500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38891500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38891500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38891500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38891500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38891500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 282205512 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 282205512 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 282205512 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 282205512 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 282205512 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 282205512 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34976.272649 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34976.272649 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34976.272649 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34976.272649 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34976.272649 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34976.272649 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34085.451358 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34085.451358 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34085.451358 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34085.451358 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34085.451358 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34085.451358 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,313 +398,313 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 366 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 366 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 366 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 366 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 366 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 793 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 793 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 793 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 793 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 793 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28758000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28758000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28758000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28758000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28758000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28758000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 363 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 363 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 363 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 363 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 363 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 778 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 778 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 778 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 778 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 778 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28274000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28274000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28274000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28274000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28274000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28274000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36264.817150 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36264.817150 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36264.817150 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36264.817150 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36264.817150 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36264.817150 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36341.902314 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36341.902314 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36341.902314 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36341.902314 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36341.902314 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36341.902314 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9619744 # number of replacements -system.cpu.dcache.tagsinuse 4087.812260 # Cycle average of tags in use -system.cpu.dcache.total_refs 661842215 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9623840 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.771116 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3371762000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.812260 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998001 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 494447214 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 494447214 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167394841 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167394841 # number of WriteReq hits +system.cpu.dcache.replacements 9617276 # number of replacements +system.cpu.dcache.tagsinuse 4087.426616 # Cycle average of tags in use +system.cpu.dcache.total_refs 660019994 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9621372 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.599363 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3361698000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.426616 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997907 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997907 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 492609527 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 492609527 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167410308 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167410308 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 93 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 93 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 64 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 64 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 661842055 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 661842055 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 661842055 # number of overall hits -system.cpu.dcache.overall_hits::total 661842055 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10786587 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10786587 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5191206 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5191206 # number of WriteReq misses +system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 660019835 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 660019835 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 660019835 # number of overall hits +system.cpu.dcache.overall_hits::total 660019835 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10110221 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10110221 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5175739 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5175739 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15977793 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15977793 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15977793 # number of overall misses -system.cpu.dcache.overall_misses::total 15977793 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 258796358500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 258796358500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 196312102576 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 196312102576 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 118500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 118500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 455108461076 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 455108461076 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 455108461076 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 455108461076 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 505233801 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 505233801 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 15285960 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15285960 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15285960 # number of overall misses +system.cpu.dcache.overall_misses::total 15285960 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 152096766000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 152096766000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119863517075 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119863517075 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 78000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 78000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 271960283075 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 271960283075 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 271960283075 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 271960283075 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 502719748 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 502719748 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 96 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 96 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 64 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 64 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 677819848 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 677819848 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 677819848 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 677819848 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021350 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021350 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030079 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.030079 # miss rate for WriteReq accesses +system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 675305795 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 675305795 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 675305795 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 675305795 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020111 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020111 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029989 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029989 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.031250 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.031250 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023572 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023572 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023572 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023572 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23992.423044 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23992.423044 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37816.280567 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37816.280567 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 39500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 39500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28483.812569 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28483.812569 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28483.812569 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28483.812569 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2524022061 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 152500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 425271 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5935.090944 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19062.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.022636 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022636 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022636 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022636 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15043.861652 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15043.861652 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23158.725174 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23158.725174 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17791.508226 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17791.508226 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17791.508226 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17791.508226 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 277962262 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 153500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 60300 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4609.656086 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17055.555556 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3474670 # number of writebacks -system.cpu.dcache.writebacks::total 3474670 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3056668 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3056668 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3297283 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3297283 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3473158 # number of writebacks +system.cpu.dcache.writebacks::total 3473158 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2383078 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2383078 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3281509 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3281509 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6353951 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6353951 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6353951 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6353951 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729919 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7729919 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893923 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893923 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9623842 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9623842 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9623842 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9623842 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 124459960000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 124459960000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91541598892 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91541598892 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 216001558892 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 216001558892 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 216001558892 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 216001558892 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015300 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015300 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014198 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014198 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014198 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014198 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16101.069106 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16101.069106 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48334.382597 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48334.382597 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22444.420731 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22444.420731 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22444.420731 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22444.420731 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 5664587 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5664587 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5664587 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5664587 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7727143 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7727143 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894230 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1894230 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9621373 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9621373 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9621373 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9621373 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75156431500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75156431500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 39462683260 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 39462683260 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114619114760 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 114619114760 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114619114760 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 114619114760 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015371 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015371 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010976 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010976 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014247 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014247 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9726.289717 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9726.289717 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20833.100130 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20833.100130 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11912.968633 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11912.968633 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11912.968633 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11912.968633 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2428430 # number of replacements -system.cpu.l2cache.tagsinuse 31166.069824 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8746727 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2458142 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.558268 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 81035522000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14015.954126 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 15.241585 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17134.874112 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.427733 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000465 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.522915 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.951113 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 33 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6117507 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6117540 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3474670 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3474670 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1063152 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1063152 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 33 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7180659 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7180692 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 33 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7180659 # number of overall hits -system.cpu.l2cache.overall_hits::total 7180692 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 759 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1612410 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1613169 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 830771 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 830771 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 759 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2443181 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2443940 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 759 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2443181 # number of overall misses -system.cpu.l2cache.overall_misses::total 2443940 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27428500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 58049619000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 58077047500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 32647460875 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 32647460875 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27428500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 90697079875 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 90724508375 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27428500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 90697079875 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 90724508375 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 792 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7729917 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7730709 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3474670 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3474670 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893923 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1893923 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 792 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9623840 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9624632 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 792 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9623840 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9624632 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958333 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208593 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.208670 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438651 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.438651 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958333 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.253868 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.253926 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958333 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.253868 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.253926 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36137.681159 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36001.773122 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36001.837067 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39297.785882 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39297.785882 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36137.681159 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37122.538148 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37122.232287 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36137.681159 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37122.538148 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37122.232287 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 30309734 # number of cycles access was blocked +system.cpu.l2cache.replacements 2427555 # number of replacements +system.cpu.l2cache.tagsinuse 31133.152617 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8743299 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2457267 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.558140 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 77440728000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14066.626463 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 15.622946 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 17050.903208 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.429279 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000477 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.520352 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.950108 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6115762 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6115791 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3473158 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3473158 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1063205 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1063205 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7178967 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7178996 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7178967 # number of overall hits +system.cpu.l2cache.overall_hits::total 7178996 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 749 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1611381 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1612130 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 831024 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 831024 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 749 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2442405 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2443154 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 749 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2442405 # number of overall misses +system.cpu.l2cache.overall_misses::total 2443154 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27440500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59348934500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 59376375000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 35714709005 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 35714709005 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27440500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 95063643505 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 95091084005 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27440500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 95063643505 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 95091084005 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7727143 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7727921 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3473158 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3473158 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894229 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1894229 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9621372 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9622150 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 778 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9621372 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9622150 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.962725 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208535 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.208611 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438714 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.438714 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962725 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.253852 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.253909 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962725 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.253852 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.253909 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36636.181575 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36831.099845 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36831.009286 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42976.747970 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42976.747970 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36636.181575 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38922.145797 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 38921.444987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36636.181575 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38922.145797 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 38921.444987 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 115700122 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 3624 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 21086 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8363.613135 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5487.058807 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1124204 # number of writebacks -system.cpu.l2cache.writebacks::total 1124204 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 758 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1612403 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1613161 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830771 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 830771 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 758 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2443174 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2443932 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 758 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2443174 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2443932 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24996000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 53015079500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53040075500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 30022059834 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 30022059834 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24996000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 83037139334 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 83062135334 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24996000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 83037139334 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 83062135334 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.957071 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208593 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208669 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438651 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438651 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.957071 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253867 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.253925 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.957071 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253867 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.253925 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32976.253298 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32879.546553 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32879.591994 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36137.587655 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36137.587655 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32976.253298 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33987.402999 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33987.089385 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32976.253298 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33987.402999 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33987.089385 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1124113 # number of writebacks +system.cpu.l2cache.writebacks::total 1124113 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 747 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611373 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1612120 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 831024 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 831024 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 747 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2442397 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2443144 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 747 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2442397 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2443144 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25029000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54213758000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54238787000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33085952005 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33085952005 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25029000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87299710005 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87324739005 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25029000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87299710005 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87324739005 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208534 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208610 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253851 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.253908 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253851 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.253908 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33506.024096 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33644.449795 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33644.385654 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39813.473504 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39813.473504 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33506.024096 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35743.456123 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35742.772020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33506.024096 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35743.456123 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35742.772020 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index becebde6e..49ea5f586 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.409361 # Number of seconds simulated -sim_ticks 2409361491000 # Number of ticks simulated -final_tick 2409361491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.399400 # Number of seconds simulated +sim_ticks 2399400439000 # Number of ticks simulated +final_tick 2399400439000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1043020 # Simulator instruction rate (inst/s) -host_op_rate 1164020 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1633141547 # Simulator tick rate (ticks/s) -host_mem_usage 227940 # Number of bytes of host memory used -host_seconds 1475.29 # Real time elapsed on the host +host_inst_rate 994913 # Simulator instruction rate (inst/s) +host_op_rate 1110332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1551375376 # Simulator tick rate (ticks/s) +host_mem_usage 233816 # Number of bytes of host memory used +host_seconds 1546.63 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 2153435 # Nu system.physmem.num_reads::total 2154051 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1050331 # Number of write requests responded to by this memory system.physmem.num_writes::total 1050331 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 57201811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 57218174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16363 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16363 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27899999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27899999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27899999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 57201811 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 85118173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 16431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 57439283 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 57455713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 28015825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 28015825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 28015825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 57439283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 85471539 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4818722982 # number of cpu cycles simulated +system.cpu.numCycles 4798800878 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759601 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 660773815 # nu system.cpu.num_load_insts 485926769 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4818722982 # Number of busy cycles +system.cpu.num_busy_cycles 4798800878 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 7 # number of replacements -system.cpu.icache.tagsinuse 515.026762 # Cycle average of tags in use +system.cpu.icache.tagsinuse 514.980115 # Cycle average of tags in use system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 515.026762 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.251478 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.251478 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 514.980115 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.251455 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.251455 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34951000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34951000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34951000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34951000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34951000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34951000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34189000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34189000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34189000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34189000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34189000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34189000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54782.131661 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54782.131661 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54782.131661 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54782.131661 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54782.131661 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54782.131661 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53587.774295 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53587.774295 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53587.774295 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53587.774295 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53587.774295 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53587.774295 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33037000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33037000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33037000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33037000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33037000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33037000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32913000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32913000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32913000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32913000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32913000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32913000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51782.131661 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51782.131661 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51782.131661 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51782.131661 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51782.131661 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51782.131661 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51587.774295 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51587.774295 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51587.774295 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51587.774295 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51587.774295 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51587.774295 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9111140 # number of replacements -system.cpu.dcache.tagsinuse 4083.605959 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4083.564925 # Cycle average of tags in use system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25924036000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4083.605959 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996974 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996974 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 25914432000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4083.564925 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996964 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996964 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115236 # n system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 158944725000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 158944725000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 59599499000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 59599499000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 218544224000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 218544224000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 218544224000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 218544224000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151247261000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151247261000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57698979000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57698979000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 208946240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 208946240000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 208946240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 208946240000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21995.960608 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21995.960608 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31548.331550 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31548.331550 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23975.706608 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23975.706608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23975.706608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23975.706608 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20930.727931 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20930.727931 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30542.312438 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30542.312438 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22922.746048 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22922.746048 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22922.746048 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22922.746048 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137266464000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 137266464000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53932052000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53932052000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191198516000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191198516000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191198516000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191198516000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136795087000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 136795087000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53920681000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53920681000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190715768000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 190715768000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190715768000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 190715768000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18995.960608 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18995.960608 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28548.331550 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28548.331550 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20975.706608 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20975.706608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20975.706608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20975.706608 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18930.727931 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18930.727931 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28542.312438 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28542.312438 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20922.746048 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20922.746048 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20922.746048 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20922.746048 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2138446 # number of replacements -system.cpu.l2cache.tagsinuse 30629.012311 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30623.782374 # Cycle average of tags in use system.cpu.l2cache.total_refs 8443619 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2168151 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 3.894387 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 437178443000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14783.850246 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 15.711580 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15829.450485 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.451167 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000479 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.483076 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.934723 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 435858689000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14787.769987 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 15.768959 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15820.243429 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.451287 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000481 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.482796 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.934564 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 5861680 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5861702 # number of ReadReq hits @@ -322,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 2154051 # nu system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2153435 # number of overall misses system.cpu.l2cache.overall_misses::total 2154051 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70949164000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 70981196000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41029456000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41029456000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111978620000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 112010652000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111978620000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 112010652000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32055000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70952200000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 70984255000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41030322000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41030322000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32055000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 111982522000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 112014577000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32055000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 111982522000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 112014577000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) @@ -357,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.236297 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.236246 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.236297 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52037.337662 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.225142 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52002.240988 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.097553 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.097553 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52037.337662 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.811989 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52001.822148 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52037.337662 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.811989 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52001.822148 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -389,17 +389,17 @@ system.cpu.l2cache.demand_mshr_misses::total 2154051 system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2153435 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2154051 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54576280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54600920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31561120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31561120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86137400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 86162040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86137400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86162040000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24663000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54579316000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54603979000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31561986000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31561986000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24663000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86141302000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 86165965000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24663000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86141302000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 86165965000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188817 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188885 # mshr miss rate for ReadReq accesses @@ -411,17 +411,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.236297 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.236297 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40037.337662 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.225142 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.240988 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.097553 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.097553 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40037.337662 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.811989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.822148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40037.337662 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.811989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.822148 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index a47f0fd8f..04d920eee 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.901049 # Number of seconds simulated -sim_ticks 5901048883000 # Number of ticks simulated -final_tick 5901048883000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.891582 # Number of seconds simulated +sim_ticks 5891581948000 # Number of ticks simulated +final_tick 5891581948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 582820 # Simulator instruction rate (inst/s) -host_op_rate 908086 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1143336514 # Simulator tick rate (ticks/s) -host_mem_usage 274832 # Number of bytes of host memory used -host_seconds 5161.25 # Real time elapsed on the host +host_inst_rate 701685 # Simulator instruction rate (inst/s) +host_op_rate 1093289 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1374310212 # Simulator tick rate (ticks/s) +host_mem_usage 228764 # Number of bytes of host memory used +host_seconds 4286.94 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862594 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 2172556 # Nu system.physmem.num_reads::total 2173231 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 23562520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 23569841 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7321 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7321 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11420657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11420657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11420657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 23562520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 34990498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 23600382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 23607714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11439009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11439009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11439009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 23600382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35046723 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11802097766 # number of cpu cycles simulated +system.cpu.numCycles 11783163896 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 1677713082 # nu system.cpu.num_load_insts 1239184745 # Number of load instructions system.cpu.num_store_insts 438528337 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11802097766 # Number of busy cycles +system.cpu.num_busy_cycles 11783163896 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 555.745887 # Cycle average of tags in use +system.cpu.icache.tagsinuse 555.725129 # Cycle average of tags in use system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 555.745887 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.271360 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.271360 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 555.725129 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.271350 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.271350 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37868000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37868000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37868000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37868000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37868000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37868000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37130000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37130000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37130000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37130000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37130000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37130000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56100.740741 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56100.740741 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56100.740741 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56100.740741 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55007.407407 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55007.407407 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55007.407407 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55007.407407 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675 system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35843000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35843000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35780000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 35780000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35780000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 35780000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35780000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 35780000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53100.740741 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53100.740741 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53007.407407 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53007.407407 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.tagsinuse 4084.618108 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4084.604436 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58864195000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4084.618108 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997221 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997221 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 58853994000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4084.604436 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997218 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997218 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 159195313000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 159195313000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 59631053000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 59631053000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 218826366000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 218826366000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 218826366000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 218826366000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151971083000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151971083000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57741123000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57741123000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 209712206000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 209712206000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 209712206000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 209712206000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.512125 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.512125 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.709943 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.709943 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24013.400892 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24013.400892 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21040.321064 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21040.321064 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30553.655440 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30553.655440 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23013.238152 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23013.238152 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137526763000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 137526763000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961572000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961572000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191488335000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191488335000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191488335000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191488335000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525383000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525383000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961469000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961469000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486852000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191486852000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486852000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191486852000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses @@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.512125 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.512125 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.709943 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.709943 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.321064 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.321064 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.655440 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.655440 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2158210 # number of replacements -system.cpu.l2cache.tagsinuse 30851.471482 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30849.854795 # Cycle average of tags in use system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1317386123000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14661.795129 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 21.581563 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16168.094790 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.447442 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000659 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.493411 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.941512 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 1315499445000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14663.466685 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 21.611649 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16164.776461 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.447493 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000660 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.493310 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.941463 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 5840135 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5840135 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3375759 # number of Writeback hits @@ -269,17 +269,17 @@ system.cpu.l2cache.demand_misses::total 2173231 # nu system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2172556 # number of overall misses system.cpu.l2cache.overall_misses::total 2173231 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35100000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71901180000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71936280000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41071732000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41071732000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35100000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112972912000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 113008012000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35100000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112972912000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 113008012000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35105000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71901183000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71936288000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41071782000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41071782000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35105000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112972965000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 113008070000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35105000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112972965000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 113008070000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses) @@ -304,17 +304,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.238467 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.238410 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.238467 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52007.407407 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.002170 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.005783 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.063304 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.063304 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.024395 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.026688 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.024395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.026688 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -336,17 +336,17 @@ system.cpu.l2cache.demand_mshr_misses::total 2173231 system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2172556 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2173231 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27000000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55308600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55335600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31593640000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31593640000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86902240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 86929240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86902240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86929240000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27005000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55308603000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55335608000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31593690000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31593690000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27005000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86902293000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 86929298000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27005000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86902293000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 86929298000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.191436 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191512 # mshr miss rate for ReadReq accesses @@ -358,17 +358,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.238467 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.238467 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40007.407407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.002170 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.005783 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.063304 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.063304 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |