diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
| commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
| tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/long/se/60.bzip2/ref | |
| parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
| download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz | |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/long/se/60.bzip2/ref')
6 files changed, 2081 insertions, 2081 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 24ed3058e..fe02977f3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.015958 # Number of seconds simulated -sim_ticks 1015958135500 # Number of ticks simulated -final_tick 1015958135500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.017017 # Number of seconds simulated +sim_ticks 1017016979500 # Number of ticks simulated +final_tick 1017016979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102863 # Simulator instruction rate (inst/s) -host_op_rate 102863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57427110 # Simulator tick rate (ticks/s) -host_mem_usage 225152 # Number of bytes of host memory used -host_seconds 17691.26 # Real time elapsed on the host +host_inst_rate 113008 # Simulator instruction rate (inst/s) +host_op_rate 113008 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63156510 # Simulator tick rate (ticks/s) +host_mem_usage 225148 # Number of bytes of host memory used +host_seconds 16103.12 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125365184 # Number of bytes read from this memory -system.physmem.bytes_read::total 125420160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125365248 # Number of bytes read from this memory +system.physmem.bytes_read::total 125420224 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958831 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959690 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1958832 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959691 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 123396014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 123450126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54112 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54112 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 64132280 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 64132280 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 64132280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 123396014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 187582407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959690 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 54056 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 123267606 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 123321662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54056 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54056 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 64065511 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 64065511 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 64065511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 123267606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 187387172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959691 # Total number of read requests seen system.physmem.writeReqs 1018058 # Total number of write requests seen -system.physmem.cpureqs 2977748 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125420160 # Total number of bytes read from memory +system.physmem.cpureqs 2977749 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125420224 # Total number of bytes read from memory system.physmem.bytesWritten 65155712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125420160 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 125420224 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 578 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 576 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 118716 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 114074 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 116204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 117698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 117699 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 117773 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 117508 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 119859 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 124486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 126960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 126961 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 130063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 128617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 128618 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 130264 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 125937 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 125207 # Track reads on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 64552 # Tr system.physmem.perBankWrReqs::15 64187 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1015958077500 # Total gap between requests +system.physmem.totGap 1017016906500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1959690 # Categorize read packet sizes +system.physmem.readPktSize::6 1959691 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,10 +92,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 1018058 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1654417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 206034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 74348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1654293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 205923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 74498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24401 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -124,10 +124,10 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 44264 # What write queue length does an incoming req see @@ -147,45 +147,45 @@ system.physmem.wrQLenPdf::19 44263 # Wh system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1724238 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 110.484683 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.063313 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.326643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1380958 80.09% 80.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 190861 11.07% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 56628 3.28% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 27570 1.60% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15749 0.91% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1724249 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 110.484089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.062986 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.322838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1380983 80.09% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 190835 11.07% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 56645 3.29% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 27563 1.60% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15745 0.91% 96.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-385 10044 0.58% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6620 0.38% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6559 0.38% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3696 0.21% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 2923 0.17% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2676 0.16% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2682 0.16% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1400 0.08% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1070 0.06% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1040 0.06% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 917 0.05% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6630 0.38% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6555 0.38% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3694 0.21% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 2928 0.17% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2668 0.15% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2688 0.16% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1402 0.08% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1069 0.06% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1034 0.06% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 922 0.05% 99.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088-1089 816 0.05% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 821 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 760 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 818 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 762 0.04% 99.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::1280-1281 561 0.03% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 626 0.04% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 627 0.04% 99.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::1408-1409 841 0.05% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3634 0.21% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 546 0.03% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 235 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 177 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3636 0.21% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 543 0.03% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 234 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 178 0.01% 99.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::1728-1729 137 0.01% 99.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::1792-1793 143 0.01% 99.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation @@ -197,10 +197,10 @@ system.physmem.bytesPerActivate::2176-2177 67 0.00% 99.82% # system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2305 60 0.00% 99.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 57 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 45 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 58 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 44 0.00% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::2560-2561 52 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 34 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 35 0.00% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::2752-2753 29 0.00% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.85% # Bytes accessed per row activation @@ -208,7 +208,7 @@ system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.85% # system.physmem.bytesPerActivate::2944-2945 31 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3008-3009 19 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 27 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 23 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 22 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3200-3201 16 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3264-3265 31 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3328-3329 31 0.00% 99.87% # Bytes accessed per row activation @@ -228,8 +228,8 @@ system.physmem.bytesPerActivate::4160-4161 8 0.00% 99.88% # system.physmem.bytesPerActivate::4224-4225 8 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4352-4353 24 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 11 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 12 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 9 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4544-4545 18 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608-4609 6 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.88% # Bytes accessed per row activation @@ -266,8 +266,8 @@ system.physmem.bytesPerActivate::6592-6593 4 0.00% 99.90% # system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6720-6721 6 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 8 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::7040-7041 4 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.90% # Bytes accessed per row activation @@ -288,73 +288,73 @@ system.physmem.bytesPerActivate::8000-8001 19 0.00% 99.92% # system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 14 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1430 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1724238 # Bytes accessed per row activation -system.physmem.totQLat 33987005500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 98689973000 # Sum of mem lat for all requests -system.physmem.totBusLat 9795560000 # Total cycles spent in databus access -system.physmem.totBankLat 54907407500 # Total cycles spent in bank access -system.physmem.avgQLat 17348.17 # Average queueing delay per request -system.physmem.avgBankLat 28026.68 # Average bank access latency per request +system.physmem.bytesPerActivate::total 1724249 # Bytes accessed per row activation +system.physmem.totQLat 33963917000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 98664809500 # Sum of mem lat for all requests +system.physmem.totBusLat 9795575000 # Total cycles spent in databus access +system.physmem.totBankLat 54905317500 # Total cycles spent in bank access +system.physmem.avgQLat 17336.36 # Average queueing delay per request +system.physmem.avgBankLat 28025.57 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 50374.85 # Average memory access latency -system.physmem.avgRdBW 123.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 64.13 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 123.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 64.13 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 50361.93 # Average memory access latency +system.physmem.avgRdBW 123.32 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 64.07 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 123.32 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 64.07 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.47 # Data bus utilization in percentage +system.physmem.busUtil 1.46 # Data bus utilization in percentage system.physmem.avgRdQLen 0.10 # Average read queue length over time system.physmem.avgWrQLen 10.57 # Average write queue length over time -system.physmem.readRowHits 900967 # Number of row buffer hits during reads -system.physmem.writeRowHits 351956 # Number of row buffer hits during writes +system.physmem.readRowHits 900981 # Number of row buffer hits during reads +system.physmem.writeRowHits 351934 # Number of row buffer hits during writes system.physmem.readRowHitRate 45.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate 34.57 # Row buffer hit rate for writes -system.physmem.avgGap 341183.36 # Average gap between requests -system.membus.throughput 187582407 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1178392 # Transaction distribution -system.membus.trans_dist::ReadResp 1178392 # Transaction distribution +system.physmem.avgGap 341538.83 # Average gap between requests +system.membus.throughput 187387172 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1178393 # Transaction distribution +system.membus.trans_dist::ReadResp 1178393 # Transaction distribution system.membus.trans_dist::Writeback 1018058 # Transaction distribution system.membus.trans_dist::ReadExReq 781298 # Transaction distribution system.membus.trans_dist::ReadExResp 781298 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 4937438 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 4937438 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575872 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 190575872 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190575872 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 4937440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4937440 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575936 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 190575936 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190575936 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11748266000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11803876500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 18466425750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18471159750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu.branchPred.lookups 326521750 # Number of BP lookups -system.cpu.branchPred.condPredicted 252556520 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 138229412 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 220084071 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135399986 # Number of BTB hits +system.cpu.branchPred.lookups 326564713 # Number of BP lookups +system.cpu.branchPred.condPredicted 252601424 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 138218301 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 218593713 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135545625 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.521938 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 62.008016 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444838557 # DTB read hits +system.cpu.dtb.read_hits 444840309 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449735635 # DTB read accesses -system.cpu.dtb.write_hits 160846849 # DTB write hits +system.cpu.dtb.read_accesses 449737387 # DTB read accesses +system.cpu.dtb.write_hits 160847153 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162548153 # DTB write accesses -system.cpu.dtb.data_hits 605685406 # DTB hits +system.cpu.dtb.write_accesses 162548457 # DTB write accesses +system.cpu.dtb.data_hits 605687462 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612283788 # DTB accesses -system.cpu.itb.fetch_hits 231915406 # ITB hits +system.cpu.dtb.data_accesses 612285844 # DTB accesses +system.cpu.itb.fetch_hits 231947501 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231915428 # ITB accesses +system.cpu.itb.fetch_accesses 231947523 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -368,34 +368,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2031916272 # number of cpu cycles simulated +system.cpu.numCycles 2034033960 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172213740 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154308010 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667655233 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172359749 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154204964 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667587623 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043857850 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043790240 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651713796 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617884761 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 120483996 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 11146958 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 131630954 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 83569020 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.166808 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139383608 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651716905 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617884714 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120522396 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11097447 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131619843 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83580106 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.161652 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139337588 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1742160374 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1742086287 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7533550 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 460194055 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571722217 # Number of cycles cpu stages are processed. -system.cpu.activity 77.351722 # Percentage of cycles cpu is active +system.cpu.timesIdled 7521644 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 462344107 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571689853 # Number of cycles cpu stages are processed. +system.cpu.activity 77.269597 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -407,211 +407,211 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.116572 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.117736 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.116572 # CPI: Total CPI of All Threads -system.cpu.ipc 0.895598 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.117736 # CPI: Total CPI of All Threads +system.cpu.ipc 0.894666 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.895598 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 845299879 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186616393 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 58.398882 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1098097789 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933818483 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.957528 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1059529924 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972386348 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 47.855631 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1622292075 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409624197 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.159502 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 1010582157 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021334115 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.264577 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 668.704565 # Cycle average of tags in use -system.cpu.icache.total_refs 231914267 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 269981.684517 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 668.704565 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.326516 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.326516 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231914267 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231914267 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231914267 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231914267 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231914267 # number of overall hits -system.cpu.icache.overall_hits::total 231914267 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses -system.cpu.icache.overall_misses::total 1139 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82633000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82633000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82633000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82633000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82633000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82633000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231915406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231915406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231915406 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231915406 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231915406 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231915406 # number of overall (read+write) accesses +system.cpu.ipc_total 0.894666 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 847369948 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186664012 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.340423 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1100283558 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933750402 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.906333 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1061657822 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972376138 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 47.805305 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1624406509 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409627451 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.138673 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 1012697898 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021336062 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.212341 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 668.751330 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 231946364 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 270019.050058 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 668.751330 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.326539 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.326539 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 231946364 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231946364 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231946364 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231946364 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231946364 # number of overall hits +system.cpu.icache.overall_hits::total 231946364 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1137 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1137 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1137 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1137 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1137 # number of overall misses +system.cpu.icache.overall_misses::total 1137 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 82490250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 82490250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 82490250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 82490250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 82490250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 82490250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231947501 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231947501 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231947501 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231947501 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231947501 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231947501 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72548.726953 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72548.726953 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72548.726953 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72548.726953 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72548.726953 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72548.726953 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72550.791557 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72550.791557 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72550.791557 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72550.791557 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72550.791557 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72550.791557 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 159 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 162 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 278 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 278 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 278 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 278 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 278 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 64913500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 64913500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 64913500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 64913500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 64913500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 64913500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65194000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 65194000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65194000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 65194000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65194000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 65194000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75568.684517 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75568.684517 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75568.684517 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75568.684517 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75568.684517 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75568.684517 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75895.227008 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75895.227008 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75895.227008 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75895.227008 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75895.227008 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75895.227008 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 806684389 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 805844654 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7222689 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7222689 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3693280 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3693279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889621 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916176 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 21917894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916181 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 21917899 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819502592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 819557568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 819557568 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819502720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 819557696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 819557696 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 10096073500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1288500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1466500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13667172000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.l2cache.replacements 1926959 # number of replacements -system.cpu.l2cache.tagsinuse 30929.406479 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8958686 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1956752 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.578345 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 67679483750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14929.609549 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.376091 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15965.420838 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.455616 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001049 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.487226 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.943891 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6044297 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6044297 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3693280 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3693280 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108320 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108320 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7152617 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7152617 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7152617 # number of overall hits -system.cpu.l2cache.overall_hits::total 7152617 # number of overall hits +system.cpu.toL2Bus.respLayer1.occupancy 14100129000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 1926960 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30930.857959 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8958684 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1956753 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.578342 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 67691760750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14923.938165 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.347502 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15972.572292 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455442 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001048 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.487444 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.943935 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6044296 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6044296 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3693279 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3693279 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108323 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108323 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7152619 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7152619 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7152619 # number of overall hits +system.cpu.l2cache.overall_hits::total 7152619 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1177533 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1178392 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1177534 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1178393 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 781298 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 781298 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1958831 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1959690 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1958832 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1959691 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1958831 # number of overall misses -system.cpu.l2cache.overall_misses::total 1959690 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 64050500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 103817165500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 103881216000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 79016574500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 79016574500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 64050500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 182833740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 182897790500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 64050500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 182833740000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 182897790500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 1958832 # number of overall misses +system.cpu.l2cache.overall_misses::total 1959691 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 64331000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 104087297000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 104151628000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 79166748750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 79166748750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 64331000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 183254045750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 183318376750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 64331000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 183254045750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 183318376750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7221830 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7222689 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3693280 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3693280 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889618 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889618 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3693279 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3693279 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889621 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889621 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111448 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112307 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111451 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112310 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111448 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112307 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111451 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112310 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413469 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.413469 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163152 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413468 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413468 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.214986 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.215060 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214986 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215060 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74564.027939 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88164.973296 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 88155.058758 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101135.001626 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101135.001626 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74564.027939 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93338.189971 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 93329.960606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74564.027939 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93338.189971 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 93329.960606 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74890.570431 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88394.302840 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 88384.459174 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101327.212856 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101327.212856 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74890.570431 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93552.711897 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93544.531638 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74890.570431 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93552.711897 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93544.531638 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -623,83 +623,83 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 1018058 # number of writebacks system.cpu.l2cache.writebacks::total 1018058 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177533 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1178392 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177534 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1178393 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781298 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 781298 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1958831 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1959690 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958832 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1959691 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1958831 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1959690 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53393500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 89166260000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89219653500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69332641250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69332641250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53393500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158498901250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 158552294750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53393500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158498901250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 158552294750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958832 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959691 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53514000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 89157154500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89210668500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69321257750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69321257750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158478412250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158531926250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53514000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158478412250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158531926250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413469 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413469 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413468 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413468 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.215060 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215060 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62157.741560 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75722.939400 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75713.050920 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88740.328594 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88740.328594 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62157.741560 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80915.046398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80906.824421 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62157.741560 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80915.046398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80906.824421 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62298.020955 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75715.142408 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75705.361878 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88725.758609 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88725.758609 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62298.020955 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80904.545285 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80896.389405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62298.020955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80904.545285 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80896.389405 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107352 # number of replacements -system.cpu.dcache.tagsinuse 4082.468819 # Cycle average of tags in use -system.cpu.dcache.total_refs 593298146 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.115682 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12678178000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.468819 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996696 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996696 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437268759 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437268759 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156029387 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156029387 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593298146 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593298146 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593298146 # number of overall hits -system.cpu.dcache.overall_hits::total 593298146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7326904 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7326904 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4699115 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4699115 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 12026019 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12026019 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12026019 # number of overall misses -system.cpu.dcache.overall_misses::total 12026019 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 188246527500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 188246527500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 260860363500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 260860363500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 449106891000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 449106891000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 449106891000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 449106891000 # number of overall miss cycles +system.cpu.dcache.tags.replacements 9107355 # number of replacements +system.cpu.dcache.tags.tagsinuse 4082.476561 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 593297569 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111451 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.115597 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 12681367250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4082.476561 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996698 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437268765 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268765 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156028804 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156028804 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593297569 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593297569 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593297569 # number of overall hits +system.cpu.dcache.overall_hits::total 593297569 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326898 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326898 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4699698 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4699698 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 12026596 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12026596 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12026596 # number of overall misses +system.cpu.dcache.overall_misses::total 12026596 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 189082879500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 189082879500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 263051310000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 263051310000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 452134189500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 452134189500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 452134189500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 452134189500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -710,54 +710,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029236 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029236 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019867 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019867 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019867 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019867 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25692.506344 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25692.506344 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55512.657915 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55512.657915 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37344.601817 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37344.601817 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37344.601817 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37344.601817 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15563445 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7313446 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 432083 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 73150 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.019573 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 99.978756 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029240 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029240 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019868 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019868 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019868 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019868 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25806.675554 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25806.675554 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55971.960326 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55971.960326 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37594.527121 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37594.527121 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37594.527121 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37594.527121 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15699726 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7389800 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 434712 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 73152 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.115235 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 101.019794 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693280 # number of writebacks -system.cpu.dcache.writebacks::total 3693280 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104632 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104632 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2809939 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2809939 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2914571 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2914571 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2914571 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2914571 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 3693279 # number of writebacks +system.cpu.dcache.writebacks::total 3693279 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104626 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104626 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2810519 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2810519 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2915145 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2915145 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2915145 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2915145 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222272 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222272 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889176 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889176 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171613180000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 171613180000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92147472000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92147472000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263760652000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 263760652000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263760652000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 263760652000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889179 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889179 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111451 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111451 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111451 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111451 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171880361750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171880361750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92301345750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92301345750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264181707500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 264181707500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264181707500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 264181707500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -766,14 +766,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23761.661150 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23761.661150 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48776.541730 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48776.541730 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28948.269474 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28948.269474 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28948.269474 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28948.269474 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23798.655292 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23798.655292 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48857.914337 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48857.914337 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28994.471627 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28994.471627 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28994.471627 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28994.471627 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 88a7eaf62..b939ad0cc 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.693021 # Number of seconds simulated -sim_ticks 693021015500 # Number of ticks simulated -final_tick 693021015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.694171 # Number of seconds simulated +sim_ticks 694171131000 # Number of ticks simulated +final_tick 694171131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172458 # Simulator instruction rate (inst/s) -host_op_rate 172458 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68844519 # Simulator tick rate (ticks/s) -host_mem_usage 228224 # Number of bytes of host memory used -host_seconds 10066.47 # Real time elapsed on the host +host_inst_rate 169313 # Simulator instruction rate (inst/s) +host_op_rate 169313 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67701038 # Simulator tick rate (ticks/s) +host_mem_usage 228220 # Number of bytes of host memory used +host_seconds 10253.48 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125798976 # Number of bytes read from this memory -system.physmem.bytes_read::total 125860352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65263616 # Number of bytes written to this memory -system.physmem.bytes_written::total 65263616 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965609 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966568 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019744 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019744 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 88563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 181522599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 181611162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 88563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 88563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 94172636 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 94172636 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 94172636 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 88563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 181522599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 275783798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966568 # Total number of read requests seen -system.physmem.writeReqs 1019744 # Total number of write requests seen -system.physmem.cpureqs 2986322 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125860352 # Total number of bytes read from memory -system.physmem.bytesWritten 65263616 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125860352 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65263616 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 585 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125790400 # Number of bytes read from this memory +system.physmem.bytes_read::total 125852032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65261440 # Number of bytes written to this memory +system.physmem.bytes_written::total 65261440 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965475 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966438 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019710 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019710 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 88785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 181209495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 181298280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 88785 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 88785 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 94013475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 94013475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 94013475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 88785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 181209495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 275311755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966438 # Total number of read requests seen +system.physmem.writeReqs 1019710 # Total number of write requests seen +system.physmem.cpureqs 2986156 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125852032 # Total number of bytes read from memory +system.physmem.bytesWritten 65261440 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125852032 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65261440 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 561 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 119008 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 114438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 116555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 118046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 118149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 117808 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 120225 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 124916 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 127564 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 130488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 129072 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 130765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 126644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 125671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 122973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123661 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 61280 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 119011 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 114417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 116554 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 118021 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 118126 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 117795 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 120229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 124937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 127536 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 130495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 129073 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 130794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 126583 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 125666 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 122963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123677 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 61282 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 61566 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 60655 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 61327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 61759 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 64220 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 65701 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 65486 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 65876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 65409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 65716 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64323 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64319 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 64636 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64301 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 60662 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 61309 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 61746 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63171 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 64226 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 65702 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 65470 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 65888 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 65399 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 65733 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64310 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64314 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 64641 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64291 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry -system.physmem.totGap 693020927000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry +system.physmem.totGap 694171008500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966568 # Categorize read packet sizes +system.physmem.readPktSize::6 1966438 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1019744 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1645883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 229621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20600 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019710 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1645970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 229492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20630 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -124,237 +124,237 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 43449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44296 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1725071 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 110.744307 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.207489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.283228 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1378927 79.93% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 191993 11.13% 91.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 57386 3.33% 94.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 28102 1.63% 96.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15937 0.92% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 9770 0.57% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6740 0.39% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6906 0.40% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3659 0.21% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3018 0.17% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2639 0.15% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2655 0.15% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1401 0.08% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1109 0.06% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1069 0.06% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 819 0.05% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 853 0.05% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 845 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 758 0.04% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 637 0.04% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 729 0.04% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 683 0.04% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3600 0.21% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 572 0.03% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 238 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 183 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 143 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 137 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 83 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 102 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 118 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 69 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 71 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 61 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 48 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 55 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 46 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 41 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 53 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 35 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 34 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 36 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 52 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 44 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 22 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 36 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 29 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 20 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 25 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 30 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 21 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 16 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 19 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 21 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 15 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1724767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 110.763752 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.212194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.511378 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1378543 79.93% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 191920 11.13% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 57620 3.34% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 28373 1.65% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15698 0.91% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 9692 0.56% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6693 0.39% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6792 0.39% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3776 0.22% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 2960 0.17% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2630 0.15% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2677 0.16% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1390 0.08% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1126 0.07% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1092 0.06% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 878 0.05% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 859 0.05% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 813 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 757 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 627 0.04% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 709 0.04% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 705 0.04% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3570 0.21% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 579 0.03% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 253 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 194 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 136 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 146 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 142 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 94 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 85 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 102 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 71 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 61 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 59 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 49 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 59 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 39 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 46 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 34 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 39 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 28 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 48 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 43 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 24 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 22 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 32 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 25 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 21 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 25 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 26 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 19 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 25 0.00% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3649 13 0.00% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::3712-3713 10 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 20 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 21 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 25 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 12 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 15 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 16 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 13 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 10 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 23 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 19 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 7 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 9 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 7 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 11 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 5 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 17 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 4 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 9 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 26 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 18 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 13 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 27 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 21 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 6 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 16 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 14 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 28 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 7 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 12 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 9 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 6 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 14 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 10 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 9 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 12 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 10 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 21 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 13 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 11 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 7 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 7 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 11 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 12 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 13 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 19 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6336-6337 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 4 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 13 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::7168-7169 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 15 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 118 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 15 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 12 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 16 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1427 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1725071 # Bytes accessed per row activation -system.physmem.totQLat 33871310750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 97989140750 # Sum of mem lat for all requests -system.physmem.totBusLat 9829915000 # Total cycles spent in databus access -system.physmem.totBankLat 54287915000 # Total cycles spent in bank access -system.physmem.avgQLat 17228.69 # Average queueing delay per request -system.physmem.avgBankLat 27613.62 # Average bank access latency per request +system.physmem.bytesPerActivate::7232-7233 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 17 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 11 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 123 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 12 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 18 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 15 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1429 0.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1724767 # Bytes accessed per row activation +system.physmem.totQLat 33917679750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 98022206000 # Sum of mem lat for all requests +system.physmem.totBusLat 9829385000 # Total cycles spent in databus access +system.physmem.totBankLat 54275141250 # Total cycles spent in bank access +system.physmem.avgQLat 17253.21 # Average queueing delay per request +system.physmem.avgBankLat 27608.62 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 49842.31 # Average memory access latency -system.physmem.avgRdBW 181.61 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 94.17 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 181.61 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 94.17 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 49861.82 # Average memory access latency +system.physmem.avgRdBW 181.30 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 94.01 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 181.30 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 94.01 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 11.24 # Average write queue length over time -system.physmem.readRowHits 907929 # Number of row buffer hits during reads -system.physmem.writeRowHits 352711 # Number of row buffer hits during writes -system.physmem.readRowHitRate 46.18 # Row buffer hit rate for reads +system.physmem.avgWrQLen 10.67 # Average write queue length over time +system.physmem.readRowHits 908058 # Number of row buffer hits during reads +system.physmem.writeRowHits 352757 # Number of row buffer hits during writes +system.physmem.readRowHitRate 46.19 # Row buffer hit rate for reads system.physmem.writeRowHitRate 34.59 # Row buffer hit rate for writes -system.physmem.avgGap 232065.81 # Average gap between requests -system.membus.throughput 275783798 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191455 # Transaction distribution -system.membus.trans_dist::ReadResp 1191455 # Transaction distribution -system.membus.trans_dist::Writeback 1019744 # Transaction distribution -system.membus.trans_dist::ReadExReq 775113 # Transaction distribution -system.membus.trans_dist::ReadExResp 775113 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 4952880 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 4952880 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 191123968 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 191123968 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191123968 # Total data (bytes) +system.physmem.avgGap 232463.70 # Average gap between requests +system.membus.throughput 275311755 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191259 # Transaction distribution +system.membus.trans_dist::ReadResp 1191259 # Transaction distribution +system.membus.trans_dist::Writeback 1019710 # Transaction distribution +system.membus.trans_dist::ReadExReq 775179 # Transaction distribution +system.membus.trans_dist::ReadExResp 775179 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 4952586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4952586 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 191113472 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 191113472 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191113472 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11815530000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11881655250 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18578292500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18594236500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) -system.cpu.branchPred.lookups 381829258 # Number of BP lookups -system.cpu.branchPred.condPredicted 296791594 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16090940 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262534664 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259935463 # Number of BTB hits +system.cpu.branchPred.lookups 381853679 # Number of BP lookups +system.cpu.branchPred.condPredicted 296812462 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16082560 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 263010897 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259938392 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.009959 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24706233 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3077 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.831796 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24703686 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3043 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613998993 # DTB read hits -system.cpu.dtb.read_misses 11257757 # DTB read misses +system.cpu.dtb.read_hits 613967200 # DTB read hits +system.cpu.dtb.read_misses 11252585 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625256750 # DTB read accesses -system.cpu.dtb.write_hits 212346659 # DTB write hits -system.cpu.dtb.write_misses 7132839 # DTB write misses +system.cpu.dtb.read_accesses 625219785 # DTB read accesses +system.cpu.dtb.write_hits 212300531 # DTB write hits +system.cpu.dtb.write_misses 7117395 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219479498 # DTB write accesses -system.cpu.dtb.data_hits 826345652 # DTB hits -system.cpu.dtb.data_misses 18390596 # DTB misses +system.cpu.dtb.write_accesses 219417926 # DTB write accesses +system.cpu.dtb.data_hits 826267731 # DTB hits +system.cpu.dtb.data_misses 18369980 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844736248 # DTB accesses -system.cpu.itb.fetch_hits 391092043 # ITB hits -system.cpu.itb.fetch_misses 41 # ITB misses +system.cpu.dtb.data_accesses 844637711 # DTB accesses +system.cpu.itb.fetch_hits 391085180 # ITB hits +system.cpu.itb.fetch_misses 51 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 391092084 # ITB accesses +system.cpu.itb.fetch_accesses 391085231 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -368,238 +368,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1386042032 # number of cpu cycles simulated +system.cpu.numCycles 1388342263 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402569601 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3162430835 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381829258 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284641696 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574759222 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140771117 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 196436536 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1508 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 391092043 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8064861 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1290645563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.450271 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.141948 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402551684 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3162454030 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381853679 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284642078 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574754052 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140783496 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 197047269 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1488 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 391085180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8065065 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1291251504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.449139 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.141692 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 715886341 55.47% 55.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42669337 3.31% 58.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21804756 1.69% 60.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39713212 3.08% 63.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129418344 10.03% 73.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61537126 4.77% 78.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38572706 2.99% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28132820 2.18% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212910921 16.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 716497452 55.49% 55.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42682670 3.31% 58.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21784053 1.69% 60.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39696423 3.07% 63.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129425846 10.02% 73.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61545626 4.77% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38574460 2.99% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28124081 2.18% 83.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212920893 16.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1290645563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.275482 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.281627 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434522823 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 177728995 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542687123 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18828896 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116877726 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58348631 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 887 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3089538872 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2030 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116877726 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 457522679 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 122552150 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7258 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535724767 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 57960983 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3007258855 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 610716 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1836419 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 51661727 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2248310547 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3900270173 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3899027162 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1243011 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1291251504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.275043 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.277863 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434540420 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 178303124 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542717448 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18794331 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116896181 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58354479 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 840 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3089587827 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116896181 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457532531 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 123212849 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5836 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535730171 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 57873936 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3007379456 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 610253 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1826446 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51579864 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2248363732 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3900421320 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3899178783 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1242537 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 872107584 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 171 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 169 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 123506231 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679721710 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255512825 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67679975 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36990562 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2725376863 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 131 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2509736857 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3186715 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 980131211 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 416747410 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 102 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1290645563 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.944559 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.970905 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 872160769 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 168 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 168 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123444205 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679751883 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255539846 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68026727 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37555626 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2725485841 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 123 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509620077 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3191439 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 980254556 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 417071077 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 94 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1291251504 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.943556 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971187 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 448740391 34.77% 34.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203240605 15.75% 50.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185935244 14.41% 64.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153422938 11.89% 76.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133053941 10.31% 87.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80846786 6.26% 93.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65044265 5.04% 98.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15249478 1.18% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5111915 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 449456095 34.81% 34.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203314241 15.75% 50.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185688017 14.38% 64.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153487226 11.89% 76.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133078124 10.31% 87.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80722513 6.25% 93.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65115490 5.04% 98.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15268261 1.18% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5121537 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1290645563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1291251504 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2163556 11.71% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11907011 64.43% 76.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4409853 23.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2192750 11.84% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11923038 64.36% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4410634 23.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643982989 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 103 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 270 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 158 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641664411 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224088858 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643953882 65.51% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 103 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 266 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 157 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 35 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641631628 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224033966 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2509736857 # Type of FU issued -system.cpu.iq.rate 1.810722 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18480420 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007363 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6329888754 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3704398033 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2413211688 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1897658 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1216996 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 850977 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2527279284 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 937993 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62596809 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509620077 # Type of FU issued +system.cpu.iq.rate 1.807638 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18526422 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007382 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6330307505 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3704630064 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413135648 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1902014 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1217951 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 852306 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527206104 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 940395 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62612888 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235126047 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263685 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 108576 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94784323 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235156220 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263801 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 109236 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94811344 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 179 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1583083 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 161 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1579414 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116877726 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 58990263 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1298967 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2867530467 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8941640 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679721710 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255512825 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 131 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 325521 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17838 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 108576 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10366897 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8557633 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18924530 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2462313409 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625257301 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47423448 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116896181 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 59627165 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1293281 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2867673451 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8945086 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679751883 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255539846 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 123 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 277586 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17880 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 109236 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10358298 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8554506 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18912804 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462213177 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625220360 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47406900 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142153473 # number of nop insts executed -system.cpu.iew.exec_refs 844736823 # number of memory reference insts executed -system.cpu.iew.exec_branches 300880868 # Number of branches executed -system.cpu.iew.exec_stores 219479522 # Number of stores executed -system.cpu.iew.exec_rate 1.776507 # Inst execution rate -system.cpu.iew.wb_sent 2442002538 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2414062665 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388567182 # num instructions producing a value -system.cpu.iew.wb_consumers 1764588303 # num instructions consuming a value +system.cpu.iew.exec_nop 142187487 # number of nop insts executed +system.cpu.iew.exec_refs 844638305 # number of memory reference insts executed +system.cpu.iew.exec_branches 300894564 # Number of branches executed +system.cpu.iew.exec_stores 219417945 # Number of stores executed +system.cpu.iew.exec_rate 1.773491 # Inst execution rate +system.cpu.iew.wb_sent 2441919357 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413987954 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388436926 # num instructions producing a value +system.cpu.iew.wb_consumers 1764428707 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.741695 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back +system.cpu.iew.wb_rate 1.738756 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786905 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 827045847 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 827192555 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16090137 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1173767837 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.550375 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.495661 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16081773 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1174355323 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.549599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.495377 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 659878599 56.22% 56.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174801477 14.89% 71.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86143733 7.34% 78.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53556827 4.56% 83.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34704625 2.96% 85.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26036675 2.22% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21629651 1.84% 90.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22889079 1.95% 91.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94127171 8.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 660542597 56.25% 56.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174710504 14.88% 71.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86129545 7.33% 78.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53592661 4.56% 83.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34688707 2.95% 85.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26049111 2.22% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21601989 1.84% 90.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22901440 1.95% 91.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94138769 8.02% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1173767837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1174355323 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -610,209 +610,209 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94127171 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94138769 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3640687439 # The number of ROB reads -system.cpu.rob.rob_writes 5410628429 # The number of ROB writes -system.cpu.timesIdled 939185 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 95396469 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3641410035 # The number of ROB reads +system.cpu.rob.rob_writes 5410940495 # The number of ROB writes +system.cpu.timesIdled 938493 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 97090759 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.798391 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.798391 # CPI: Total CPI of All Threads -system.cpu.ipc 1.252519 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.252519 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3318270268 # number of integer regfile reads -system.cpu.int_regfile_writes 1932125497 # number of integer regfile writes -system.cpu.fp_regfile_reads 30353 # number of floating regfile reads +system.cpu.cpi 0.799716 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.799716 # CPI: Total CPI of All Threads +system.cpu.ipc 1.250444 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.250444 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3318091757 # number of integer regfile reads +system.cpu.int_regfile_writes 1932096202 # number of integer regfile writes +system.cpu.fp_regfile_reads 30725 # number of floating regfile reads system.cpu.fp_regfile_writes 534 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1191881478 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7297634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7297634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3724968 # Transaction distribution +system.cpu.toL2Bus.throughput 1189905456 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3725037 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1883631 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1883631 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22085580 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 22087498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 825937536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 825998912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 825998912 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1926 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22085475 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 22087401 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 825936384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 825998016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 825998016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10178169165 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10178230165 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1438500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1633750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13770459000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14189007000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 768.731270 # Cycle average of tags in use -system.cpu.icache.total_refs 391090558 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 959 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 407810.800834 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 768.731270 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.375357 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.375357 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 391090558 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 391090558 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 391090558 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 391090558 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 391090558 # number of overall hits -system.cpu.icache.overall_hits::total 391090558 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1484 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1484 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1484 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1484 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1484 # number of overall misses -system.cpu.icache.overall_misses::total 1484 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 114408499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 114408499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 114408499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 114408499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 114408499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 114408499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 391092042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 391092042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 391092042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 391092042 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 391092042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 391092042 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 770.551884 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 391083687 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 406109.747664 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 770.551884 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.376246 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.376246 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 391083687 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 391083687 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 391083687 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 391083687 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 391083687 # number of overall hits +system.cpu.icache.overall_hits::total 391083687 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1493 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1493 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1493 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1493 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1493 # number of overall misses +system.cpu.icache.overall_misses::total 1493 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108163750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108163750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108163750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108163750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108163750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108163750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391085180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 391085180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 391085180 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 391085180 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 391085180 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 391085180 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77094.675876 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77094.675876 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77094.675876 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77094.675876 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77094.675876 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77094.675876 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1730 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72447.253851 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72447.253851 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72447.253851 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72447.253851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72447.253851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72447.253851 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 340 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 346 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 525 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 525 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 525 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 525 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 525 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 525 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 959 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 959 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 959 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 80495999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 80495999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 80495999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 80495999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 80495999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 80495999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 530 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 530 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 530 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 530 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 530 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 530 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 963 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 963 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 963 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75133750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75133750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75133750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75133750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75133750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75133750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83937.433785 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83937.433785 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83937.433785 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83937.433785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83937.433785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83937.433785 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78020.508827 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78020.508827 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78020.508827 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78020.508827 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78020.508827 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78020.508827 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1933868 # number of replacements -system.cpu.l2cache.tagsinuse 31434.625731 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9058431 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1963643 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.613074 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 28082175250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14594.670874 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 26.048249 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16813.906608 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.445394 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000795 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.513120 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.959309 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6106179 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6106179 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3724968 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3724968 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108518 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108518 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7214697 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7214697 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7214697 # number of overall hits -system.cpu.l2cache.overall_hits::total 7214697 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 959 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1190496 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1191455 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 775113 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 775113 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 959 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1965609 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1966568 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 959 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1965609 # number of overall misses -system.cpu.l2cache.overall_misses::total 1966568 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 79530000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 111301241000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 111380771000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71651309000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 71651309000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 79530000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 182952550000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 183032080000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 79530000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 182952550000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 183032080000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 959 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296675 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297634 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3724968 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3724968 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.tags.replacements 1933728 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31435.165334 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9058547 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1963512 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.613441 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 28123107250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14593.465528 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.016964 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16815.682842 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.445357 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000794 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.513174 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.959325 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6106292 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6106292 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3725037 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3725037 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108452 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108452 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7214744 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7214744 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7214744 # number of overall hits +system.cpu.l2cache.overall_hits::total 7214744 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1190296 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1191259 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 775179 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 775179 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 963 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1965475 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1966438 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 963 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1965475 # number of overall misses +system.cpu.l2cache.overall_misses::total 1966438 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 74164750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 111539773000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 111613937750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71882646250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 71882646250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 74164750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 183422419250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 183496584000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 74164750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 183422419250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 183496584000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 963 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7296588 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7297551 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3725037 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3725037 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883631 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1883631 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 959 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180306 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181265 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 959 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180306 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181265 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 963 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180219 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181182 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 963 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180219 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181182 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163156 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163266 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411499 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.411499 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163130 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163241 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411534 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.411534 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214111 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214194 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214099 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214181 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214111 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214194 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82930.135558 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 93491.486742 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 93482.985929 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92439.823613 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92439.823613 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82930.135558 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93076.776714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 93071.828688 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82930.135558 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93076.776714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 93071.828688 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214099 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214181 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77014.278297 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 93707.592901 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 93694.098219 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92730.383886 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92730.383886 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77014.278297 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93322.183823 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93314.197549 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77014.278297 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93322.183823 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93314.197549 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -821,180 +821,180 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019744 # number of writebacks -system.cpu.l2cache.writebacks::total 1019744 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190496 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191455 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775113 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775113 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1965609 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1966568 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1965609 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1966568 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 67634750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96495519500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96563154250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61990929250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61990929250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 67634750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158486448750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 158554083500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 67634750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158486448750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 158554083500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019710 # number of writebacks +system.cpu.l2cache.writebacks::total 1019710 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190296 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191259 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775179 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775179 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966438 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965475 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966438 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 61969250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96454947000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96516916250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62065331750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62065331750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61969250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158520278750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158582248000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61969250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158520278750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158582248000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163156 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163266 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411499 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411499 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163130 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163241 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411534 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411534 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214194 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214099 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214181 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214194 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70526.329510 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81054.887627 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81046.413209 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79976.634697 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79976.634697 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70526.329510 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80629.692248 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80624.765327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70526.329510 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80629.692248 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80624.765327 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214099 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214181 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64350.207684 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81034.420850 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81020.933525 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80065.806414 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80065.806414 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64350.207684 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80652.401455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80644.417978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64350.207684 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80652.401455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80644.417978 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176210 # number of replacements -system.cpu.dcache.tagsinuse 4087.713956 # Cycle average of tags in use -system.cpu.dcache.total_refs 694263707 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180306 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.625334 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5139692000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.713956 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997977 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997977 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538720806 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538720806 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155542899 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155542899 # number of WriteReq hits +system.cpu.dcache.tags.replacements 9176123 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.719090 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 694209653 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9180219 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 75.620163 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5145271250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.719090 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997978 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997978 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538667558 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538667558 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155542093 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155542093 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694263705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694263705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694263705 # number of overall hits -system.cpu.dcache.overall_hits::total 694263705 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11385401 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11385401 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5185603 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5185603 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 694209651 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694209651 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694209651 # number of overall hits +system.cpu.dcache.overall_hits::total 694209651 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11383512 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11383512 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5186409 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5186409 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16571004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16571004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16571004 # number of overall misses -system.cpu.dcache.overall_misses::total 16571004 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 352412462500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 352412462500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 293618457575 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 293618457575 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 71500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 646030920075 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 646030920075 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 646030920075 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 646030920075 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 550106207 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 550106207 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16569921 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16569921 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16569921 # number of overall misses +system.cpu.dcache.overall_misses::total 16569921 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 354593331250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 354593331250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 296662127899 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 296662127899 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 461500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 461500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 651255459149 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 651255459149 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 651255459149 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 651255459149 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550051070 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550051070 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710834709 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710834709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710834709 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710834709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020697 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020697 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032263 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032263 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 710779572 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710779572 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710779572 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710779572 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020695 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020695 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032268 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.023312 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.023312 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.023312 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.023312 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30953.012766 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30953.012766 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56621.854310 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56621.854310 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38985.623326 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38985.623326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38985.623326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38985.623326 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13659344 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8231616 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 745438 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.323917 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 126.379710 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31149.730527 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31149.730527 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57199.909976 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57199.909976 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 461500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 461500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39303.473997 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39303.473997 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39303.473997 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39303.473997 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13761211 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8306103 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 744858 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.474946 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 127.521348 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3724968 # number of writebacks -system.cpu.dcache.writebacks::total 3724968 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4088719 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4088719 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3301980 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3301980 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7390699 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7390699 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7390699 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7390699 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296682 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296682 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883623 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883623 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725037 # number of writebacks +system.cpu.dcache.writebacks::total 3725037 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4086921 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4086921 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3302782 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3302782 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7389703 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7389703 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7389703 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7389703 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296591 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296591 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883627 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883627 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180305 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180305 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180305 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180305 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180470424000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 180470424000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85065304522 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85065304522 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265535728522 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 265535728522 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265535728522 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 265535728522 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9180218 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180218 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180218 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180218 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180738700500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 180738700500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85282559486 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85282559486 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 459500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 459500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 266021259986 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 266021259986 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 266021259986 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 266021259986 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013265 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013265 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24733.217646 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24733.217646 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45160.472410 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45160.472410 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28924.499624 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28924.499624 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28924.499624 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28924.499624 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012916 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012916 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012916 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012916 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24770.293484 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24770.293484 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45275.715142 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45275.715142 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 459500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 459500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28977.662620 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28977.662620 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28977.662620 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28977.662620 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 4fe8387b5..72597a7eb 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 5246772452 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 612.458646 # Cycle average of tags in use -system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.299052 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1926937 # number of replacements -system.cpu.l2cache.tagsinuse 30535.257456 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8959453 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1956729 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.578791 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.931862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1926937 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits @@ -318,15 +318,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.tagsinuse 4079.262869 # Cycle average of tags in use -system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9107638 # number of replacements +system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 48447911f..3d9ea108c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.540696 # Number of seconds simulated -sim_ticks 540696400000 # Number of ticks simulated -final_tick 540696400000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.541686 # Number of seconds simulated +sim_ticks 541686426500 # Number of ticks simulated +final_tick 541686426500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169038 # Simulator instruction rate (inst/s) -host_op_rate 188575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59174301 # Simulator tick rate (ticks/s) -host_mem_usage 246336 # Number of bytes of host memory used -host_seconds 9137.35 # Real time elapsed on the host +host_inst_rate 161069 # Simulator instruction rate (inst/s) +host_op_rate 179684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56487595 # Simulator tick rate (ticks/s) +host_mem_usage 246340 # Number of bytes of host memory used +host_seconds 9589.48 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143740608 # Number of bytes read from this memory -system.physmem.bytes_read::total 143788736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143725568 # Number of bytes read from this memory +system.physmem.bytes_read::total 143773696 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 48128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 48128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70441600 # Number of bytes written to this memory -system.physmem.bytes_written::total 70441600 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 70430528 # Number of bytes written to this memory +system.physmem.bytes_written::total 70430528 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 752 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245947 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246699 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100650 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100650 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 265843471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 265932483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89011 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89011 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 130279395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 130279395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 130279395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 265843471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 396211878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246699 # Total number of read requests seen -system.physmem.writeReqs 1100650 # Total number of write requests seen -system.physmem.cpureqs 3347359 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143788736 # Total number of bytes read from memory -system.physmem.bytesWritten 70441600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143788736 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70441600 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 675 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu.data 2245712 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246464 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100477 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100477 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 88848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 265329831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 265418679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 88848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 88848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 130020847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 130020847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 130020847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 88848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 265329831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 395439526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246464 # Total number of read requests seen +system.physmem.writeReqs 1100477 # Total number of write requests seen +system.physmem.cpureqs 3346951 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143773696 # Total number of bytes read from memory +system.physmem.bytesWritten 70430528 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143773696 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70430528 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 599 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 139594 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 136159 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 133894 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 136244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 134956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 135313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 136207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 136262 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 143860 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 146526 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 144286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 146187 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 145855 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 146147 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 142095 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 142439 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69117 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 67412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 65719 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 66245 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 66183 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 66419 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 67973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68813 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 70394 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 70993 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 70492 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 70984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 70346 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70810 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 69619 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69131 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 139699 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 136238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 133756 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 136368 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 134718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 135333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 136160 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 136095 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 143598 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 146293 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 144461 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 146176 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 145883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 146345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 142220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 142522 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 67428 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 65656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 66333 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 66095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 66425 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 67930 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68755 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 70311 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 70943 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 70521 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 70921 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 70374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70896 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 69672 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 69074 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry -system.physmem.totGap 540696152000 # Total gap between requests +system.physmem.totGap 541686363500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246699 # Categorize read packet sizes +system.physmem.readPktSize::6 2246464 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1100650 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1614963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 444775 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 139732 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 46537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100477 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1615292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 444627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 139018 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46909 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,217 +124,217 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1997676 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.204860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.811800 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 283.656472 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1593756 79.78% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 230264 11.53% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 68043 3.41% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 32667 1.64% 96.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 17678 0.88% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10939 0.55% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7434 0.37% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 7476 0.37% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4079 0.20% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3182 0.16% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2817 0.14% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2754 0.14% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1425 0.07% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1138 0.06% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 999 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 880 0.04% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 791 0.04% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 732 0.04% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 642 0.03% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 540 0.03% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 574 0.03% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 838 0.04% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3581 0.18% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 454 0.02% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 187 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 173 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 114 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 112 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 90 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 76 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 95 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 66 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 72 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 55 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 44 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 45 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 44 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 34 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 42 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 31 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 29 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 30 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 32 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 28 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 35 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 28 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 31 0.00% 99.88% # Bytes accessed per row activation +system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1997603 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.193624 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.812437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 283.653287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1593724 79.78% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 230021 11.51% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 68328 3.42% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 32466 1.63% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 17759 0.89% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 11013 0.55% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7534 0.38% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 7551 0.38% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3933 0.20% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3162 0.16% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2715 0.14% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2783 0.14% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1408 0.07% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1190 0.06% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1060 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 829 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 802 0.04% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 757 0.04% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 590 0.03% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 531 0.03% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 601 0.03% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 798 0.04% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3587 0.18% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 465 0.02% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 167 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 158 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 136 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 120 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 86 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 82 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 107 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 81 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 77 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 52 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 39 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 48 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 40 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 36 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 29 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 41 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 32 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 31 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 29 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 27 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 27 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 30 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 18 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136-3137 33 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 25 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 18 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 21 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 23 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 12 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 21 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 11 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 16 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 19 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 19 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 12 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 18 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 11 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 17 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 17 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 21 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 17 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 17 0.00% 99.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::3904-3905 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 10 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 29 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 20 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 29 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 15 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 17 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 15 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 13 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 9 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 31 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 28 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 33 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 13 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 14 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 16 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 11 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 13 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 17 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 11 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 15 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 12 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 21 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 17 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 9 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::6208-6209 17 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::6272-6273 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 6 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 15 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 16 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 15 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 11 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 10 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 9 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 9 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 15 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 14 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::7296-7297 8 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 9 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 9 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 124 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 13 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 13 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 8 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 7 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 7 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 5 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 122 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 15 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 8 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 6 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 8 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 12 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 22 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1443 0.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1997676 # Bytes accessed per row activation -system.physmem.totQLat 50306526000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 124453758500 # Sum of mem lat for all requests -system.physmem.totBusLat 11230120000 # Total cycles spent in databus access -system.physmem.totBankLat 62917112500 # Total cycles spent in bank access -system.physmem.avgQLat 22398.04 # Average queueing delay per request -system.physmem.avgBankLat 28012.66 # Average bank access latency per request +system.physmem.bytesPerActivate::8064-8065 8 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 20 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1459 0.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1997603 # Bytes accessed per row activation +system.physmem.totQLat 50283923250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 124431529500 # Sum of mem lat for all requests +system.physmem.totBusLat 11229325000 # Total cycles spent in databus access +system.physmem.totBankLat 62918281250 # Total cycles spent in bank access +system.physmem.avgQLat 22389.56 # Average queueing delay per request +system.physmem.avgBankLat 28015.17 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 55410.70 # Average memory access latency -system.physmem.avgRdBW 265.93 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 130.28 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 265.93 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 130.28 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 55404.72 # Average memory access latency +system.physmem.avgRdBW 265.42 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 130.02 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 265.42 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 130.02 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.10 # Data bus utilization in percentage +system.physmem.busUtil 3.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.23 # Average read queue length over time -system.physmem.avgWrQLen 10.44 # Average write queue length over time -system.physmem.readRowHits 1005962 # Number of row buffer hits during reads -system.physmem.writeRowHits 343028 # Number of row buffer hits during writes -system.physmem.readRowHitRate 44.79 # Row buffer hit rate for reads +system.physmem.avgWrQLen 10.65 # Average write queue length over time +system.physmem.readRowHits 1005654 # Number of row buffer hits during reads +system.physmem.writeRowHits 343066 # Number of row buffer hits during writes +system.physmem.readRowHitRate 44.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate 31.17 # Row buffer hit rate for writes -system.physmem.avgGap 161529.66 # Average gap between requests -system.membus.throughput 396211878 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1420214 # Transaction distribution -system.membus.trans_dist::ReadResp 1420214 # Transaction distribution -system.membus.trans_dist::Writeback 1100650 # Transaction distribution -system.membus.trans_dist::ReadExReq 826485 # Transaction distribution -system.membus.trans_dist::ReadExResp 826485 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 5594048 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 5594048 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 214230336 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 214230336 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214230336 # Total data (bytes) +system.physmem.avgGap 161845.21 # Average gap between requests +system.membus.throughput 395439408 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1420071 # Transaction distribution +system.membus.trans_dist::ReadResp 1420070 # Transaction distribution +system.membus.trans_dist::Writeback 1100477 # Transaction distribution +system.membus.trans_dist::ReadExReq 826393 # Transaction distribution +system.membus.trans_dist::ReadExResp 826393 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 5593404 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 5593404 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 214204160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 214204160 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214204160 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12859707750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12928469250 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21134071500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 21152142500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.9 # Layer utilization (%) -system.cpu.branchPred.lookups 304230401 # Number of BP lookups -system.cpu.branchPred.condPredicted 250450611 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15192997 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 172575058 # Number of BTB lookups -system.cpu.branchPred.BTBHits 162497547 # Number of BTB hits +system.cpu.branchPred.lookups 304298989 # Number of BP lookups +system.cpu.branchPred.condPredicted 250519406 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15198708 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 177303182 # Number of BTB lookups +system.cpu.branchPred.BTBHits 162516904 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.160506 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17547944 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 207 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.660455 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17540360 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 213 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -378,132 +378,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1081392801 # number of cpu cycles simulated +system.cpu.numCycles 1083372854 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 300338229 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2194868023 # Number of instructions fetch has processed -system.cpu.fetch.Branches 304230401 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 180045491 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 436913465 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88946702 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 165329116 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 33 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 290586210 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6069176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 973112936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494450 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.204820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 300343787 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2195221955 # Number of instructions fetch has processed +system.cpu.fetch.Branches 304298989 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 180057264 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 436998042 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88977352 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 165479201 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 101 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 290623561 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6109702 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 973376815 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494162 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.204787 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 536199557 55.10% 55.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25797166 2.65% 57.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39079992 4.02% 61.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48369850 4.97% 66.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43937617 4.52% 71.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46464611 4.77% 76.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38405061 3.95% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19061800 1.96% 81.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175797282 18.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 536378856 55.10% 55.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25841118 2.65% 57.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39079231 4.01% 61.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48353852 4.97% 66.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43959831 4.52% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46474608 4.77% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38397974 3.94% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19032697 1.96% 81.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175858648 18.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 973112936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.281332 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.029668 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 332624022 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 143219561 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 406441589 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20296480 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70531284 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46039188 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 865 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2374316328 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2545 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70531284 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 356409274 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 71650111 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21139 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 401304268 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73196860 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2310523412 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 156231 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5060521 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60179356 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 18 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2286636992 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10669420338 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10669417166 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3172 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 973376815 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.280881 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.026285 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 332723748 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 143314435 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 406466996 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20316722 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 70554914 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46046806 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 803 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2374638821 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2490 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 70554914 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 356505375 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 71902909 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 22171 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 401350772 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73040674 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2310606044 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 153145 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5003938 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60088597 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2286724696 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10669719595 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10669716841 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2754 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 580317062 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 904 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 901 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 161063694 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 625481573 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 221078320 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85817344 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70539912 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2205002740 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 913 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2019903116 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4041921 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 477338341 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1137890497 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 973112936 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.075713 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906230 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 580404766 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 862 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 859 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 161072397 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 625574992 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 221105439 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85703818 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 70396970 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2205173654 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 876 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2020003765 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4023223 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 477517821 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1138229874 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 706 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 973376815 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.075254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906645 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 289817184 29.78% 29.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153400597 15.76% 45.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161373326 16.58% 62.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120291643 12.36% 74.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123812966 12.72% 87.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73732869 7.58% 94.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38377982 3.94% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9754115 1.00% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2552254 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 290079957 29.80% 29.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153607537 15.78% 45.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161004232 16.54% 62.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120476061 12.38% 74.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123716545 12.71% 87.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73794754 7.58% 94.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38284776 3.93% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9892649 1.02% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2520304 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 973112936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 973376815 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 873823 3.65% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5574 0.02% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18262233 76.32% 80.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4786578 20.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 894925 3.74% 3.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5467 0.02% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18249723 76.22% 79.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4791929 20.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1237523467 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925246 0.05% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1237561423 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 924895 0.05% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.31% # Type of FU issued @@ -525,90 +525,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.31% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 44 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 588384414 29.13% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193069911 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 588422338 29.13% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193095054 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2019903116 # Type of FU issued -system.cpu.iq.rate 1.867872 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23928208 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011846 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5040888987 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2682531512 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957653574 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 310 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 612 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 122 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2043831169 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 155 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64629118 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2020003765 # Type of FU issued +system.cpu.iq.rate 1.864551 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23942044 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011852 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5041349349 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2682881596 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957831333 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 100 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2043945677 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64652125 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 139554804 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 275861 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192692 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46231275 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 139648223 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 271348 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192348 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46258394 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5362990 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 5367173 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70531284 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 34407025 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1609544 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2205003765 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7646058 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 625481573 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 221078320 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 851 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 482587 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 96102 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192692 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8138129 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9602458 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17740587 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988966025 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574553789 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30937091 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 70554914 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 34630118 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1599053 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2205174629 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7647376 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 625574992 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 221105439 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 814 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 476287 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 97145 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192348 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8141918 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9600574 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17742492 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1989129664 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574576777 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30874101 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 112 # number of nop insts executed -system.cpu.iew.exec_refs 764737764 # number of memory reference insts executed -system.cpu.iew.exec_branches 238303653 # Number of branches executed -system.cpu.iew.exec_stores 190183975 # Number of stores executed -system.cpu.iew.exec_rate 1.839263 # Inst execution rate -system.cpu.iew.wb_sent 1966073864 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957653696 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295701173 # num instructions producing a value -system.cpu.iew.wb_consumers 2059307469 # num instructions consuming a value +system.cpu.iew.exec_nop 99 # number of nop insts executed +system.cpu.iew.exec_refs 764789002 # number of memory reference insts executed +system.cpu.iew.exec_branches 238317780 # Number of branches executed +system.cpu.iew.exec_stores 190212225 # Number of stores executed +system.cpu.iew.exec_rate 1.836053 # Inst execution rate +system.cpu.iew.wb_sent 1966244201 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957831433 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295814578 # num instructions producing a value +system.cpu.iew.wb_consumers 2059506895 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.810308 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629193 # average fanout of values written-back +system.cpu.iew.wb_rate 1.807163 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629187 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 482029293 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 482200307 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15192188 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 902581652 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.909050 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.715598 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15197938 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 902821901 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.908542 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.715709 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 414112551 45.88% 45.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193170118 21.40% 67.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72777120 8.06% 75.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35259342 3.91% 79.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18942446 2.10% 81.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30787152 3.41% 84.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19991978 2.21% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11413503 1.26% 88.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106127442 11.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 414368116 45.90% 45.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193212165 21.40% 67.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72772864 8.06% 75.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35254508 3.90% 79.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18855841 2.09% 81.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30818249 3.41% 84.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19938130 2.21% 86.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11407177 1.26% 88.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106194851 11.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 902581652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 902821901 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -619,212 +619,212 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106127442 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106194851 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3001556757 # The number of ROB reads -system.cpu.rob.rob_writes 4480884032 # The number of ROB writes -system.cpu.timesIdled 1155619 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 108279865 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3001900611 # The number of ROB reads +system.cpu.rob.rob_writes 4481254115 # The number of ROB writes +system.cpu.timesIdled 1150610 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 109996039 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.700129 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.700129 # CPI: Total CPI of All Threads -system.cpu.ipc 1.428309 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.428309 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9959942925 # number of integer regfile reads -system.cpu.int_regfile_writes 1937523681 # number of integer regfile writes -system.cpu.fp_regfile_reads 126 # number of floating regfile reads -system.cpu.fp_regfile_writes 125 # number of floating regfile writes -system.cpu.misc_regfile_reads 737562736 # number of misc regfile reads +system.cpu.cpi 0.701411 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.701411 # CPI: Total CPI of All Threads +system.cpu.ipc 1.425698 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.425698 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9960721721 # number of integer regfile reads +system.cpu.int_regfile_writes 1937694107 # number of integer regfile writes +system.cpu.fp_regfile_reads 91 # number of floating regfile reads +system.cpu.fp_regfile_writes 89 # number of floating regfile writes +system.cpu.misc_regfile_reads 737621013 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1584099202 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7708436 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7708436 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3781153 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893485 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893485 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1562 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22983433 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 22984995 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 49984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 856466752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 856516736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856516736 # Total data (bytes) +system.cpu.toL2Bus.throughput 1581534685 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7709688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7709687 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3782769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893417 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1564 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22987414 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 22988978 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 856645824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 856695872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856695872 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10472863577 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10475876330 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1171999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1321749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14401713992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14846430743 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.7 # Layer utilization (%) -system.cpu.icache.replacements 22 # number of replacements -system.cpu.icache.tagsinuse 627.830229 # Cycle average of tags in use -system.cpu.icache.total_refs 290585017 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 781 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 372067.883483 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 627.830229 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.306558 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.306558 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 290585017 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 290585017 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 290585017 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 290585017 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 290585017 # number of overall hits -system.cpu.icache.overall_hits::total 290585017 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1193 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1193 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1193 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1193 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1193 # number of overall misses -system.cpu.icache.overall_misses::total 1193 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 86035500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 86035500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 86035500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 86035500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 86035500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 86035500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 290586210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 290586210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 290586210 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 290586210 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 290586210 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 290586210 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 22 # number of replacements +system.cpu.icache.tags.tagsinuse 629.635316 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 290622345 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 371639.827366 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 629.635316 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.307439 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.307439 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 290622345 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 290622345 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 290622345 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 290622345 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 290622345 # number of overall hits +system.cpu.icache.overall_hits::total 290622345 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1216 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1216 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1216 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1216 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1216 # number of overall misses +system.cpu.icache.overall_misses::total 1216 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 85849749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 85849749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 85849749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 85849749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 85849749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 85849749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 290623561 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 290623561 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 290623561 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 290623561 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 290623561 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 290623561 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72116.932104 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72116.932104 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72116.932104 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72116.932104 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72116.932104 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72116.932104 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70600.122533 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70600.122533 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70600.122533 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70600.122533 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70600.122533 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70600.122533 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 50.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 781 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 781 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 781 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 781 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59384001 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59384001 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59384001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59384001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59384001 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59384001 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 782 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 782 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 782 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59439751 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59439751 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59439751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59439751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59439751 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59439751 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76035.852753 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76035.852753 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76035.852753 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76035.852753 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76035.852753 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76035.852753 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76009.911765 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76009.911765 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76009.911765 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76009.911765 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76009.911765 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76009.911765 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2214008 # number of replacements -system.cpu.l2cache.tagsinuse 31545.875472 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9245067 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2243786 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.120298 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 21328593250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14315.671297 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 19.864874 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17210.339300 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.436880 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000606 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.525218 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.962704 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6288185 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6288213 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3781153 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3781153 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1067000 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1067000 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7355185 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7355213 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7355185 # number of overall hits -system.cpu.l2cache.overall_hits::total 7355213 # number of overall hits +system.cpu.l2cache.tags.replacements 2213775 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31546.363307 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9248170 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2243553 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.122109 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 21352949250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14312.491305 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.144724 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 17213.727277 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.436783 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000615 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.525321 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.962719 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6289580 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6289609 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3782769 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3782769 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1067024 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1067024 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7356604 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7356633 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7356604 # number of overall hits +system.cpu.l2cache.overall_hits::total 7356633 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 753 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1419470 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1420223 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 826485 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 826485 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1419326 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1420079 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 826393 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826393 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 753 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2245955 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2246708 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2245719 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2246472 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 753 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2245955 # number of overall misses -system.cpu.l2cache.overall_misses::total 2246708 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58316000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 138202856500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 138261172500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84038252500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 84038252500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58316000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 222241109000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 222299425000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58316000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 222241109000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 222299425000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 781 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7707655 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7708436 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3781153 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3781153 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893485 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1893485 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 781 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9601140 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9601921 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 781 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9601140 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9601921 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964149 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184164 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.184243 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436489 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.436489 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964149 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.233926 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.233985 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964149 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.233926 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.233985 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77444.887118 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 97362.294730 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 97351.734552 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101681.521746 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101681.521746 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77444.887118 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98951.719424 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98944.511258 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77444.887118 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98951.719424 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98944.511258 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.data 2245719 # number of overall misses +system.cpu.l2cache.overall_misses::total 2246472 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58361250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 138416431000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 138474792250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84266311250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 84266311250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 58361250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 222682742250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 222741103500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 58361250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 222682742250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 222741103500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 782 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7708906 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7709688 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3782769 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3782769 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893417 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1893417 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 782 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9602323 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9603105 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 782 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9602323 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9603105 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.962916 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184115 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.184194 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436456 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.436456 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962916 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.233872 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.233932 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962916 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.233872 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.233932 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77504.980080 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 97522.648778 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 97512.034366 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101968.810542 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101968.810542 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77504.980080 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99158.773760 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 99151.515576 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77504.980080 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99158.773760 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 99151.515576 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,187 +833,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1100650 # number of writebacks -system.cpu.l2cache.writebacks::total 1100650 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1100477 # number of writebacks +system.cpu.l2cache.writebacks::total 1100477 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 752 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419462 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1420214 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826485 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 826485 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419319 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1420071 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826393 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 826393 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 752 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2245947 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2246699 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2245712 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2246464 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 752 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2245947 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2246699 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48914000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 120590551250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120639465250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73785244750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73785244750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48914000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 194375796000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 194424710000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48914000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 194375796000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 194424710000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962868 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184163 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184242 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436489 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436489 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962868 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233925 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.233984 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962868 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233925 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.233984 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65045.212766 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84955.110633 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 84944.568389 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89275.963569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89275.963569 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65045.212766 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86545.139311 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86537.943000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65045.212766 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86545.139311 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86537.943000 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 2245712 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2246464 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48787000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 120499016750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120547803750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73852563750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73852563750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48787000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 194351580500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 194400367500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48787000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 194351580500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 194400367500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184114 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184193 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436456 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436456 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233872 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233931 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233872 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233931 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64876.329787 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84899.178233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 84888.575113 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89367.363651 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89367.363651 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9597044 # number of replacements -system.cpu.dcache.tagsinuse 4088.193523 # Cycle average of tags in use -system.cpu.dcache.total_refs 655932792 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9601140 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.318220 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3513476000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4088.193523 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998094 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998094 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 488973029 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 488973029 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166959638 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166959638 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 9598226 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.205485 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 655929620 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9602322 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 68.309480 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3516509250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.205485 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998097 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998097 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 488969047 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 488969047 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166960447 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166960447 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 655932667 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 655932667 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 655932667 # number of overall hits -system.cpu.dcache.overall_hits::total 655932667 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11505709 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11505709 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5626409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5626409 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 655929494 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 655929494 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 655929494 # number of overall hits +system.cpu.dcache.overall_hits::total 655929494 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11507818 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11507818 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5625600 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5625600 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17132118 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17132118 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17132118 # number of overall misses -system.cpu.dcache.overall_misses::total 17132118 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 379498751500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 379498751500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 307395824029 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 307395824029 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 651000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 651000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 686894575529 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 686894575529 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 686894575529 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 686894575529 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500478738 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500478738 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17133418 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17133418 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17133418 # number of overall misses +system.cpu.dcache.overall_misses::total 17133418 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 381897864985 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 381897864985 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 310946372440 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 310946372440 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 233500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 233500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 692844237425 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 692844237425 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 692844237425 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 692844237425 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500476865 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500476865 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673064785 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673064785 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673064785 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673064785 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032601 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032601 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025454 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025454 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025454 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025454 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32983.517270 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32983.517270 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54634.461169 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54634.461169 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 217000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 217000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40093.967105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40093.967105 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29400681 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3494014 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1217576 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673062912 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673062912 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673062912 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673062912 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022994 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022994 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032596 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032596 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025456 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025456 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025456 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025456 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33185.949325 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33185.949325 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55273.459265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55273.459265 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40438.179786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40438.179786 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29551948 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3560628 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1217583 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.146896 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 53.645121 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.270993 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 54.667874 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781153 # number of writebacks -system.cpu.dcache.writebacks::total 3781153 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798054 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3798054 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732924 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3732924 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3782769 # number of writebacks +system.cpu.dcache.writebacks::total 3782769 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798912 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3798912 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732183 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3732183 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7530978 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7530978 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7530978 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7530978 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707655 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7707655 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893485 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893485 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601140 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210632290508 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 210632290508 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97135590826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 97135590826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 307767881334 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 307767881334 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 307767881334 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 307767881334 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7531095 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7531095 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7531095 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7531095 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708906 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708906 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893417 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893417 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602323 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602323 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602323 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602323 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210908812007 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 210908812007 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97317389015 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 97317389015 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 308226201022 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 308226201022 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 308226201022 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 308226201022 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27327.674955 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27327.674955 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51299.899828 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51299.899828 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014267 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014267 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27359.110619 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27359.110619 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51397.758135 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51397.758135 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 7f261f2f5..991abe176 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 4782410230 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 7 # number of replacements -system.cpu.icache.tagsinuse 514.976015 # Cycle average of tags in use -system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.251453 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 7 # number of replacements +system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1926075 # number of replacements -system.cpu.l2cache.tagsinuse 30987.094489 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8967572 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1955843 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.585016 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.945651 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1926075 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9111140 # number of replacements -system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use -system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9111140 # number of replacements +system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 136c3d430..cc029b4bd 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -77,15 +77,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 11765161052 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 555.705054 # Cycle average of tags in use -system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.271340 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 10 # number of replacements +system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits @@ -155,19 +155,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1926197 # number of replacements -system.cpu.l2cache.tagsinuse 31136.249379 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.950203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1926197 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits @@ -290,15 +290,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.tagsinuse 4084.587030 # Cycle average of tags in use -system.cpu.dcache.total_refs 1668600407 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9108581 # number of replacements +system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits |