diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
| commit | 74553c7d3fc5430752c0c08f2b319a99fb7ed632 (patch) | |
| tree | 79b2a309fff0edaf1ef3e9aa62656904c3351650 /tests/long/se/60.bzip2/ref | |
| parent | 3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (diff) | |
| download | gem5-74553c7d3fc5430752c0c08f2b319a99fb7ed632.tar.xz | |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
Diffstat (limited to 'tests/long/se/60.bzip2/ref')
9 files changed, 2356 insertions, 1728 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index e0742a983..24ed3058e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.993430 # Number of seconds simulated -sim_ticks 993429839500 # Number of ticks simulated -final_tick 993429839500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.015958 # Number of seconds simulated +sim_ticks 1015958135500 # Number of ticks simulated +final_tick 1015958135500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61068 # Simulator instruction rate (inst/s) -host_op_rate 61068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33337374 # Simulator tick rate (ticks/s) -host_mem_usage 271484 # Number of bytes of host memory used -host_seconds 29799.28 # Real time elapsed on the host +host_inst_rate 102863 # Simulator instruction rate (inst/s) +host_op_rate 102863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57427110 # Simulator tick rate (ticks/s) +host_mem_usage 225152 # Number of bytes of host memory used +host_seconds 17691.26 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory -system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125365184 # Number of bytes read from this memory +system.physmem.bytes_read::total 125420160 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65155584 # Number of bytes written to this memory -system.physmem.bytes_written::total 65155584 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory +system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018056 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018056 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 126194172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 126249512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55340 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55340 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 65586498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 65586498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 65586498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 126194172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 191836009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959688 # Total number of read requests seen -system.physmem.writeReqs 1018056 # Total number of write requests seen -system.physmem.cpureqs 2977747 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125420032 # Total number of bytes read from memory -system.physmem.bytesWritten 65155584 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65155584 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 583 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu.data 1958831 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959690 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 54112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 123396014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 123450126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54112 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54112 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 64132280 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 64132280 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 64132280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 123396014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 187582407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959690 # Total number of read requests seen +system.physmem.writeReqs 1018058 # Total number of write requests seen +system.physmem.cpureqs 2977748 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125420160 # Total number of bytes read from memory +system.physmem.bytesWritten 65155712 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125420160 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 578 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122178 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 121799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 121645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 123762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123293 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122178 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 120330 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 121053 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 121887 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 121114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 123048 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 125176 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 123788 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 122723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123934 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63389 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 62256 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 62952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63764 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 64028 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63369 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 63391 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63292 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64555 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64147 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 63646 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64277 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 118716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 114074 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 116204 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 117698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 117773 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 117508 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 119859 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 124486 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 126960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 130063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 128617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 130264 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 125937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 125207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 122563 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123183 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 61224 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 61467 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 60558 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 61216 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 61647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63085 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 64137 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 65614 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 65334 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 65770 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 65297 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 65611 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64203 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 64552 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64187 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3 # Number of times wr buffer was full causing retry -system.physmem.totGap 993429787500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1015958077500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1959688 # Categorize read packet sizes +system.physmem.readPktSize::6 1959690 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1018056 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1630073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 205372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 87756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1018058 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1654417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 206034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 74348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,15 +124,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 41526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 43761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see @@ -147,65 +147,214 @@ system.physmem.wrQLenPdf::19 44263 # Wh system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.totQLat 35756114000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 104195196500 # Sum of mem lat for all requests -system.physmem.totBusLat 9795525000 # Total cycles spent in databus access -system.physmem.totBankLat 58643557500 # Total cycles spent in bank access -system.physmem.avgQLat 18251.25 # Average queueing delay per request -system.physmem.avgBankLat 29933.85 # Average bank access latency per request +system.physmem.wrQLenPdf::23 1545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1724238 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 110.484683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.063313 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.326643 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1380958 80.09% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 190861 11.07% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 56628 3.28% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 27570 1.60% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15749 0.91% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10044 0.58% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6620 0.38% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6559 0.38% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3696 0.21% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 2923 0.17% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2676 0.16% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2682 0.16% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1400 0.08% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1070 0.06% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1040 0.06% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 917 0.05% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 816 0.05% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 821 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 760 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 561 0.03% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 626 0.04% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 841 0.05% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3634 0.21% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 546 0.03% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 235 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 177 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 137 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 143 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 89 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 86 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 92 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 72 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 67 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 60 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 57 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 45 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 52 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 34 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 29 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 31 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 19 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 27 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 23 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 16 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 31 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 31 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 24 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 13 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 15 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 19 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 18 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 13 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 23 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 24 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 19 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 13 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 8 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 8 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 24 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 11 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 18 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 6 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 9 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 16 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 19 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 19 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 11 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 7 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 9 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 20 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 9 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 7 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 11 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 10 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 13 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 14 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 14 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 4 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 4 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 18 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 115 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 10 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 19 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 14 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1430 0.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1724238 # Bytes accessed per row activation +system.physmem.totQLat 33987005500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 98689973000 # Sum of mem lat for all requests +system.physmem.totBusLat 9795560000 # Total cycles spent in databus access +system.physmem.totBankLat 54907407500 # Total cycles spent in bank access +system.physmem.avgQLat 17348.17 # Average queueing delay per request +system.physmem.avgBankLat 28026.68 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53185.10 # Average memory access latency -system.physmem.avgRdBW 126.25 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 65.59 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 126.25 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 65.59 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 50374.85 # Average memory access latency +system.physmem.avgRdBW 123.45 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 64.13 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 123.45 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 64.13 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.50 # Data bus utilization in percentage +system.physmem.busUtil 1.47 # Data bus utilization in percentage system.physmem.avgRdQLen 0.10 # Average read queue length over time -system.physmem.avgWrQLen 10.25 # Average write queue length over time -system.physmem.readRowHits 770910 # Number of row buffer hits during reads -system.physmem.writeRowHits 285915 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.08 # Row buffer hit rate for writes -system.physmem.avgGap 333618.27 # Average gap between requests -system.cpu.branchPred.lookups 326686623 # Number of BP lookups -system.cpu.branchPred.condPredicted 252728421 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 138236618 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 220072192 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135769528 # Number of BTB hits +system.physmem.avgWrQLen 10.57 # Average write queue length over time +system.physmem.readRowHits 900967 # Number of row buffer hits during reads +system.physmem.writeRowHits 351956 # Number of row buffer hits during writes +system.physmem.readRowHitRate 45.99 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.57 # Row buffer hit rate for writes +system.physmem.avgGap 341183.36 # Average gap between requests +system.membus.throughput 187582407 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1178392 # Transaction distribution +system.membus.trans_dist::ReadResp 1178392 # Transaction distribution +system.membus.trans_dist::Writeback 1018058 # Transaction distribution +system.membus.trans_dist::ReadExReq 781298 # Transaction distribution +system.membus.trans_dist::ReadExResp 781298 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 4937438 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4937438 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575872 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 190575872 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190575872 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11748266000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 18466425750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.8 # Layer utilization (%) +system.cpu.branchPred.lookups 326521750 # Number of BP lookups +system.cpu.branchPred.condPredicted 252556520 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 138229412 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 220084071 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135399986 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.693177 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.521938 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444795652 # DTB read hits +system.cpu.dtb.read_hits 444838557 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449692730 # DTB read accesses -system.cpu.dtb.write_hits 160833314 # DTB write hits +system.cpu.dtb.read_accesses 449735635 # DTB read accesses +system.cpu.dtb.write_hits 160846849 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162534618 # DTB write accesses -system.cpu.dtb.data_hits 605628966 # DTB hits +system.cpu.dtb.write_accesses 162548153 # DTB write accesses +system.cpu.dtb.data_hits 605685406 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612227348 # DTB accesses -system.cpu.itb.fetch_hits 231949721 # ITB hits +system.cpu.dtb.data_accesses 612283788 # DTB accesses +system.cpu.itb.fetch_hits 231915406 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231949743 # ITB accesses +system.cpu.itb.fetch_accesses 231915428 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,34 +368,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1986859680 # number of cpu cycles simulated +system.cpu.numCycles 2031916272 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172586758 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154099865 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667601840 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172213740 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154308010 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667655233 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043804457 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043857850 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651738878 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617884917 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 120537665 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 11100495 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 131638160 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 83561944 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.170119 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139346059 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651713796 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617884761 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120483996 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11146958 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131630954 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83569020 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.166808 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139383608 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1741702087 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1742160374 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7484450 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 415164157 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571695523 # Number of cycles cpu stages are processed. -system.cpu.activity 79.104505 # Percentage of cycles cpu is active +system.cpu.timesIdled 7533550 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 460194055 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571722217 # Number of cycles cpu stages are processed. +system.cpu.activity 77.351722 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -258,191 +407,211 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.091813 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.116572 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.091813 # CPI: Total CPI of All Threads -system.cpu.ipc 0.915908 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.116572 # CPI: Total CPI of All Threads +system.cpu.ipc 0.895598 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.915908 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 800109422 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186750258 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.729948 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1053226597 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933633083 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.990389 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1014475629 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972384051 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.940751 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1577240024 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409619656 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.616436 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 965534852 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021324828 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.403974 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.895598 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 845299879 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186616393 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.398882 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1098097789 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933818483 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.957528 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1059529924 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972386348 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 47.855631 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1622292075 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409624197 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.159502 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 1010582157 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021334115 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.264577 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 667.831181 # Cycle average of tags in use -system.cpu.icache.total_refs 231948615 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 668.704565 # Cycle average of tags in use +system.cpu.icache.total_refs 231914267 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270021.670547 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 269981.684517 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 667.831181 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.326089 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.326089 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231948615 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231948615 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231948615 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231948615 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231948615 # number of overall hits -system.cpu.icache.overall_hits::total 231948615 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1106 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1106 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1106 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1106 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1106 # number of overall misses -system.cpu.icache.overall_misses::total 1106 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62073500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62073500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62073500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62073500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62073500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62073500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231949721 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231949721 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231949721 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231949721 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231949721 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231949721 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 668.704565 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.326516 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56124.321881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56124.321881 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72548.726953 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72548.726953 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72548.726953 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72548.726953 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72548.726953 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72548.726953 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413467 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.413467 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413469 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413469 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214985 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.215059 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214986 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.215060 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58616.414435 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70573.913553 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70565.197006 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84666.853109 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84666.853109 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58616.414435 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76195.019575 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76187.314256 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58616.414435 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76195.019575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76187.314256 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214986 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.215060 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74564.027939 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88164.973296 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 88155.058758 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101135.001626 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101135.001626 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74564.027939 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93338.189971 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93329.960606 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74564.027939 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93338.189971 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93329.960606 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,86 +620,86 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1018056 # number of writebacks -system.cpu.l2cache.writebacks::total 1018056 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1018058 # number of writebacks +system.cpu.l2cache.writebacks::total 1018058 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177531 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1178390 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177533 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1178392 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781298 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 781298 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1958829 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1959688 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958831 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1959690 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39688224 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68425761624 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68465449848 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56456219513 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56456219513 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39688224 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124881981137 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 124921669361 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39688224 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124881981137 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 124921669361 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958831 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959690 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53393500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 89166260000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89219653500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69332641250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69332641250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53393500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158498901250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158552294750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53393500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158498901250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158552294750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163051 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413467 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413469 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413469 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.215060 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46202.821886 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58109.520364 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58100.840849 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72259.521352 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72259.521352 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46202.821886 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63753.385894 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63745.692866 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46202.821886 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63753.385894 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63745.692866 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.215060 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62157.741560 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75722.939400 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75713.050920 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88740.328594 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88740.328594 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62157.741560 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80915.046398 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80906.824421 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62157.741560 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80915.046398 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80906.824421 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107366 # number of replacements -system.cpu.dcache.tagsinuse 4082.260687 # Cycle average of tags in use -system.cpu.dcache.total_refs 593512555 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111462 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.139113 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12624962000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.260687 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996646 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996646 # Average percentage of cache occupancy +system.cpu.dcache.replacements 9107352 # number of replacements +system.cpu.dcache.tagsinuse 4082.468819 # Cycle average of tags in use +system.cpu.dcache.total_refs 593298146 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.115682 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12678178000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.468819 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996696 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996696 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437268759 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437268759 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156243796 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156243796 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593512555 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593512555 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593512555 # number of overall hits -system.cpu.dcache.overall_hits::total 593512555 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 156029387 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156029387 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593298146 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593298146 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593298146 # number of overall hits +system.cpu.dcache.overall_hits::total 593298146 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7326904 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7326904 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4484706 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4484706 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 11811610 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11811610 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11811610 # number of overall misses -system.cpu.dcache.overall_misses::total 11811610 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 167226851000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 167226851000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 202255523500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 202255523500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 369482374500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 369482374500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 369482374500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 369482374500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 4699115 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4699115 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 12026019 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12026019 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12026019 # number of overall misses +system.cpu.dcache.overall_misses::total 12026019 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 188246527500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 188246527500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 260860363500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 260860363500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 449106891000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 449106891000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 449106891000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 449106891000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -541,54 +710,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027902 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027902 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019513 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019513 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019513 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019513 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22823.671635 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22823.671635 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45098.948181 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45098.948181 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31281.288029 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31281.288029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31281.288029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31281.288029 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13468960 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4773919 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 372025 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65739 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.204449 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.619282 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029236 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029236 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019867 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019867 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019867 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019867 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25692.506344 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25692.506344 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55512.657915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55512.657915 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37344.601817 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37344.601817 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37344.601817 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37344.601817 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15563445 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7313446 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 432083 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 73150 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.019573 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 99.978756 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693289 # number of writebacks -system.cpu.dcache.writebacks::total 3693289 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104624 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104624 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595524 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2595524 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2700148 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2700148 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2700148 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2700148 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111462 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111462 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111462 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111462 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150904604500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 150904604500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79287604500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 79287604500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230192209000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 230192209000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230192209000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 230192209000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3693280 # number of writebacks +system.cpu.dcache.writebacks::total 3693280 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104632 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104632 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2809939 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2809939 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2914571 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2914571 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2914571 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2914571 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222272 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222272 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889176 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889176 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171613180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171613180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92147472000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92147472000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263760652000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 263760652000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263760652000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 263760652000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -597,14 +766,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20894.316545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20894.316545 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41969.277973 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41969.277973 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25264.025576 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25264.025576 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25264.025576 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25264.025576 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23761.661150 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23761.661150 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48776.541730 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48776.541730 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28948.269474 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28948.269474 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28948.269474 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28948.269474 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 19663f540..88a7eaf62 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.665535 # Number of seconds simulated -sim_ticks 665534636500 # Number of ticks simulated -final_tick 665534636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.693021 # Number of seconds simulated +sim_ticks 693021015500 # Number of ticks simulated +final_tick 693021015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68112 # Simulator instruction rate (inst/s) -host_op_rate 68112 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26111525 # Simulator tick rate (ticks/s) -host_mem_usage 272636 # Number of bytes of host memory used -host_seconds 25488.16 # Real time elapsed on the host +host_inst_rate 172458 # Simulator instruction rate (inst/s) +host_op_rate 172458 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68844519 # Simulator tick rate (ticks/s) +host_mem_usage 228224 # Number of bytes of host memory used +host_seconds 10066.47 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 62080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125797184 # Number of bytes read from this memory -system.physmem.bytes_read::total 125859264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65262656 # Number of bytes written to this memory -system.physmem.bytes_written::total 65262656 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 970 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965581 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966551 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019729 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019729 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 189016735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 189110013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93278 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93278 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98060495 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98060495 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98060495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 189016735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 287170509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966551 # Total number of read requests seen -system.physmem.writeReqs 1019729 # Total number of write requests seen -system.physmem.cpureqs 2986294 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125859264 # Total number of bytes read from memory -system.physmem.bytesWritten 65262656 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125859264 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65262656 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 565 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125798976 # Number of bytes read from this memory +system.physmem.bytes_read::total 125860352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65263616 # Number of bytes written to this memory +system.physmem.bytes_written::total 65263616 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965609 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966568 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019744 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019744 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 88563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 181522599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 181611162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 88563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 88563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 94172636 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 94172636 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 94172636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 88563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 181522599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 275783798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966568 # Total number of read requests seen +system.physmem.writeReqs 1019744 # Total number of write requests seen +system.physmem.cpureqs 2986322 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125860352 # Total number of bytes read from memory +system.physmem.bytesWritten 65263616 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125860352 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65263616 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 585 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 122308 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 122187 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 124219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123641 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122574 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 120687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 121413 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121604 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122268 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 121464 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 123454 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 125591 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 124312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 123151 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 124443 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63482 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 62396 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63113 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63858 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 64137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63872 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63465 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63448 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 63476 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63820 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63370 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64242 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64662 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64289 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 63740 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64359 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 119008 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 114438 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 116555 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 118046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 118149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 117808 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 120225 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 124916 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 127564 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 130488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 129072 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 130765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 126644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 125671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 122973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123661 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 61280 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 61566 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 60655 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 61327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 61759 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63170 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 64220 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 65701 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 65486 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 65876 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 65409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 65716 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64323 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64319 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 64636 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64301 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 14 # Number of times wr buffer was full causing retry -system.physmem.totGap 665534568000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry +system.physmem.totGap 693020927000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966551 # Categorize read packet sizes +system.physmem.readPktSize::6 1966568 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1019729 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1625924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 234682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 77512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019744 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1645883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 229621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,22 +124,22 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 43951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 43412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44337 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see @@ -147,65 +147,214 @@ system.physmem.wrQLenPdf::19 44336 # Wh system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see -system.physmem.totQLat 34329674750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 102455589750 # Sum of mem lat for all requests -system.physmem.totBusLat 9829930000 # Total cycles spent in databus access -system.physmem.totBankLat 58295985000 # Total cycles spent in bank access -system.physmem.avgQLat 17461.81 # Average queueing delay per request -system.physmem.avgBankLat 29652.29 # Average bank access latency per request +system.physmem.wrQLenPdf::23 925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1725071 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 110.744307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.207489 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.283228 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1378927 79.93% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 191993 11.13% 91.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 57386 3.33% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 28102 1.63% 96.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15937 0.92% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 9770 0.57% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6740 0.39% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6906 0.40% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3659 0.21% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3018 0.17% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2639 0.15% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2655 0.15% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1401 0.08% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1109 0.06% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1069 0.06% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 819 0.05% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 853 0.05% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 845 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 758 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 637 0.04% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 729 0.04% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 683 0.04% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3600 0.21% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 572 0.03% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 238 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 183 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 143 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 137 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 83 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 102 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 118 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 69 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 71 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 61 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 48 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 55 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 46 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 41 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 53 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 35 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 34 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 36 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 52 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 44 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 22 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 36 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 29 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 20 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 25 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 30 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 21 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 16 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 19 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 21 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 15 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 13 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 10 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 20 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 21 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 25 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 12 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 15 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 16 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 13 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 23 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 19 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 8 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 7 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 9 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 8 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 7 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 11 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 5 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 8 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 17 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 4 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 9 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 26 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 18 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 11 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 13 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 15 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 118 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 15 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 12 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 5 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 16 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1427 0.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1725071 # Bytes accessed per row activation +system.physmem.totQLat 33871310750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 97989140750 # Sum of mem lat for all requests +system.physmem.totBusLat 9829915000 # Total cycles spent in databus access +system.physmem.totBankLat 54287915000 # Total cycles spent in bank access +system.physmem.avgQLat 17228.69 # Average queueing delay per request +system.physmem.avgBankLat 27613.62 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52114.10 # Average memory access latency -system.physmem.avgRdBW 189.11 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 98.06 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 189.11 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 98.06 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 49842.31 # Average memory access latency +system.physmem.avgRdBW 181.61 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 94.17 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 181.61 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 94.17 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.24 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.52 # Average write queue length over time -system.physmem.readRowHits 776084 # Number of row buffer hits during reads -system.physmem.writeRowHits 286116 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes -system.physmem.avgGap 222864.09 # Average gap between requests -system.cpu.branchPred.lookups 381314788 # Number of BP lookups -system.cpu.branchPred.condPredicted 296330051 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16069549 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262009169 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259516575 # Number of BTB hits +system.physmem.busUtil 2.15 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.14 # Average read queue length over time +system.physmem.avgWrQLen 11.24 # Average write queue length over time +system.physmem.readRowHits 907929 # Number of row buffer hits during reads +system.physmem.writeRowHits 352711 # Number of row buffer hits during writes +system.physmem.readRowHitRate 46.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.59 # Row buffer hit rate for writes +system.physmem.avgGap 232065.81 # Average gap between requests +system.membus.throughput 275783798 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191455 # Transaction distribution +system.membus.trans_dist::ReadResp 1191455 # Transaction distribution +system.membus.trans_dist::Writeback 1019744 # Transaction distribution +system.membus.trans_dist::ReadExReq 775113 # Transaction distribution +system.membus.trans_dist::ReadExResp 775113 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 4952880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4952880 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 191123968 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 191123968 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191123968 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11815530000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 18578292500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.cpu.branchPred.lookups 381829258 # Number of BP lookups +system.cpu.branchPred.condPredicted 296791594 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16090940 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262534664 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259935463 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.048662 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24704658 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2987 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.009959 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24706233 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3077 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613784934 # DTB read hits -system.cpu.dtb.read_misses 11255491 # DTB read misses +system.cpu.dtb.read_hits 613998993 # DTB read hits +system.cpu.dtb.read_misses 11257757 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625040425 # DTB read accesses -system.cpu.dtb.write_hits 212268072 # DTB write hits -system.cpu.dtb.write_misses 7147147 # DTB write misses +system.cpu.dtb.read_accesses 625256750 # DTB read accesses +system.cpu.dtb.write_hits 212346659 # DTB write hits +system.cpu.dtb.write_misses 7132839 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219415219 # DTB write accesses -system.cpu.dtb.data_hits 826053006 # DTB hits -system.cpu.dtb.data_misses 18402638 # DTB misses +system.cpu.dtb.write_accesses 219479498 # DTB write accesses +system.cpu.dtb.data_hits 826345652 # DTB hits +system.cpu.dtb.data_misses 18390596 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844455644 # DTB accesses -system.cpu.itb.fetch_hits 390718533 # ITB hits -system.cpu.itb.fetch_misses 44 # ITB misses +system.cpu.dtb.data_accesses 844736248 # DTB accesses +system.cpu.itb.fetch_hits 391092043 # ITB hits +system.cpu.itb.fetch_misses 41 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 390718577 # ITB accesses +system.cpu.itb.fetch_accesses 391092084 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,139 +368,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1331069274 # number of cpu cycles simulated +system.cpu.numCycles 1386042032 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402166078 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3159376011 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381314788 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284221233 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574162316 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140275246 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 173581201 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1319 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 44 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 390718533 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8058234 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1266376452 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494816 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402569601 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3162430835 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381829258 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284641696 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574759222 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140771117 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 196436536 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1508 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 391092043 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8064861 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1290645563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.450271 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.141948 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 692214136 54.66% 54.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42617572 3.37% 58.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21747694 1.72% 59.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39672890 3.13% 62.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129244053 10.21% 73.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61517613 4.86% 77.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38549434 3.04% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28120980 2.22% 83.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212692080 16.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 715886341 55.47% 55.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42669337 3.31% 58.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21804756 1.69% 60.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39713212 3.08% 63.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129418344 10.03% 73.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61537126 4.77% 78.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38572706 2.99% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28132820 2.18% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212910921 16.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1266376452 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286473 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.373562 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 433844233 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 155093027 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542385824 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18588672 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116464696 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58295749 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 820 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3086840549 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2050 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116464696 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 456708081 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 101341646 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 4855 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535414758 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56442416 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3004830564 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 566431 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1735808 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 50354826 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2246618583 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3897053047 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3895813174 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1239873 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1290645563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.275482 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.281627 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434522823 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 177728995 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542687123 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18828896 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116877726 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58348631 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 887 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3089538872 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2030 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116877726 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457522679 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 122552150 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7258 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535724767 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 57960983 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3007258855 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 610716 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1836419 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51661727 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2248310547 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3900270173 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3899027162 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1243011 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 870415620 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 152 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 150 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121369541 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679327249 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255330910 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67787749 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36895317 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2723405811 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 116 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2508867042 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3090361 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 978262694 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 414978517 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 87 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1266376452 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981138 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.973034 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 872107584 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 171 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 169 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123506231 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679721710 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255512825 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67679975 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36990562 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2725376863 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 131 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509736857 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3186715 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 980131211 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 416747410 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 102 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1290645563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.944559 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.970905 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 426237987 33.66% 33.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201818534 15.94% 49.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185298881 14.63% 64.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153239824 12.10% 76.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133194400 10.52% 86.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 81007004 6.40% 93.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65236623 5.15% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15246676 1.20% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5096523 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 448740391 34.77% 34.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203240605 15.75% 50.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185935244 14.41% 64.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153422938 11.89% 76.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133053941 10.31% 87.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80846786 6.26% 93.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65044265 5.04% 98.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15249478 1.18% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5111915 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1266376452 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1290645563 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2152645 11.65% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11915798 64.49% 76.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4409146 23.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2163556 11.71% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11907011 64.43% 76.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4409853 23.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643427997 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 106 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643982989 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 103 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 257 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 155 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 24 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 270 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 158 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued @@ -373,84 +522,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641412571 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224025892 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641664411 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224088858 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2508867042 # Type of FU issued -system.cpu.iq.rate 1.884851 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18477589 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007365 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6303778600 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3700560143 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2412458758 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1899886 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1215836 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 851322 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2526405516 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 939115 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62596425 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509736857 # Type of FU issued +system.cpu.iq.rate 1.810722 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18480420 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007363 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6329888754 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3704398033 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413211688 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1897658 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1216996 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 850977 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527279284 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 937993 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62596809 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234731586 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 264011 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 109067 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94602408 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235126047 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263685 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 108576 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94784323 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 66 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1508918 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 179 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1583083 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116464696 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 45220798 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1155063 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2865407567 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8873020 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679327249 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255330910 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 116 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 297140 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16951 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 109067 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10347954 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8554699 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18902653 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2461486866 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625041025 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47380176 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116877726 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 58990263 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1298967 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2867530467 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8941640 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679721710 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255512825 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 131 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 325521 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17838 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 108576 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10366897 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8557633 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18924530 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462313409 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625257301 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47423448 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142001640 # number of nop insts executed -system.cpu.iew.exec_refs 844456273 # number of memory reference insts executed -system.cpu.iew.exec_branches 300755716 # Number of branches executed -system.cpu.iew.exec_stores 219415248 # Number of stores executed -system.cpu.iew.exec_rate 1.849255 # Inst execution rate -system.cpu.iew.wb_sent 2441275432 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413310080 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388594213 # num instructions producing a value -system.cpu.iew.wb_consumers 1764461796 # num instructions consuming a value +system.cpu.iew.exec_nop 142153473 # number of nop insts executed +system.cpu.iew.exec_refs 844736823 # number of memory reference insts executed +system.cpu.iew.exec_branches 300880868 # Number of branches executed +system.cpu.iew.exec_stores 219479522 # Number of stores executed +system.cpu.iew.exec_rate 1.776507 # Inst execution rate +system.cpu.iew.wb_sent 2442002538 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2414062665 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388567182 # num instructions producing a value +system.cpu.iew.wb_consumers 1764588303 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.813061 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786979 # average fanout of values written-back +system.cpu.iew.wb_rate 1.741695 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 824506637 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 827045847 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16068781 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1149911756 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.582539 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.513361 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16090137 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1173767837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.550375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.495661 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 636560643 55.36% 55.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174447924 15.17% 70.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86151555 7.49% 78.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53744022 4.67% 82.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34427444 2.99% 85.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25274936 2.20% 87.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21893247 1.90% 89.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22942792 2.00% 91.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94469193 8.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 659878599 56.22% 56.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174801477 14.89% 71.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86143733 7.34% 78.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53556827 4.56% 83.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34704625 2.96% 85.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26036675 2.22% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21629651 1.84% 90.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22889079 1.95% 91.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94127171 8.02% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1149911756 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1173767837 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,189 +610,209 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94469193 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94127171 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3613950126 # The number of ROB reads -system.cpu.rob.rob_writes 5405135678 # The number of ROB writes -system.cpu.timesIdled 818095 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64692822 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3640687439 # The number of ROB reads +system.cpu.rob.rob_writes 5410628429 # The number of ROB writes +system.cpu.timesIdled 939185 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 95396469 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.766726 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.766726 # CPI: Total CPI of All Threads -system.cpu.ipc 1.304248 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.304248 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3317233936 # number of integer regfile reads -system.cpu.int_regfile_writes 1931587557 # number of integer regfile writes -system.cpu.fp_regfile_reads 30073 # number of floating regfile reads -system.cpu.fp_regfile_writes 508 # number of floating regfile writes +system.cpu.cpi 0.798391 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.798391 # CPI: Total CPI of All Threads +system.cpu.ipc 1.252519 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.252519 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3318270268 # number of integer regfile reads +system.cpu.int_regfile_writes 1932125497 # number of integer regfile writes +system.cpu.fp_regfile_reads 30353 # number of floating regfile reads +system.cpu.fp_regfile_writes 534 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.toL2Bus.throughput 1191881478 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3724968 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1883631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1883631 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1918 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22085580 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 22087498 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 825937536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 825998912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 825998912 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10178169165 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1438500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13770459000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 775.031780 # Cycle average of tags in use -system.cpu.icache.total_refs 390717051 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 970 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 402801.083505 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 768.731270 # Cycle average of tags in use +system.cpu.icache.total_refs 391090558 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 959 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 407810.800834 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 775.031780 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.378433 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.378433 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 390717051 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 390717051 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 390717051 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 390717051 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 390717051 # number of overall hits -system.cpu.icache.overall_hits::total 390717051 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1482 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1482 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1482 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1482 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1482 # number of overall misses -system.cpu.icache.overall_misses::total 1482 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 88954499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 88954499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 88954499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 88954499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 88954499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 88954499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 390718533 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 390718533 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 390718533 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 390718533 # 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number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1484 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1484 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1484 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1484 # number of overall misses +system.cpu.icache.overall_misses::total 1484 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 114408499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 114408499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 114408499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 114408499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 114408499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 114408499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391092042 # 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average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82930.135558 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93076.776714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93071.828688 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82930.135558 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93076.776714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93071.828688 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -652,180 +821,180 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019729 # number of writebacks -system.cpu.l2cache.writebacks::total 1019729 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 970 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190459 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191429 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775122 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775122 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 970 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1965581 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1966551 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 970 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1965581 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1966551 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 47610542 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 75287051777 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 75334662319 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48380240227 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48380240227 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47610542 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 123667292004 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 123714902546 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47610542 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 123667292004 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 123714902546 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019744 # number of writebacks +system.cpu.l2cache.writebacks::total 1019744 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190496 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191455 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775113 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775113 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965609 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966568 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965609 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966568 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 67634750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96495519500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96563154250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61990929250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61990929250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 67634750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158486448750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158554083500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 67634750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158486448750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158554083500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163145 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163257 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411517 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411517 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163156 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163266 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411499 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411499 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214104 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214187 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214194 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214104 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214187 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49083.032990 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63242.036708 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63230.509178 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62416.290890 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62416.290890 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49083.032990 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62916.405889 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62909.582587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49083.032990 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62916.405889 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62909.582587 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214194 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70526.329510 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81054.887627 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81046.413209 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79976.634697 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79976.634697 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70526.329510 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80629.692248 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80624.765327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70526.329510 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80629.692248 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80624.765327 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176393 # number of replacements -system.cpu.dcache.tagsinuse 4087.522074 # Cycle average of tags in use -system.cpu.dcache.total_refs 694329819 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180489 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.631028 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5069314000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.522074 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997930 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538683298 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538683298 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155646519 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155646519 # number of WriteReq hits +system.cpu.dcache.replacements 9176210 # number of replacements +system.cpu.dcache.tagsinuse 4087.713956 # Cycle average of tags in use +system.cpu.dcache.total_refs 694263707 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180306 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.625334 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5139692000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.713956 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997977 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997977 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538720806 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538720806 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155542899 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155542899 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694329817 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694329817 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694329817 # number of overall hits -system.cpu.dcache.overall_hits::total 694329817 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11282174 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11282174 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5081983 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5081983 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 694263705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694263705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694263705 # number of overall hits +system.cpu.dcache.overall_hits::total 694263705 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11385401 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11385401 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5185603 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5185603 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16364157 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16364157 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16364157 # number of overall misses -system.cpu.dcache.overall_misses::total 16364157 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 295231740500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 295231740500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 224040653758 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 224040653758 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 49500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 49500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 519272394258 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 519272394258 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 519272394258 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 519272394258 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 549965472 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 549965472 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16571004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16571004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16571004 # number of overall misses +system.cpu.dcache.overall_misses::total 16571004 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 352412462500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 352412462500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 293618457575 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 293618457575 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 71500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 646030920075 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 646030920075 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 646030920075 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 646030920075 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550106207 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550106207 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710693974 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710693974 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710693974 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710693974 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020514 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020514 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031618 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.031618 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 710834709 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710834709 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710834709 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710834709 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020697 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020697 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032263 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032263 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023026 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023026 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023026 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023026 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26167.983272 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26167.983272 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44085.282016 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44085.282016 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31732.303366 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31732.303366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31732.303366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31732.303366 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12263483 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5814647 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 736139 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65133 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.659195 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 89.273440 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.023312 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023312 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023312 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023312 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30953.012766 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30953.012766 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56621.854310 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56621.854310 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38985.623326 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38985.623326 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38985.623326 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38985.623326 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13659344 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8231616 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 745438 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.323917 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 126.379710 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725155 # number of writebacks -system.cpu.dcache.writebacks::total 3725155 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3985249 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3985249 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198420 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3198420 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7183669 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7183669 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7183669 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7183669 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296925 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296925 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883563 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883563 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3724968 # number of writebacks +system.cpu.dcache.writebacks::total 3724968 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4088719 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4088719 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3301980 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3301980 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7390699 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7390699 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7390699 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7390699 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296682 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296682 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883623 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883623 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180488 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180488 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180488 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180488 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159258474500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 159258474500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71462908450 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71462908450 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 47500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 47500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230721382950 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 230721382950 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230721382950 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 230721382950 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013268 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9180305 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180305 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180305 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180305 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180470424000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 180470424000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85065304522 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85065304522 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265535728522 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 265535728522 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265535728522 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 265535728522 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012918 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012918 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.422969 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.422969 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37940.280442 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37940.280442 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 47500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 47500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25131.712274 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25131.712274 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25131.712274 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25131.712274 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24733.217646 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24733.217646 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45160.472410 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45160.472410 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28924.499624 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28924.499624 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28924.499624 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28924.499624 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 4f12f01d2..87abf8a8a 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2288605 # Simulator instruction rate (inst/s) -host_op_rate 2288605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1148451794 # Simulator tick rate (ticks/s) -host_mem_usage 263992 # Number of bytes of host memory used -host_seconds 795.15 # Real time elapsed on the host +host_inst_rate 4050769 # Simulator instruction rate (inst/s) +host_op_rate 4050768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2032728095 # Simulator tick rate (ticks/s) +host_mem_usage 217548 # Number of bytes of host memory used +host_seconds 449.24 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 906468506 # Wr system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11068994882 # Throughput (bytes/s) +system.membus.data_through_bus 10108087278 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 56da2f7b0..4fe8387b5 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu sim_ticks 2623386226000 # Number of ticks simulated final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1056521 # Simulator instruction rate (inst/s) -host_op_rate 1056521 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1523075909 # Simulator tick rate (ticks/s) -host_mem_usage 272444 # Number of bytes of host memory used -host_seconds 1722.43 # Real time elapsed on the host +host_inst_rate 781919 # Simulator instruction rate (inst/s) +host_op_rate 781919 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1127211275 # Simulator tick rate (ticks/s) +host_mem_usage 225028 # Number of bytes of host memory used +host_seconds 2327.32 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 24836956 # To system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 72644797 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1178362 # Transaction distribution +system.membus.trans_dist::ReadResp 1178362 # Transaction distribution +system.membus.trans_dist::Writeback 1018077 # Transaction distribution +system.membus.trans_dist::ReadExReq 781301 # Transaction distribution +system.membus.trans_dist::ReadExResp 781301 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 4937403 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4937403 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190575360 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -402,5 +418,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 312415345 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1604 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916965 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 21918569 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819534784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 819586112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 819586112 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 2a4746f89..48447911f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517355 # Number of seconds simulated -sim_ticks 517355353500 # Number of ticks simulated -final_tick 517355353500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.540696 # Number of seconds simulated +sim_ticks 540696400000 # Number of ticks simulated +final_tick 540696400000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80961 # Simulator instruction rate (inst/s) -host_op_rate 90318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27118174 # Simulator tick rate (ticks/s) -host_mem_usage 288124 # Number of bytes of host memory used -host_seconds 19077.81 # Real time elapsed on the host +host_inst_rate 169038 # Simulator instruction rate (inst/s) +host_op_rate 188575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59174301 # Simulator tick rate (ticks/s) +host_mem_usage 246336 # Number of bytes of host memory used +host_seconds 9137.35 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143726656 # Number of bytes read from this memory -system.physmem.bytes_read::total 143774272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70431232 # Number of bytes written to this memory -system.physmem.bytes_written::total 70431232 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245729 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246473 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100488 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100488 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 277810319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 277902357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136137051 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136137051 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136137051 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 277810319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 414039407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246473 # Total number of read requests seen -system.physmem.writeReqs 1100488 # Total number of write requests seen -system.physmem.cpureqs 3346979 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143774272 # Total number of bytes read from memory -system.physmem.bytesWritten 70431232 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143774272 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70431232 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 670 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143740608 # Number of bytes read from this memory +system.physmem.bytes_read::total 143788736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70441600 # Number of bytes written to this memory +system.physmem.bytes_written::total 70441600 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 752 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245947 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246699 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100650 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100650 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 265843471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 265932483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89011 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89011 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 130279395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 130279395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 130279395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 265843471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 396211878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246699 # Total number of read requests seen +system.physmem.writeReqs 1100650 # Total number of write requests seen +system.physmem.cpureqs 3347359 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143788736 # Total number of bytes read from memory +system.physmem.bytesWritten 70441600 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143788736 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70441600 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 675 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 141489 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 139656 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 141525 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 141936 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 142251 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 140152 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 141094 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 140745 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 138661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 136342 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140561 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 140724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 141098 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 138976 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 138964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 141629 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69092 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 68439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69113 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 69523 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 69288 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 69039 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 68977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68383 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 67923 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 67021 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 69461 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 69311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 69094 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 68543 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 68433 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 68848 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 139594 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 136159 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 133894 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 136244 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 134956 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 135313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 136207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 136262 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 143860 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 146526 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 144286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 146187 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 145855 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 146147 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 142095 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 142439 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69117 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 67412 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 65719 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 66245 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 66183 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 66419 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 67973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68813 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 70394 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 70993 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 70492 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 70984 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 70346 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70810 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 69619 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 69131 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 18 # Number of times wr buffer was full causing retry -system.physmem.totGap 517355284500 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry +system.physmem.totGap 540696152000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246473 # Categorize read packet sizes +system.physmem.readPktSize::6 2246699 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1100488 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1563773 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 450876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 162701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100650 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1614963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 444775 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 139732 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,68 +124,217 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 44051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see -system.physmem.totQLat 51860326500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 131350914000 # Sum of mem lat for all requests -system.physmem.totBusLat 11229015000 # Total cycles spent in databus access -system.physmem.totBankLat 68261572500 # Total cycles spent in bank access -system.physmem.avgQLat 23092.11 # Average queueing delay per request -system.physmem.avgBankLat 30395.17 # Average bank access latency per request +system.physmem.wrQLenPdf::0 45615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1997676 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.204860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.811800 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 283.656472 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1593756 79.78% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 230264 11.53% 91.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 68043 3.41% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 32667 1.64% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 17678 0.88% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10939 0.55% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7434 0.37% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 7476 0.37% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4079 0.20% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3182 0.16% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2817 0.14% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2754 0.14% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1425 0.07% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1138 0.06% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 999 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 880 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 791 0.04% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 732 0.04% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 642 0.03% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 540 0.03% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 574 0.03% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 838 0.04% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3581 0.18% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 454 0.02% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 187 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 173 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 114 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 112 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 90 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 76 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 95 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 66 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 72 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 55 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 44 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 45 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 44 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 34 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 42 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 31 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 29 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 30 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 32 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 28 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 35 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 28 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 31 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 33 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 25 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 18 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 21 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 23 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 12 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 21 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 11 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 16 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 19 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 13 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 29 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 20 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 29 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 13 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 17 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 15 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 13 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 13 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 17 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 11 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 9 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 21 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 17 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 15 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 16 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 15 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 8 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 3 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 5 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 9 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 9 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 124 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 13 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 13 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 8 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 8 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 12 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 22 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1443 0.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1997676 # Bytes accessed per row activation +system.physmem.totQLat 50306526000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 124453758500 # Sum of mem lat for all requests +system.physmem.totBusLat 11230120000 # Total cycles spent in databus access +system.physmem.totBankLat 62917112500 # Total cycles spent in bank access +system.physmem.avgQLat 22398.04 # Average queueing delay per request +system.physmem.avgBankLat 28012.66 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58487.28 # Average memory access latency -system.physmem.avgRdBW 277.90 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 136.14 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 277.90 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 136.14 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 55410.70 # Average memory access latency +system.physmem.avgRdBW 265.93 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 130.28 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 265.93 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 130.28 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.23 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.25 # Average read queue length over time -system.physmem.avgWrQLen 11.18 # Average write queue length over time -system.physmem.readRowHits 827290 # Number of row buffer hits during reads -system.physmem.writeRowHits 270800 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 24.61 # Row buffer hit rate for writes -system.physmem.avgGap 154574.64 # Average gap between requests -system.cpu.branchPred.lookups 303238356 # Number of BP lookups -system.cpu.branchPred.condPredicted 249416285 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15213179 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 173189005 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161485027 # Number of BTB hits +system.physmem.busUtil 3.10 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.23 # Average read queue length over time +system.physmem.avgWrQLen 10.44 # Average write queue length over time +system.physmem.readRowHits 1005962 # Number of row buffer hits during reads +system.physmem.writeRowHits 343028 # Number of row buffer hits during writes +system.physmem.readRowHitRate 44.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 31.17 # Row buffer hit rate for writes +system.physmem.avgGap 161529.66 # Average gap between requests +system.membus.throughput 396211878 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1420214 # Transaction distribution +system.membus.trans_dist::ReadResp 1420214 # Transaction distribution +system.membus.trans_dist::Writeback 1100650 # Transaction distribution +system.membus.trans_dist::ReadExReq 826485 # Transaction distribution +system.membus.trans_dist::ReadExResp 826485 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 5594048 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 5594048 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 214230336 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 214230336 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214230336 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12859707750 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 21134071500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.9 # Layer utilization (%) +system.cpu.branchPred.lookups 304230401 # Number of BP lookups +system.cpu.branchPred.condPredicted 250450611 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15192997 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 172575058 # Number of BTB lookups +system.cpu.branchPred.BTBHits 162497547 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.242078 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17562220 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 189 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.160506 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17547944 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 207 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,237 +378,237 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1034710708 # number of cpu cycles simulated +system.cpu.numCycles 1081392801 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 298243506 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2186139129 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303238356 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 179047247 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435102558 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 87842368 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 155357657 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 150 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 288597285 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5732219 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 958597013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.523325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.213142 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 300338229 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2194868023 # Number of instructions fetch has processed +system.cpu.fetch.Branches 304230401 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 180045491 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 436913465 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88946702 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 165329116 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 33 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 290586210 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6069176 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 973112936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494450 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.204820 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 523494535 54.61% 54.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25506855 2.66% 57.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39100627 4.08% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48361324 5.05% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43019358 4.49% 70.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46453211 4.85% 75.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38427133 4.01% 79.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18718773 1.95% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175515197 18.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 536199557 55.10% 55.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25797166 2.65% 57.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39079992 4.02% 61.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48369850 4.97% 66.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43937617 4.52% 71.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46464611 4.77% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38405061 3.95% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19061800 1.96% 81.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175797282 18.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 958597013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.293066 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.112802 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 329802987 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 133619813 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405201175 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20080558 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69892480 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46072656 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 693 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2366906963 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2456 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69892480 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 353335624 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 63410713 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18651 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400220631 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71718914 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2304481635 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 133374 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5031151 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58581263 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 68 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2279812946 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10642278370 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10642275398 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2972 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 973112936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.281332 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.029668 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 332624022 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 143219561 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 406441589 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20296480 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 70531284 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46039188 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 865 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2374316328 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2545 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 70531284 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 356409274 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 71650111 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21139 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 401304268 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73196860 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2310523412 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 156231 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5060521 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60179356 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 18 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2286636992 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10669420338 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10669417166 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3172 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 573493016 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 743 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 740 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 158758361 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624481311 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220974466 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86299107 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 71333452 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2201408276 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 781 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018173722 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4013043 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 473803931 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1125355707 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 611 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 958597013 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.105341 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906395 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 580317062 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 904 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 901 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 161063694 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 625481573 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 221078320 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85817344 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 70539912 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2205002740 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 913 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2019903116 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4041921 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 477338341 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1137890497 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 973112936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.075713 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906230 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 277575373 28.96% 28.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151381497 15.79% 44.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161170411 16.81% 61.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119836935 12.50% 74.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123952521 12.93% 86.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73863494 7.71% 94.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38468068 4.01% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9785076 1.02% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2563638 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 289817184 29.78% 29.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153400597 15.76% 45.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161373326 16.58% 62.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120291643 12.36% 74.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123812966 12.72% 87.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73732869 7.58% 94.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38377982 3.94% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9754115 1.00% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2552254 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 958597013 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 973112936 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 884210 3.70% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5702 0.02% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18296872 76.51% 80.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4728009 19.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 873823 3.65% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5574 0.02% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18262233 76.32% 80.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4786578 20.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236704914 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925192 0.05% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 4 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587491999 29.11% 90.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193051561 9.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1237523467 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925246 0.05% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 44 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 588384414 29.13% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193069911 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018173722 # Type of FU issued -system.cpu.iq.rate 1.950471 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23914793 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011850 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5022872024 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2675402581 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957467931 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 269 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 546 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 94 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042088379 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 136 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64652420 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2019903116 # Type of FU issued +system.cpu.iq.rate 1.867872 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23928208 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011846 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5040888987 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2682531512 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957653574 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 310 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 612 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 122 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2043831169 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 155 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64629118 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138554542 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 270922 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192724 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46127421 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 139554804 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 275861 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192692 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46231275 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4683320 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 5362990 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69892480 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28879520 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1498948 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2201409154 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6144718 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624481311 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220974466 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 719 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 474123 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 89366 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192724 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8152988 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9608721 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17761709 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988146149 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573921356 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30027573 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 70531284 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 34407025 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1609544 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2205003765 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7646058 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 625481573 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 221078320 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 851 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 482587 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 96102 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192692 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8138129 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9602458 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17740587 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988966025 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574553789 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30937091 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 97 # number of nop insts executed -system.cpu.iew.exec_refs 764085836 # number of memory reference insts executed -system.cpu.iew.exec_branches 238329441 # Number of branches executed -system.cpu.iew.exec_stores 190164480 # Number of stores executed -system.cpu.iew.exec_rate 1.921451 # Inst execution rate -system.cpu.iew.wb_sent 1965914335 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957468025 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296382145 # num instructions producing a value -system.cpu.iew.wb_consumers 2061123370 # num instructions consuming a value +system.cpu.iew.exec_nop 112 # number of nop insts executed +system.cpu.iew.exec_refs 764737764 # number of memory reference insts executed +system.cpu.iew.exec_branches 238303653 # Number of branches executed +system.cpu.iew.exec_stores 190183975 # Number of stores executed +system.cpu.iew.exec_rate 1.839263 # Inst execution rate +system.cpu.iew.wb_sent 1966073864 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957653696 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295701173 # num instructions producing a value +system.cpu.iew.wb_consumers 2059307469 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.891802 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.628969 # average fanout of values written-back +system.cpu.iew.wb_rate 1.810308 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629193 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 478433603 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 482029293 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15212517 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 888704533 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.938860 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.728045 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15192188 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 902581652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.909050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.715598 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 401292741 45.15% 45.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192157168 21.62% 66.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72538162 8.16% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35233922 3.96% 78.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18967934 2.13% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30755514 3.46% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20061647 2.26% 86.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11460153 1.29% 88.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106237292 11.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 414112551 45.88% 45.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193170118 21.40% 67.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72777120 8.06% 75.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35259342 3.91% 79.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18942446 2.10% 81.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30787152 3.41% 84.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19991978 2.21% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11413503 1.26% 88.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106127442 11.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 888704533 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 902581652 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -470,192 +619,212 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106237292 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106127442 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2983974098 # The number of ROB reads -system.cpu.rob.rob_writes 4473052836 # The number of ROB writes -system.cpu.timesIdled 1016894 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76113695 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3001556757 # The number of ROB reads +system.cpu.rob.rob_writes 4480884032 # The number of ROB writes +system.cpu.timesIdled 1155619 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 108279865 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.669905 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.669905 # CPI: Total CPI of All Threads -system.cpu.ipc 1.492749 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.492749 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956441643 # number of integer regfile reads -system.cpu.int_regfile_writes 1937434969 # number of integer regfile writes -system.cpu.fp_regfile_reads 88 # number of floating regfile reads -system.cpu.fp_regfile_writes 99 # number of floating regfile writes -system.cpu.misc_regfile_reads 737571197 # number of misc regfile reads +system.cpu.cpi 0.700129 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.700129 # CPI: Total CPI of All Threads +system.cpu.ipc 1.428309 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.428309 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9959942925 # number of integer regfile reads +system.cpu.int_regfile_writes 1937523681 # number of integer regfile writes +system.cpu.fp_regfile_reads 126 # number of floating regfile reads +system.cpu.fp_regfile_writes 125 # number of floating regfile writes +system.cpu.misc_regfile_reads 737562736 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.icache.replacements 21 # number of replacements -system.cpu.icache.tagsinuse 624.513050 # Cycle average of tags in use -system.cpu.icache.total_refs 288596120 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 772 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 373829.170984 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 1584099202 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7708436 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7708436 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3781153 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893485 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1562 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22983433 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 22984995 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 49984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 856466752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 856516736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856516736 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10472863577 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1171999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14401713992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.7 # Layer utilization (%) +system.cpu.icache.replacements 22 # number of replacements +system.cpu.icache.tagsinuse 627.830229 # Cycle average of tags in use +system.cpu.icache.total_refs 290585017 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 781 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 372067.883483 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 624.513050 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.304938 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.304938 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 288596120 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 288596120 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 288596120 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 288596120 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 288596120 # number of overall hits -system.cpu.icache.overall_hits::total 288596120 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1165 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1165 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1165 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1165 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1165 # number of overall misses -system.cpu.icache.overall_misses::total 1165 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 63973500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 63973500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 63973500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 63973500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 63973500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 63973500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 288597285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 288597285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 288597285 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 288597285 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 288597285 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 288597285 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 627.830229 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.306558 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.306558 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 290585017 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 290585017 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 290585017 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 290585017 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 290585017 # number of overall hits +system.cpu.icache.overall_hits::total 290585017 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1193 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1193 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1193 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1193 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1193 # number of overall misses +system.cpu.icache.overall_misses::total 1193 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 86035500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 86035500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 86035500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 86035500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 86035500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 86035500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 290586210 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 290586210 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 290586210 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 290586210 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 290586210 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 290586210 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54912.875536 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54912.875536 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54912.875536 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54912.875536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54912.875536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54912.875536 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 195 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72116.932104 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72116.932104 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72116.932104 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72116.932104 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72116.932104 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72116.932104 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.750000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 393 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 393 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 393 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 393 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 393 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 393 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 772 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 772 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 772 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 772 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 772 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 772 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45298000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45298000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45298000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45298000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45298000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45298000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 781 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 781 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 781 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 781 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59384001 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59384001 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59384001 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59384001 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59384001 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59384001 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58676.165803 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58676.165803 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58676.165803 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 58676.165803 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58676.165803 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 58676.165803 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76035.852753 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76035.852753 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76035.852753 # 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number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962868 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184163 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184242 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436489 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436489 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962868 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233984 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962868 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233984 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65045.212766 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84955.110633 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 84944.568389 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89275.963569 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89275.963569 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65045.212766 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86545.139311 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86537.943000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65045.212766 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86545.139311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86537.943000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9596411 # number of replacements -system.cpu.dcache.tagsinuse 4088.019440 # Cycle average of tags in use -system.cpu.dcache.total_refs 656077460 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9600507 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.337793 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3440663000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4088.019440 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998052 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 489029858 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 489029858 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167047476 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167047476 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits +system.cpu.dcache.replacements 9597044 # number of replacements +system.cpu.dcache.tagsinuse 4088.193523 # Cycle average of tags in use +system.cpu.dcache.total_refs 655932792 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9601140 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.318220 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3513476000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4088.193523 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998094 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998094 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 488973029 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 488973029 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166959638 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166959638 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656077334 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656077334 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656077334 # number of overall hits -system.cpu.dcache.overall_hits::total 656077334 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11474951 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11474951 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5538571 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5538571 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 655932667 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 655932667 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 655932667 # number of overall hits +system.cpu.dcache.overall_hits::total 655932667 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11505709 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11505709 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5626409 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5626409 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17013522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17013522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17013522 # number of overall misses -system.cpu.dcache.overall_misses::total 17013522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 323064220500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 323064220500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 229479325824 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 229479325824 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 552543546324 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 552543546324 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 552543546324 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 552543546324 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500504809 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500504809 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17132118 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17132118 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17132118 # number of overall misses +system.cpu.dcache.overall_misses::total 17132118 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 379498751500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 379498751500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 307395824029 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 307395824029 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 651000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 651000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 686894575529 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 686894575529 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 686894575529 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 686894575529 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500478738 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500478738 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673090856 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673090856 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673090856 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673090856 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022927 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022927 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032092 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025277 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025277 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025277 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025277 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28153.864927 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28153.864927 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41432.948286 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41432.948286 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32476.729176 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32476.729176 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32476.729176 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32476.729176 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 26385368 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1054130 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1182490 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64549 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.313396 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16.330695 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673064785 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673064785 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673064785 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673064785 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032601 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032601 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025454 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025454 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025454 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025454 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32983.517270 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32983.517270 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54634.461169 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54634.461169 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 217000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 217000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40093.967105 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40093.967105 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29400681 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3494014 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1217576 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.146896 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 53.645121 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781426 # number of writebacks -system.cpu.dcache.writebacks::total 3781426 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767868 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3767868 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645146 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3645146 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3781153 # number of writebacks +system.cpu.dcache.writebacks::total 3781153 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798054 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3798054 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732924 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3732924 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7413014 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7413014 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7413014 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7413014 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707083 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7707083 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893425 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893425 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9600508 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9600508 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9600508 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9600508 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186133873500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 186133873500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83704359724 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83704359724 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269838233224 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 269838233224 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269838233224 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 269838233224 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7530978 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7530978 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7530978 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7530978 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707655 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7707655 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893485 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893485 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9601140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9601140 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9601140 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9601140 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210632290508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 210632290508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97135590826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 97135590826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 307767881334 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 307767881334 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 307767881334 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 307767881334 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24151.014528 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24151.014528 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44207.908802 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44207.908802 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28106.661983 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28106.661983 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28106.661983 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28106.661983 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27327.674955 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27327.674955 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51299.899828 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51299.899828 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index bf810ed1c..c05db510c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu sim_ticks 861538200000 # Number of ticks simulated final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1602478 # Simulator instruction rate (inst/s) -host_op_rate 1787682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 893842215 # Simulator tick rate (ticks/s) -host_mem_usage 278712 # Number of bytes of host memory used -host_seconds 963.86 # Real time elapsed on the host +host_inst_rate 2812355 # Simulator instruction rate (inst/s) +host_op_rate 3137389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1568696760 # Simulator tick rate (ticks/s) +host_mem_usage 234512 # Number of bytes of host memory used +host_seconds 549.21 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1723073853 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 724469782 # Wr system.physmem.bw_total::cpu.inst 7171199554 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2560009600 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9731209155 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9731209155 # Throughput (bytes/s) +system.membus.data_through_bus 8383808419 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 8d9905464..7f261f2f5 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu sim_ticks 2391205115000 # Number of ticks simulated final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 809589 # Simulator instruction rate (inst/s) -host_op_rate 903509 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1258086461 # Simulator tick rate (ticks/s) -host_mem_usage 287292 # Number of bytes of host memory used -host_seconds 1900.67 # Real time elapsed on the host +host_inst_rate 1401168 # Simulator instruction rate (inst/s) +host_op_rate 1563717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2177389973 # Simulator tick rate (ticks/s) +host_mem_usage 243008 # Number of bytes of host memory used +host_seconds 1098.20 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 27225047 # To system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 79651138 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1177898 # Transaction distribution +system.membus.trans_dist::ReadResp 1177898 # Transaction distribution +system.membus.trans_dist::Writeback 1017198 # Transaction distribution +system.membus.trans_dist::ReadExReq 780876 # Transaction distribution +system.membus.trans_dist::ReadExResp 780876 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 4934746 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4934746 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190462208 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21927890 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 21929166 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 820009856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 820050688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 545751e41..09bbb2360 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -33,6 +33,9 @@ system.physmem.bw_write::total 542745211 # Wr system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 13588998587 # Throughput (bytes/s) +system.membus.data_through_bus 38674388193 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 5692014456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 225f011f6..136c3d430 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -34,6 +34,26 @@ system.physmem.bw_total::writebacks 11079992 # To system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 32392097 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1177614 # Transaction distribution +system.membus.trans_dist::ReadResp 1177614 # Transaction distribution +system.membus.trans_dist::Writeback 1018421 # Transaction distribution +system.membus.trans_dist::ReadExReq 781295 # Transaction distribution +system.membus.trans_dist::ReadExResp 781295 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190549120 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 11765161052 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -370,5 +390,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 139381638 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1350 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21923310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 21924660 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 43200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819880512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 819923712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |