diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
| commit | c49e739352b6d6bd665c78c560602d0cff1e6a1a (patch) | |
| tree | 5d32efd82f884376573604727d971a80458ed04a /tests/long/se/60.bzip2/ref | |
| parent | e5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff) | |
| download | gem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz | |
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/long/se/60.bzip2/ref')
26 files changed, 559 insertions, 186 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 7c9012664..1fcd4f24c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout index 9d80ff74e..0482efbeb 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:59 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:44:37 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 9080a092b..0ddfc2b1c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 1.009999 # Nu sim_ticks 1009998808500 # Number of ticks simulated final_tick 1009998808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95125 # Simulator instruction rate (inst/s) -host_op_rate 95125 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52795470 # Simulator tick rate (ticks/s) -host_mem_usage 214864 # Number of bytes of host memory used -host_seconds 19130.41 # Real time elapsed on the host +host_inst_rate 98665 # Simulator instruction rate (inst/s) +host_op_rate 98665 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54760444 # Simulator tick rate (ticks/s) +host_mem_usage 215204 # Number of bytes of host memory used +host_seconds 18443.95 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 172618048 # Number of bytes read from this memory -system.physmem.bytes_inst_read 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written 74938304 # Number of bytes written to this memory -system.physmem.num_reads 2697157 # Number of read requests responded to by this memory -system.physmem.num_writes 1170911 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 170909160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 54432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 74196428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 245105588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 172563072 # Number of bytes read from this memory +system.physmem.bytes_read::total 172618048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74938304 # Number of bytes written to this memory +system.physmem.bytes_written::total 74938304 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2696298 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2697157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1170911 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1170911 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 54432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 170854728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 170909160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 74196428 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 74196428 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 74196428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 170854728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 245105588 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -156,11 +169,17 @@ system.cpu.icache.demand_accesses::total 231980227 # nu system.cpu.icache.overall_accesses::cpu.inst 231980227 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 231980227 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54607.276119 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54607.276119 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54607.276119 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54607.276119 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 125500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,11 +207,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 45929000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45929000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 45929000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53467.986030 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53467.986030 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53467.986030 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53467.986030 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107352 # number of replacements system.cpu.dcache.tagsinuse 4082.536815 # Cycle average of tags in use @@ -236,13 +261,21 @@ system.cpu.dcache.demand_accesses::total 605324165 # nu system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018229 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.018229 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016940 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016940 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016940 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24698.466940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24698.466940 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.899650 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37643.899650 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28397.395554 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28397.395554 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 11000000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 8092150500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2762 # number of cycles access was blocked @@ -278,13 +311,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 215283040500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215283040500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 215283040500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21612.503361 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21612.503361 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.051551 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31332.051551 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23627.752746 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23627.752746 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2686301 # number of replacements system.cpu.l2cache.tagsinuse 26348.804807 # Cycle average of tags in use @@ -346,18 +387,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 9111448 system.cpu.l2cache.overall_accesses::total 9112307 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250216 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.250306 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470613 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.470613 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.295924 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.295991 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.295924 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.295991 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52334.109430 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52247.136865 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52247.178190 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52297.536757 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52297.536757 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52263.781827 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52263.781827 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked @@ -392,18 +441,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990994500 system.cpu.l2cache.overall_mshr_miss_latency::total 108025475000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250216 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250306 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.470613 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.295991 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.295991 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.279395 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.540678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.597095 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.619831 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40112.619831 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 7904554e8..b6ae8cce3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 70e725c8b..3e17983a4 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:19 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:48:46 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 385663c88..ad65e54b6 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.614317 # Nu sim_ticks 614317285000 # Number of ticks simulated final_tick 614317285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104366 # Simulator instruction rate (inst/s) -host_op_rate 104366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36931162 # Simulator tick rate (ticks/s) -host_mem_usage 215744 # Number of bytes of host memory used -host_seconds 16634.12 # Real time elapsed on the host +host_inst_rate 134863 # Simulator instruction rate (inst/s) +host_op_rate 134863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47722573 # Simulator tick rate (ticks/s) +host_mem_usage 216172 # Number of bytes of host memory used +host_seconds 12872.68 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 173249728 # Number of bytes read from this memory -system.physmem.bytes_inst_read 62784 # Number of instructions bytes read from this memory -system.physmem.bytes_written 75020608 # Number of bytes written to this memory -system.physmem.num_reads 2707027 # Number of read requests responded to by this memory -system.physmem.num_writes 1172197 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 282019947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 102201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 122120295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 404140242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 62784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 173186944 # Number of bytes read from this memory +system.physmem.bytes_read::total 173249728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 62784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 62784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75020608 # Number of bytes written to this memory +system.physmem.bytes_written::total 75020608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2706046 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2707027 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1172197 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1172197 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 102201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 281917745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 282019947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 102201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 102201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122120295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122120295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122120295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 102201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 281917745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 404140242 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -358,11 +371,17 @@ system.cpu.icache.demand_accesses::total 401793450 # nu system.cpu.icache.overall_accesses::cpu.inst 401793450 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 401793450 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34225.423729 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34225.423729 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34225.423729 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34225.423729 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34225.423729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34225.423729 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,11 +409,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 34897000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34897000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 34897000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35572.884811 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35572.884811 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35572.884811 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35572.884811 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35572.884811 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35572.884811 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9176629 # number of replacements system.cpu.dcache.tagsinuse 4086.046414 # Cycle average of tags in use @@ -446,15 +471,25 @@ system.cpu.dcache.demand_accesses::total 716734309 # nu system.cpu.dcache.overall_accesses::cpu.data 716734309 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 716734309 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018867 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.018867 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030574 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.030574 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.285714 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.285714 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.021493 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021493 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.021493 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021493 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16686.513125 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16686.513125 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27968.066921 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27968.066921 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 23500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 23500 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 20285.420171 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20285.420171 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 20285.420171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20285.420171 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 118562765 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2148382500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 37554 # number of cycles access was blocked @@ -496,15 +531,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 119919732956 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 119919732956 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 119919732956 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013124 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013124 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.142857 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.142857 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012809 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012809 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012809 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012809 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11148.160071 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11148.160071 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20476.218184 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20476.218184 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35500 # average LoadLockedReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13062.121566 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13062.121566 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13062.121566 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13062.121566 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2696556 # number of replacements system.cpu.l2cache.tagsinuse 26644.209628 # Cycle average of tags in use @@ -566,18 +611,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 9180725 system.cpu.l2cache.overall_accesses::total 9181706 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250005 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.250106 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.468092 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.468092 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.294753 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.294828 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.294753 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.294828 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34371.049949 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34338.518024 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34338.535509 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34465.947843 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34465.947843 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34371.049949 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34380.041027 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34380.037768 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34371.049949 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34380.041027 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34380.037768 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 17522000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 1684 # number of cycles access was blocked @@ -612,18 +665,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84423852000 system.cpu.l2cache.overall_mshr_miss_latency::total 84454420000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250005 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250106 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.468092 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.468092 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.294828 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.294828 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31160.040775 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31161.925712 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31161.924699 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31273.347207 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31273.347207 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31198.218562 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31198.218562 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index e320bcc80..16083f416 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr index 1b49765a7..1ed796979 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 0267f64e9..88b1b065e 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:38:02 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:21:33 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index ce798be64..cdd816836 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2012645 # Simulator instruction rate (inst/s) -host_op_rate 2012645 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1009971108 # Simulator tick rate (ticks/s) -host_mem_usage 205536 # Number of bytes of host memory used -host_seconds 904.17 # Real time elapsed on the host +host_inst_rate 3414010 # Simulator instruction rate (inst/s) +host_op_rate 3414010 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1713194291 # Simulator tick rate (ticks/s) +host_mem_usage 206032 # Number of bytes of host memory used +host_seconds 533.03 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 9280309971 # Number of bytes read from this memory -system.physmem.bytes_inst_read 7305514036 # Number of instructions bytes read from this memory -system.physmem.bytes_written 827777307 # Number of bytes written to this memory -system.physmem.num_reads 2270974172 # Number of read requests responded to by this memory -system.physmem.num_writes 160728502 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10162526375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999999926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 906468506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11068994882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory +system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 7305514036 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7305514036 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 827777307 # Number of bytes written to this memory +system.physmem.bytes_written::total 827777307 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1826378509 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 444595663 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2270974172 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 160728502 # Number of write requests responded to by this memory +system.physmem.num_writes::total 160728502 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999999926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2162526450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10162526375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999999926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999999926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 906468506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 906468506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index b8d054f36..f89f54e31 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout index 166dc5643..267941dc1 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:38:45 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:46 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index ada639802..3da64d83e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 2.663444 # Nu sim_ticks 2663443716000 # Number of ticks simulated final_tick 2663443716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 768706 # Simulator instruction rate (inst/s) -host_op_rate 768706 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1125083732 # Simulator tick rate (ticks/s) -host_mem_usage 214428 # Number of bytes of host memory used -host_seconds 2367.33 # Real time elapsed on the host +host_inst_rate 1479188 # Simulator instruction rate (inst/s) +host_op_rate 1479188 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2164950496 # Simulator tick rate (ticks/s) +host_mem_usage 214896 # Number of bytes of host memory used +host_seconds 1230.26 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 172614208 # Number of bytes read from this memory -system.physmem.bytes_inst_read 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written 74939072 # Number of bytes written to this memory -system.physmem.num_reads 2697097 # Number of read requests responded to by this memory -system.physmem.num_writes 1170923 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 64808656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 19271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 28136158 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 92944814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 172562880 # Number of bytes read from this memory +system.physmem.bytes_read::total 172614208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74939072 # Number of bytes written to this memory +system.physmem.bytes_written::total 74939072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2696295 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2697097 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1170923 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1170923 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 64789385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64808656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 28136158 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 28136158 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 28136158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 64789385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 92944814 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -110,11 +123,17 @@ system.cpu.icache.demand_accesses::total 1826378510 # nu system.cpu.icache.overall_accesses::cpu.inst 1826378510 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1826378510 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,11 +155,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 42506000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42506000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 42506000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use @@ -184,13 +209,21 @@ system.cpu.dcache.demand_accesses::total 605324165 # nu system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24508.481513 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24508.481513 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33767.845574 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33767.845574 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26428.412638 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26428.412638 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -218,13 +251,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 213473464000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213473464000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 213473464000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21508.481513 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21508.481513 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30767.845574 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30767.845574 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23428.412638 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23428.412638 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2686269 # number of replacements system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use @@ -286,18 +327,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 9111734 system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250202 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.250285 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470663 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.470663 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.295915 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.295977 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.295915 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.295977 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -332,18 +381,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107851800000 system.cpu.l2cache.overall_mshr_miss_latency::total 107883880000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250202 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250285 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470663 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.470663 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.295977 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.295977 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 11fd3546f..48015577c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 35c5c026a..2f52f2c05 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:46:03 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:36:31 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 54d82ede5..7863d76cc 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.463994 # Nu sim_ticks 463993693500 # Number of ticks simulated final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113228 # Simulator instruction rate (inst/s) -host_op_rate 126315 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34014323 # Simulator tick rate (ticks/s) -host_mem_usage 231672 # Number of bytes of host memory used -host_seconds 13641.13 # Real time elapsed on the host +host_inst_rate 128371 # Simulator instruction rate (inst/s) +host_op_rate 143208 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38563333 # Simulator tick rate (ticks/s) +host_mem_usage 232076 # Number of bytes of host memory used +host_seconds 12031.99 # Real time elapsed on the host sim_insts 1544563066 # Number of instructions simulated sim_ops 1723073879 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 189795648 # Number of bytes read from this memory -system.physmem.bytes_inst_read 49344 # Number of instructions bytes read from this memory -system.physmem.bytes_written 78222144 # Number of bytes written to this memory -system.physmem.num_reads 2965557 # Number of read requests responded to by this memory -system.physmem.num_writes 1222221 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 409047904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 106346 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 168584498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 577632403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 49344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 189746304 # Number of bytes read from this memory +system.physmem.bytes_read::total 189795648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78222144 # Number of bytes written to this memory +system.physmem.bytes_written::total 78222144 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2964786 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2965557 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1222221 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1222221 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 106346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 408941558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 409047904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 106346 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 106346 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 168584498 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 168584498 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 168584498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 408941558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 577632403 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -369,11 +382,17 @@ system.cpu.icache.demand_accesses::total 283730265 # nu system.cpu.icache.overall_accesses::cpu.inst 283730265 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 283730265 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33283.208020 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33283.208020 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33283.208020 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,11 +420,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 27579500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27579500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 27579500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34431.335830 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34431.335830 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9619302 # number of replacements system.cpu.dcache.tagsinuse 4087.756066 # Cycle average of tags in use @@ -461,15 +486,25 @@ system.cpu.dcache.demand_accesses::total 676628084 # nu system.cpu.dcache.overall_accesses::cpu.data 676628084 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 676628084 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021216 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021216 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.030175 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.023501 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023501 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.023501 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023501 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17679.887499 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17679.887499 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24831.987697 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24831.987697 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37833.333333 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20022.197405 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20022.197405 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 271440605 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 164500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 91957 # number of cycles access was blocked @@ -507,13 +542,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 138431091460 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138431091460 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 138431091460 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015335 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015335 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014223 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.817537 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.817537 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23955.185749 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23955.185749 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2953110 # number of replacements system.cpu.l2cache.tagsinuse 26875.343151 # Cycle average of tags in use @@ -578,18 +621,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 9623398 system.cpu.l2cache.overall_accesses::total 9624199 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963795 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265109 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.265181 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483459 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.483459 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963795 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.308082 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.308136 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963795 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.308082 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.308136 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.865285 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.448450 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34328.459152 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34690.748311 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34690.748311 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34440.319656 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34440.319656 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 57329500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 6735 # number of cycles access was blocked @@ -633,18 +684,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92824744500 system.cpu.l2cache.overall_mshr_miss_latency::total 92848795000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265108 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.265180 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483459 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.483459 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308135 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308135 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31193.904021 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31187.061187 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31187.063761 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.171225 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.171225 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index e2f8298fd..b103ca45f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index 89e0dc3cd..4559b3892 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:48:29 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:41:45 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 991f53624..6c3e8b909 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.861538 # Nu sim_ticks 861538205000 # Number of ticks simulated final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1163959 # Simulator instruction rate (inst/s) -host_op_rate 1298482 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 649242111 # Simulator tick rate (ticks/s) -host_mem_usage 220952 # Number of bytes of host memory used -host_seconds 1326.99 # Real time elapsed on the host +host_inst_rate 2187855 # Simulator instruction rate (inst/s) +host_op_rate 2440714 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1220358665 # Simulator tick rate (ticks/s) +host_mem_usage 221416 # Number of bytes of host memory used +host_seconds 705.97 # Real time elapsed on the host sim_insts 1544563049 # Number of instructions simulated sim_ops 1723073862 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 7759650064 # Number of bytes read from this memory -system.physmem.bytes_inst_read 6178262392 # Number of instructions bytes read from this memory -system.physmem.bytes_written 624158392 # Number of bytes written to this memory -system.physmem.num_reads 2026949786 # Number of read requests responded to by this memory -system.physmem.num_writes 172586108 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9006739363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7171199555 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 724469778 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9731209141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 6178262392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1581387672 # Number of bytes read from this memory +system.physmem.bytes_read::total 7759650064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6178262392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6178262392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory +system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1544565598 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 482384188 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2026949786 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory +system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7171199555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1835539809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9006739363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7171199555 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7171199555 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 724469778 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 724469778 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7171199555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2560009587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9731209141 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 745e9eef0..88ea9515a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 4467d8b99..d07a6ceff 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:48:54 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:44:07 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 47aaa5f47..db0ae235a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 2.431420 # Nu sim_ticks 2431419954000 # Number of ticks simulated final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 629125 # Simulator instruction rate (inst/s) -host_op_rate 702110 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 994091440 # Simulator tick rate (ticks/s) -host_mem_usage 230132 # Number of bytes of host memory used -host_seconds 2445.87 # Real time elapsed on the host +host_inst_rate 1031283 # Simulator instruction rate (inst/s) +host_op_rate 1150922 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1629547552 # Simulator tick rate (ticks/s) +host_mem_usage 230584 # Number of bytes of host memory used +host_seconds 1492.08 # Real time elapsed on the host sim_insts 1538759609 # Number of instructions simulated sim_ops 1717270343 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 172766016 # Number of bytes read from this memory -system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written 75006720 # Number of bytes written to this memory -system.physmem.num_reads 2699469 # Number of read requests responded to by this memory -system.physmem.num_writes 1171980 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 71055605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 16214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 30848937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 101904542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 172726592 # Number of bytes read from this memory +system.physmem.bytes_read::total 172766016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75006720 # Number of bytes written to this memory +system.physmem.bytes_written::total 75006720 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2698853 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2699469 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1171980 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1171980 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 16214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 71039391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 71055605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30848937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30848937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30848937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 71039391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 101904542 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 1544565599 # nu system.cpu.icache.overall_accesses::cpu.inst 1544565599 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1544565599 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54551.724138 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54551.724138 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54551.724138 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 32890000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32890000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 32890000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51551.724138 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51551.724138 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9111140 # number of replacements system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use @@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 654970174 # nu system.cpu.dcache.overall_accesses::cpu.data 654970174 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 654970174 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24514.084594 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33784.641656 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26435.424162 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26435.424162 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 213619422000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213619422000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 213619422000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21514.084594 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21514.084594 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30784.641656 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30784.641656 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2687066 # number of replacements system.cpu.l2cache.tagsinuse 26134.517233 # Cycle average of tags in use @@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 9115236 system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250335 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.250398 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471063 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.471063 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.296082 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.296128 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.296082 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.296128 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107954120000 system.cpu.l2cache.overall_mshr_miss_latency::total 107978760000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250335 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250398 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471063 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.296128 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.296128 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 9635789c5..c6605043f 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:49:05 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 681bc52fe..d066014cc 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007259500 # Number of ticks simulated final_tick 2846007259500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1189657 # Simulator instruction rate (inst/s) -host_op_rate 1853594 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1125559296 # Simulator tick rate (ticks/s) -host_mem_usage 239492 # Number of bytes of host memory used -host_seconds 2528.53 # Real time elapsed on the host +host_inst_rate 1390065 # Simulator instruction rate (inst/s) +host_op_rate 2165848 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1315169413 # Simulator tick rate (ticks/s) +host_mem_usage 216596 # Number of bytes of host memory used +host_seconds 2163.99 # Real time elapsed on the host sim_insts 3008081057 # Number of instructions simulated sim_ops 4686862651 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 37129731755 # Number of bytes read from this memory -system.physmem.bytes_inst_read 32105863408 # Number of instructions bytes read from this memory -system.physmem.bytes_written 1544656790 # Number of bytes written to this memory -system.physmem.num_reads 5252417675 # Number of read requests responded to by this memory -system.physmem.num_writes 438528337 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 13046253354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 11281019506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 542745204 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 13588998558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 32105863408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5023868347 # Number of bytes read from this memory +system.physmem.bytes_read::total 37129731755 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 32105863408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 32105863408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 1544656790 # Number of bytes written to this memory +system.physmem.bytes_written::total 1544656790 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4013232926 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1239184749 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5252417675 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 438528337 # Number of write requests responded to by this memory +system.physmem.num_writes::total 438528337 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11281019506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1765233848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13046253354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11281019506 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11281019506 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 542745204 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 542745204 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11281019506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2307979052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13588998558 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 5692014520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index efac2f0f1..11192711e 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 16:08:32 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 2bc91e6e3..e2cb03bbf 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 5.923548 # Nu sim_ticks 5923548078000 # Number of ticks simulated final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 747861 # Simulator instruction rate (inst/s) -host_op_rate 1165236 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1472697488 # Simulator tick rate (ticks/s) -host_mem_usage 248420 # Number of bytes of host memory used -host_seconds 4022.24 # Real time elapsed on the host +host_inst_rate 633731 # Simulator instruction rate (inst/s) +host_op_rate 987410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1247949692 # Simulator tick rate (ticks/s) +host_mem_usage 225520 # Number of bytes of host memory used +host_seconds 4746.62 # Real time elapsed on the host sim_insts 3008081057 # Number of instructions simulated sim_ops 4686862651 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 173910080 # Number of bytes read from this memory -system.physmem.bytes_inst_read 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written 75176384 # Number of bytes written to this memory -system.physmem.num_reads 2717345 # Number of read requests responded to by this memory -system.physmem.num_writes 1174631 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 29359107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 12691107 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 42050214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 173866880 # Number of bytes read from this memory +system.physmem.bytes_read::total 173910080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75176384 # Number of bytes written to this memory +system.physmem.bytes_written::total 75176384 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2716670 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2717345 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1174631 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1174631 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 29351814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29359107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12691107 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12691107 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12691107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 29351814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42050214 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 11847096156 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 4013232927 # nu system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 35775000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35775000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 35775000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use @@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 1677713086 # nu system.cpu.dcache.overall_accesses::cpu.data 1677713086 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1677713086 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24617.504171 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24617.504171 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33796.256483 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33796.256483 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26521.034159 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26521.034159 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 214339587000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214339587000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 214339587000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21617.504171 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21617.504171 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30796.256483 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30796.256483 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23521.034159 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23521.034159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2706631 # number of replacements system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use @@ -254,18 +295,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 9112677 system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.252798 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.252868 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471339 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.471339 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.298120 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.298172 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.298120 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.298172 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,18 +349,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108666800000 system.cpu.l2cache.overall_mshr_miss_latency::total 108693800000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.252798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.252868 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471339 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471339 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.298172 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.298172 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |