diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
| commit | fce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch) | |
| tree | 26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/long/se/60.bzip2/ref | |
| parent | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff) | |
| download | gem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz | |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/long/se/60.bzip2/ref')
3 files changed, 1692 insertions, 1691 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 2c8c2e903..bbfef95ab 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.985090 # Number of seconds simulated -sim_ticks 985089830500 # Number of ticks simulated -final_tick 985089830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.993559 # Number of seconds simulated +sim_ticks 993559170500 # Number of ticks simulated +final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87940 # Simulator instruction rate (inst/s) -host_op_rate 87940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47603973 # Simulator tick rate (ticks/s) -host_mem_usage 516412 # Number of bytes of host memory used -host_seconds 20693.44 # Real time elapsed on the host +host_inst_rate 148425 # Simulator instruction rate (inst/s) +host_op_rate 148425 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 81036604 # Simulator tick rate (ticks/s) +host_mem_usage 464668 # Number of bytes of host memory used +host_seconds 12260.62 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125364992 # Number of bytes read from this memory -system.physmem.bytes_read::total 125419968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory +system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory -system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory +system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958828 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959687 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 127262497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 127318306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 66141704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 66141704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 66141704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 127262497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193460010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959687 # Total number of read requests seen -system.physmem.writeReqs 1018055 # Total number of write requests seen -system.physmem.cpureqs 2977742 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125419968 # Total number of bytes read from memory -system.physmem.bytesWritten 65155520 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125419968 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65155520 # bytesWritten derated as per pkt->getSize() +system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 55332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 126177745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 126233078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 65578089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 65578089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 65578089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 126177745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 191811167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959688 # Total number of read requests seen +system.physmem.writeReqs 1018058 # Total number of write requests seen +system.physmem.cpureqs 2977859 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125420032 # Total number of bytes read from memory +system.physmem.bytesWritten 65155712 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 582 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 123239 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 122861 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 121276 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 122602 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122222 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 124477 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 123481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122168 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 122610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 120102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 120483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 121941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 124488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123177 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 63438 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63830 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 63139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 62716 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63395 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63432 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 62525 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63278 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 63327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 63976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64713 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 65307 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64492 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 122179 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 121801 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 121647 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 123761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123294 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122180 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 120330 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 121052 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121195 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 121884 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 121113 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 123048 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 125175 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 123789 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 122721 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123937 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63389 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 62256 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 62952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63764 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 64028 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63369 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 63391 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63292 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 64137 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64555 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64147 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 63647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64278 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 985089778500 # Total gap between requests +system.physmem.numWrRetry 113 # Number of times wr buffer was full causing retry +system.physmem.totGap 993559118500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1959687 # Categorize read packet sizes +system.physmem.readPktSize::6 1959688 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1018055 # categorize write packet sizes +system.physmem.writePktSize::6 1018171 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1651728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 82029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1630106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 205346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 87736 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35917 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 41624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44262 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see @@ -161,66 +161,66 @@ system.physmem.wrQLenPdf::19 44263 # Wh system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 19640844571 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 85229742571 # Sum of mem lat for all requests -system.physmem.totBusLat 7836420000 # Total cycles spent in databus access -system.physmem.totBankLat 57752478000 # Total cycles spent in bank access -system.physmem.avgQLat 10025.42 # Average queueing delay per request -system.physmem.avgBankLat 29479.01 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43504.43 # Average memory access latency -system.physmem.avgRdBW 127.32 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 66.14 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 127.32 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 66.14 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.21 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.09 # Average read queue length over time -system.physmem.avgWrQLen 10.28 # Average write queue length over time -system.physmem.readRowHits 834572 # Number of row buffer hits during reads -system.physmem.writeRowHits 194113 # Number of row buffer hits during writes -system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes -system.physmem.avgGap 330817.71 # Average gap between requests -system.cpu.branchPred.lookups 326556831 # Number of BP lookups -system.cpu.branchPred.condPredicted 252596788 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 138232865 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 218937552 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135479530 # Number of BTB hits +system.physmem.totQLat 35848625999 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 104288840999 # Sum of mem lat for all requests +system.physmem.totBusLat 9795530000 # Total cycles spent in databus access +system.physmem.totBankLat 58644685000 # Total cycles spent in bank access +system.physmem.avgQLat 18298.46 # Average queueing delay per request +system.physmem.avgBankLat 29934.41 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 53232.87 # Average memory access latency +system.physmem.avgRdBW 126.23 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 65.58 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 126.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 65.58 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 1.50 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.10 # Average read queue length over time +system.physmem.avgWrQLen 10.46 # Average write queue length over time +system.physmem.readRowHits 770935 # Number of row buffer hits during reads +system.physmem.writeRowHits 285714 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes +system.physmem.avgGap 333661.47 # Average gap between requests +system.cpu.branchPred.lookups 326540496 # Number of BP lookups +system.cpu.branchPred.condPredicted 252608544 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 138248451 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 220022753 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135563778 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.880444 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.613527 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444784566 # DTB read hits +system.cpu.dtb.read_hits 444796007 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449681644 # DTB read accesses -system.cpu.dtb.write_hits 160833172 # DTB write hits +system.cpu.dtb.read_accesses 449693085 # DTB read accesses +system.cpu.dtb.write_hits 160833351 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162534476 # DTB write accesses -system.cpu.dtb.data_hits 605617738 # DTB hits +system.cpu.dtb.write_accesses 162534655 # DTB write accesses +system.cpu.dtb.data_hits 605629358 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612216120 # DTB accesses -system.cpu.itb.fetch_hits 231916745 # ITB hits +system.cpu.dtb.data_accesses 612227740 # DTB accesses +system.cpu.itb.fetch_hits 232025962 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231916767 # ITB accesses +system.cpu.itb.fetch_accesses 232025984 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,34 +234,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1970179662 # number of cpu cycles simulated +system.cpu.numCycles 1987118342 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172296521 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154260310 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667620352 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172378846 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154161650 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667662469 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043822969 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043865086 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651716748 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617888959 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 120522099 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 11112308 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 131634407 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 83565858 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.168329 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139351244 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651727789 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617884568 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120519408 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11130585 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131649993 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83550128 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.175613 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139371391 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1741570972 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1741838166 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7474606 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 398498363 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571681299 # Number of cycles cpu stages are processed. -system.cpu.activity 79.773501 # Percentage of cycles cpu is active +system.cpu.timesIdled 7484554 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 415293759 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571824583 # Number of cycles cpu stages are processed. +system.cpu.activity 79.100703 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -273,191 +273,191 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.082647 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.091955 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.082647 # CPI: Total CPI of All Threads -system.cpu.ipc 0.923662 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.091955 # CPI: Total CPI of All Threads +system.cpu.ipc 0.915789 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.923662 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 783567133 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186612529 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.228646 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1036391021 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933788641 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 47.396116 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 997796043 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972383619 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.355073 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1560555740 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409623922 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.791196 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 948846788 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021332874 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.839581 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.915789 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 800261653 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186856689 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.727529 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1053419210 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933699132 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.987596 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1014725197 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972393145 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.934838 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1577495451 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409622891 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.613915 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 965781597 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021336745 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.397882 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 667.601881 # Cycle average of tags in use -system.cpu.icache.total_refs 231915637 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 667.839755 # Cycle average of tags in use +system.cpu.icache.total_refs 232024853 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 269983.279395 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270110.422584 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 667.601881 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325977 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325977 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231915637 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231915637 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231915637 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231915637 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231915637 # number of overall hits -system.cpu.icache.overall_hits::total 231915637 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1108 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1108 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1108 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1108 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1108 # number of overall misses -system.cpu.icache.overall_misses::total 1108 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 59929000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 59929000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 59929000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 59929000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 59929000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 59929000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231916745 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231916745 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231916745 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231916745 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231916745 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231916745 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 667.839755 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.326094 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.326094 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 232024853 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232024853 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232024853 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232024853 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232024853 # number of overall hits +system.cpu.icache.overall_hits::total 232024853 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1109 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1109 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1109 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1109 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1109 # number of overall misses +system.cpu.icache.overall_misses::total 1109 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 64824000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 64824000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 64824000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 64824000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 64824000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 64824000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232025962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232025962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232025962 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232025962 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232025962 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232025962 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54087.545126 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54087.545126 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54087.545126 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54087.545126 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54087.545126 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54087.545126 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58452.660054 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58452.660054 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58452.660054 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58452.660054 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 249 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 249 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 249 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 250 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 250 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 250 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 250 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 250 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 250 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47313000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47313000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47313000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47313000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47313000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47313000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51094000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51094000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51094000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51094000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51094000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51094000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55079.161816 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55079.161816 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55079.161816 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55079.161816 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55079.161816 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55079.161816 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59480.791618 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59480.791618 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59480.791618 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59480.791618 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59480.791618 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59480.791618 # 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Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.482832 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.942771 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6044304 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6044304 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3693296 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3693296 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108342 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108342 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7152646 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7152646 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7152646 # number of overall hits -system.cpu.l2cache.overall_hits::total 7152646 # number of overall hits +system.cpu.l2cache.replacements 1926957 # number of replacements +system.cpu.l2cache.tagsinuse 30901.189493 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8958712 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1956750 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.578363 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 67146389752 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15036.220551 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 34.907128 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15830.061814 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.458869 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001065 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.483095 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.943029 # 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average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70184.095400 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54074.505239 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66904.411464 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66898.787664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54074.505239 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66904.411464 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66898.787664 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58476.135041 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70625.488947 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70616.632538 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84703.875213 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84703.875213 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58476.135041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76240.797436 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76233.010561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58476.135041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76240.797436 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76233.010561 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -466,86 +466,86 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.262475 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996646 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996646 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437268758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156244122 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156244122 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593512880 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593512880 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593512880 # number of overall hits +system.cpu.dcache.overall_hits::total 593512880 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326905 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326905 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4484380 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4484380 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 11811285 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 11811285 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11811285 # number of overall misses +system.cpu.dcache.overall_misses::total 11811285 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 167288165500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 167288165500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 202507086500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 202507086500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 369795252000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 369795252000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 369795252000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 369795252000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -556,54 +556,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027736 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027736 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019469 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019469 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019469 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019469 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21881.475631 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21881.475631 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43820.034894 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43820.034894 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30180.449638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30180.449638 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9247830 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4818517 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 358256 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65602 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.813469 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 73.450764 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027900 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027900 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019512 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019512 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019512 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019512 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.036924 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.036924 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.324339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.324339 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31308.638476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31308.638476 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13465460 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4770860 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 372579 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65753 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.141221 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.557298 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693296 # number of writebacks -system.cpu.dcache.writebacks::total 3693296 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104633 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104633 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2568846 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2568846 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2673479 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2673479 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2673479 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2673479 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222278 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222278 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889196 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889196 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111474 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111474 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111474 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111474 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144015924000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 144015924000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67975303000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 67975303000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211991227000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 211991227000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211991227000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 211991227000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3693293 # number of writebacks +system.cpu.dcache.writebacks::total 3693293 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104622 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104622 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595195 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2595195 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2699817 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2699817 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2699817 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2699817 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222283 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222283 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889185 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889185 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111468 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111468 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111468 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111468 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964459500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964459500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79317190500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 79317190500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230281650000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230281650000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230281650000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230281650000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -612,14 +612,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19940.512398 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19940.512398 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35981.075018 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35981.075018 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.595412 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.595412 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41984.872048 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41984.872048 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index c63a4e0f8..db2985766 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.655920 # Number of seconds simulated -sim_ticks 655919824500 # Number of ticks simulated -final_tick 655919824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.665563 # Number of seconds simulated +sim_ticks 665562897500 # Number of ticks simulated +final_tick 665562897500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111017 # Simulator instruction rate (inst/s) -host_op_rate 111017 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41944886 # Simulator tick rate (ticks/s) -host_mem_usage 517560 # Number of bytes of host memory used -host_seconds 15637.66 # Real time elapsed on the host +host_inst_rate 181531 # Simulator instruction rate (inst/s) +host_op_rate 181531 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69595242 # Simulator tick rate (ticks/s) +host_mem_usage 467736 # Number of bytes of host memory used +host_seconds 9563.34 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125796416 # Number of bytes read from this memory -system.physmem.bytes_read::total 125857920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65262592 # Number of bytes written to this memory -system.physmem.bytes_written::total 65262592 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965569 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966530 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019728 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019728 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 191786269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 191880037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 99497819 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 99497819 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 99497819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 191786269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 291377856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966530 # Total number of read requests seen -system.physmem.writeReqs 1019728 # Total number of write requests seen -system.physmem.cpureqs 2986258 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125857920 # Total number of bytes read from memory -system.physmem.bytesWritten 65262592 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125857920 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65262592 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 571 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125801472 # Number of bytes read from this memory +system.physmem.bytes_read::total 125863104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65262912 # Number of bytes written to this memory +system.physmem.bytes_written::total 65262912 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965648 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966611 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019733 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019733 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 189015152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 189107753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92601 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92601 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98056716 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98056716 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98056716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 189015152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 287164469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966611 # Total number of read requests seen +system.physmem.writeReqs 1019733 # Total number of write requests seen +system.physmem.cpureqs 2988993 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125863104 # Total number of bytes read from memory +system.physmem.bytesWritten 65262912 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125863104 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65262912 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 562 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 123004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 123537 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 123239 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 121669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 124908 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 123890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122835 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 123027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 120429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 120849 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 122324 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 124974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123664 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63268 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 63478 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63945 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63503 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 63256 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 62809 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63505 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63532 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 62611 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63461 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 64078 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 63409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64056 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64812 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 65441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64564 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 122665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 122306 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 122208 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 124220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122580 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 120700 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 121417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121606 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 121462 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 123460 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 125578 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 124270 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 123173 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 124451 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63478 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 62392 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63122 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63842 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 64138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63473 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63461 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 63474 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63840 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63360 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 64241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64652 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64261 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 63751 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64373 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 655919756000 # Total gap between requests +system.physmem.numWrRetry 2649 # Number of times wr buffer was full causing retry +system.physmem.totGap 665562829000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966530 # Categorize read packet sizes +system.physmem.readPktSize::6 1966611 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1019728 # categorize write packet sizes +system.physmem.writePktSize::6 1022382 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1634092 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 234966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 26268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1625792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 234895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 77536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27805 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44320 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see @@ -161,66 +161,66 @@ system.physmem.wrQLenPdf::19 44336 # Wh system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 20705208242 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 85868216242 # Sum of mem lat for all requests -system.physmem.totBusLat 7863836000 # Total cycles spent in databus access -system.physmem.totBankLat 57299172000 # Total cycles spent in bank access -system.physmem.avgQLat 10531.86 # Average queueing delay per request -system.physmem.avgBankLat 29145.66 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43677.52 # Average memory access latency -system.physmem.avgRdBW 191.88 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 99.50 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 191.88 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 99.50 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.82 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 10.55 # Average write queue length over time -system.physmem.readRowHits 840760 # Number of row buffer hits during reads -system.physmem.writeRowHits 193886 # Number of row buffer hits during writes -system.physmem.readRowHitRate 42.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 19.01 # Row buffer hit rate for writes -system.physmem.avgGap 219646.04 # Average gap between requests -system.cpu.branchPred.lookups 381024003 # Number of BP lookups -system.cpu.branchPred.condPredicted 296029232 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16079219 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 261934224 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259237388 # Number of BTB hits +system.physmem.totQLat 34363983237 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 102498683237 # Sum of mem lat for all requests +system.physmem.totBusLat 9830245000 # Total cycles spent in databus access +system.physmem.totBankLat 58304455000 # Total cycles spent in bank access +system.physmem.avgQLat 17478.70 # Average queueing delay per request +system.physmem.avgBankLat 29655.65 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 52134.35 # Average memory access latency +system.physmem.avgRdBW 189.11 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 98.06 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 189.11 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 98.06 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.24 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 10.79 # Average write queue length over time +system.physmem.readRowHits 776053 # Number of row buffer hits during reads +system.physmem.writeRowHits 286138 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes +system.physmem.avgGap 222868.77 # Average gap between requests +system.cpu.branchPred.lookups 381322658 # Number of BP lookups +system.cpu.branchPred.condPredicted 296346711 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16069927 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262182430 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259521497 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.970415 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24703724 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3041 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.985083 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24701305 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3076 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613741491 # DTB read hits -system.cpu.dtb.read_misses 11247891 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 624989382 # DTB read accesses -system.cpu.dtb.write_hits 212247245 # DTB write hits -system.cpu.dtb.write_misses 7144332 # DTB write misses +system.cpu.dtb.read_hits 613798645 # DTB read hits +system.cpu.dtb.read_misses 11251599 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 625050244 # DTB read accesses +system.cpu.dtb.write_hits 212271089 # DTB write hits +system.cpu.dtb.write_misses 7143652 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219391577 # DTB write accesses -system.cpu.dtb.data_hits 825988736 # DTB hits -system.cpu.dtb.data_misses 18392223 # DTB misses -system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 844380959 # DTB accesses -system.cpu.itb.fetch_hits 390708850 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.write_accesses 219414741 # DTB write accesses +system.cpu.dtb.data_hits 826069734 # DTB hits +system.cpu.dtb.data_misses 18395251 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 844464985 # DTB accesses +system.cpu.itb.fetch_hits 390709896 # ITB hits +system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 390708888 # ITB accesses +system.cpu.itb.fetch_accesses 390709940 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,139 +234,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1311839650 # number of cpu cycles simulated +system.cpu.numCycles 1331125796 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402148068 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3157560086 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381024003 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 283941112 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 573880213 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140086808 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 165153102 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1285 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 390708850 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8061624 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1257505437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.510971 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.156516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402151320 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3159313188 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381322658 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284222802 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574163176 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140279243 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 173671179 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1322 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 390709896 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8056983 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1266457048 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152796 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 683625224 54.36% 54.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42619367 3.39% 57.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21744894 1.73% 59.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39684878 3.16% 62.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129121337 10.27% 72.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61516601 4.89% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38545793 3.07% 80.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28125558 2.24% 83.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212521785 16.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 692293872 54.66% 54.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42630313 3.37% 58.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21744461 1.72% 59.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39673370 3.13% 62.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129246893 10.21% 73.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61513639 4.86% 77.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38552077 3.04% 80.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28113770 2.22% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212688653 16.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1257505437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.290450 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.406971 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 433733980 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 146719588 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542274905 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18455051 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116321913 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58305735 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 954 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3085307728 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2035 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116321913 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 456557347 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 93252503 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5104 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535232007 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56136563 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3003562340 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 560555 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1735251 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 50037437 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2245657329 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3895152131 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3893909248 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1242883 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1266457048 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.286466 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.373414 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433835858 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 155176701 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542390430 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18584911 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116469148 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58290582 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 824 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3086789571 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2029 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116469148 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 456704578 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 101399871 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7042 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535436988 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56439421 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3004825157 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 566473 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1727265 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 50367655 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2246602827 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3897066108 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3895827965 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1238143 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 869454366 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 190 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 189 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 120669951 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679225578 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255273844 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68130212 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37368209 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2722510883 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 144 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2508555980 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3078936 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 977267031 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 413974741 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 115 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1257505437 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.994867 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.973352 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 870399864 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 162 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 161 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 121306422 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679329311 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255341435 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67772546 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36892101 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2723405673 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2508908939 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3097394 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 978157995 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 414914582 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1266457048 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.981045 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.973109 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 417762073 33.22% 33.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201459942 16.02% 49.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185268981 14.73% 63.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153261704 12.19% 76.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133079768 10.58% 86.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 81048988 6.45% 93.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65262511 5.19% 98.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15257874 1.21% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5103596 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 426262331 33.66% 33.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201879469 15.94% 49.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185440300 14.64% 64.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153069981 12.09% 76.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133127020 10.51% 86.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81075751 6.40% 93.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65263497 5.15% 98.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15238482 1.20% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5100217 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1257505437 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1266457048 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2150864 11.67% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11870466 64.42% 76.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4405017 23.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2147356 11.64% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11882629 64.43% 76.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4412064 23.92% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643219876 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643457358 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 108 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 253 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 157 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 26 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 38 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued @@ -388,84 +388,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641326950 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224008572 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641426814 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224024134 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2508555980 # Type of FU issued -system.cpu.iq.rate 1.912243 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18426347 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007345 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6294223850 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3698666551 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2412312770 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1898830 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1217307 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 851008 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2526043830 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 938497 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62613731 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2508908939 # Type of FU issued +system.cpu.iq.rate 1.884802 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18442049 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007351 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6303917077 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3700456251 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2412530118 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1897292 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1213669 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 850482 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2526413076 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 937912 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62601543 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234629915 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 264851 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107543 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94545342 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234733648 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263681 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107887 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94612933 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 100 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1452143 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 149 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1508556 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116321913 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 41870148 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1143259 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2864507060 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8845706 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679225578 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255273844 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 144 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 295805 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17199 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107543 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10354551 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8556122 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18910673 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2461271813 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 624989902 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47284167 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116469148 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 45249808 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1153798 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2865411802 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8865893 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679329311 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255341435 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 296621 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17062 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107887 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10351897 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8549059 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18900956 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2461552831 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625050873 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47356108 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 141996033 # number of nop insts executed -system.cpu.iew.exec_refs 844381512 # number of memory reference insts executed -system.cpu.iew.exec_branches 300766985 # Number of branches executed -system.cpu.iew.exec_stores 219391610 # Number of stores executed -system.cpu.iew.exec_rate 1.876199 # Inst execution rate -system.cpu.iew.wb_sent 2441119325 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413163778 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388569148 # num instructions producing a value -system.cpu.iew.wb_consumers 1764314853 # num instructions consuming a value +system.cpu.iew.exec_nop 142006007 # number of nop insts executed +system.cpu.iew.exec_refs 844465652 # number of memory reference insts executed +system.cpu.iew.exec_branches 300780520 # Number of branches executed +system.cpu.iew.exec_stores 219414779 # Number of stores executed +system.cpu.iew.exec_rate 1.849226 # Inst execution rate +system.cpu.iew.wb_sent 2441340597 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413380600 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388547079 # num instructions producing a value +system.cpu.iew.wb_consumers 1764258867 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.839526 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.787030 # average fanout of values written-back +system.cpu.iew.wb_rate 1.813037 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.787043 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 823556826 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 824496541 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16078403 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1141183524 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.594643 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.519930 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16069169 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1149987900 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.582434 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.513328 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 628040121 55.03% 55.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174132211 15.26% 70.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86354537 7.57% 77.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53988637 4.73% 82.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34269513 3.00% 85.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24750272 2.17% 87.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22050678 1.93% 89.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22940990 2.01% 91.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94656565 8.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 636582703 55.36% 55.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174528815 15.18% 70.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86154838 7.49% 78.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53696009 4.67% 82.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34510870 3.00% 85.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25214106 2.19% 87.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21871895 1.90% 89.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22921084 1.99% 91.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94507580 8.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1141183524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1149987900 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,189 +476,189 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94656565 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94507580 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3604084711 # The number of ROB reads -system.cpu.rob.rob_writes 5403096067 # The number of ROB writes -system.cpu.timesIdled 804666 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 54334213 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3613977787 # The number of ROB reads +system.cpu.rob.rob_writes 5405122718 # The number of ROB writes +system.cpu.timesIdled 818240 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64668748 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.755649 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.755649 # CPI: Total CPI of All Threads -system.cpu.ipc 1.323366 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.323366 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3316903206 # number of integer regfile reads -system.cpu.int_regfile_writes 1931453212 # number of integer regfile writes -system.cpu.fp_regfile_reads 30791 # number of floating regfile reads -system.cpu.fp_regfile_writes 509 # number of floating regfile writes +system.cpu.cpi 0.766758 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.766758 # CPI: Total CPI of All Threads +system.cpu.ipc 1.304192 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.304192 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3317304663 # number of integer regfile reads +system.cpu.int_regfile_writes 1931628776 # number of integer regfile writes +system.cpu.fp_regfile_reads 30090 # number of floating regfile reads +system.cpu.fp_regfile_writes 557 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 768.875728 # Cycle average of tags in use -system.cpu.icache.total_refs 390707378 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 406563.348595 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 772.264197 # Cycle average of tags in use +system.cpu.icache.total_refs 390708412 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 963 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 405720.053998 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 768.875728 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.375428 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.375428 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 390707378 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 390707378 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 390707378 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 390707378 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 390707378 # number of overall hits -system.cpu.icache.overall_hits::total 390707378 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1472 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1472 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1472 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1472 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1472 # number of overall misses -system.cpu.icache.overall_misses::total 1472 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 78332000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 78332000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 78332000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 78332000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 78332000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 78332000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 390708850 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 390708850 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 390708850 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 390708850 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 390708850 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 390708850 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 772.264197 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.377082 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.377082 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 390708412 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 390708412 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 390708412 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 390708412 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 390708412 # number of overall hits +system.cpu.icache.overall_hits::total 390708412 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1482 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1482 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1482 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1482 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1482 # number of overall misses +system.cpu.icache.overall_misses::total 1482 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 83554999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 83554999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 83554999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 83554999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 83554999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 83554999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 390709894 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 390709894 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 390709894 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 390709894 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 390709894 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 390709894 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53214.673913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53214.673913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53214.673913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53214.673913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53214.673913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53214.673913 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56379.891363 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56379.891363 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56379.891363 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56379.891363 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56379.891363 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56379.891363 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 398 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56.857143 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 511 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 511 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 511 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 511 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 511 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 961 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 961 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 961 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56098500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 56098500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56098500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 56098500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56098500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 56098500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 519 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 519 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 519 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 519 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 519 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 519 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 963 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 963 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 963 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59079999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59079999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59079999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59079999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59079999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59079999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58375.130073 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58375.130073 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58375.130073 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 58375.130073 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58375.130073 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 58375.130073 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61349.947040 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61349.947040 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61349.947040 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61349.947040 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61349.947040 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61349.947040 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1933820 # number of replacements -system.cpu.l2cache.tagsinuse 31412.329215 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9058347 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1963602 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.613128 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 27341900502 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14673.243602 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 26.610693 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16712.474920 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.447792 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000812 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.510024 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.958628 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6106187 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6106187 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3724933 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3724933 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108387 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108387 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7214574 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7214574 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7214574 # number of overall hits -system.cpu.l2cache.overall_hits::total 7214574 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 961 # 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Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5062814000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.418525 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997905 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997905 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538685115 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538685115 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155650275 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155650275 # number of WriteReq hits +system.cpu.dcache.replacements 9176263 # number of replacements +system.cpu.dcache.tagsinuse 4087.522413 # Cycle average of tags in use +system.cpu.dcache.total_refs 694338200 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180359 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.633012 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5069314000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.522413 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997930 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538691860 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538691860 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155646338 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155646338 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694335390 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694335390 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694335390 # number of overall hits -system.cpu.dcache.overall_hits::total 694335390 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11273608 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11273608 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5078227 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5078227 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 694338198 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694338198 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694338198 # number of overall hits +system.cpu.dcache.overall_hits::total 694338198 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11282428 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11282428 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5082164 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5082164 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16351835 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16351835 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16351835 # number of overall misses -system.cpu.dcache.overall_misses::total 16351835 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 280031703000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 280031703000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 217034506033 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 217034506033 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 48500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 48500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 497066209033 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 497066209033 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 497066209033 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 497066209033 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 549958723 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 549958723 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16364592 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16364592 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16364592 # number of overall misses +system.cpu.dcache.overall_misses::total 16364592 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 295012100000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 295012100000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 224191521595 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 224191521595 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 431500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 431500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 519203621595 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 519203621595 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 519203621595 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 519203621595 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 549974288 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 549974288 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710687225 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710687225 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710687225 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710687225 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020499 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020499 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031595 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.031595 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 710702790 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710702790 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710702790 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710702790 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020514 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020514 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.031620 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023008 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023008 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023008 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023008 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24839.581348 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24839.581348 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42738.244280 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42738.244280 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30398.191337 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30398.191337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30398.191337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30398.191337 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10428893 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5642690 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 733632 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.023026 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023026 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023026 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023026 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26147.926670 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26147.926670 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44113.397678 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44113.397678 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 431500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 431500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31727.257337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31727.257337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31727.257337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31727.257337 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12329196 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5816488 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 735313 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.215428 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 86.632020 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.767276 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 89.300335 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3724933 # number of writebacks -system.cpu.dcache.writebacks::total 3724933 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3977017 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3977017 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3194676 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3194676 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7171693 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7171693 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7171693 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7171693 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296591 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296591 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883551 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883551 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725054 # number of writebacks +system.cpu.dcache.writebacks::total 3725054 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3985636 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3985636 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198598 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3198598 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7184234 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7184234 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7184234 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7184234 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296792 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296792 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883566 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883566 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 149546401000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 149546401000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65349746897 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 65349746897 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 46500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 46500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214896147897 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 214896147897 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214896147897 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 214896147897 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180358 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180358 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180358 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180358 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159255490500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 159255490500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71503545346 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71503545346 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 429500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 429500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230759035846 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230759035846 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230759035846 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230759035846 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013268 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses @@ -831,16 +831,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012917 system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20495.379418 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20495.379418 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34694.970774 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34694.970774 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 46500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 46500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23408.804341 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23408.804341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23408.804341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23408.804341 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.411839 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.411839 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37961.794461 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37961.794461 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 429500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 429500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index fe1996e1b..fe58c49f1 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.506354 # Number of seconds simulated -sim_ticks 506353996500 # Number of ticks simulated -final_tick 506353996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517386 # Number of seconds simulated +sim_ticks 517386177000 # Number of ticks simulated +final_tick 517386177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105319 # Simulator instruction rate (inst/s) -host_op_rate 117491 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34526611 # Simulator tick rate (ticks/s) -host_mem_usage 552892 # Number of bytes of host memory used -host_seconds 14665.62 # Real time elapsed on the host +host_inst_rate 165493 # Simulator instruction rate (inst/s) +host_op_rate 184620 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55435711 # Simulator tick rate (ticks/s) +host_mem_usage 502788 # Number of bytes of host memory used +host_seconds 9333.08 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143771904 # Number of bytes read from this memory -system.physmem.bytes_read::total 143819904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143728256 # Number of bytes read from this memory +system.physmem.bytes_read::total 143776256 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 48000 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 48000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70451968 # Number of bytes written to this memory -system.physmem.bytes_written::total 70451968 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 70436224 # Number of bytes written to this memory +system.physmem.bytes_written::total 70436224 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2246436 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2247186 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100812 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100812 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 94795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283935557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 284030352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 94795 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 94795 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 139135799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 139135799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 139135799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 94795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283935557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 423166152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2247186 # Total number of read requests seen -system.physmem.writeReqs 1100812 # Total number of write requests seen -system.physmem.cpureqs 3347998 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143819904 # Total number of bytes read from memory -system.physmem.bytesWritten 70451968 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143819904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70451968 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 672 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu.data 2245754 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246504 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100566 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100566 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 277796861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 277889635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92774 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92774 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136138589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136138589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136138589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 277796861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 414028224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246504 # Total number of read requests seen +system.physmem.writeReqs 1100566 # Total number of write requests seen +system.physmem.cpureqs 3350665 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143776256 # Total number of bytes read from memory +system.physmem.bytesWritten 70436224 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143776256 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70436224 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 651 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 139825 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 143804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 141798 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 141106 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 137923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 140335 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 141438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 140855 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 141349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 139500 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140412 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 140930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 137255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 141125 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 138862 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 139997 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69198 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 70413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69591 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 68873 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 67768 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 68429 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 68697 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68477 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 68286 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 68308 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 68629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 68528 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 67273 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70384 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 69023 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 68935 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 141458 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 139475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 141540 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 141707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 142337 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 139999 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 141291 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 140517 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 138551 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 136478 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140625 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 140699 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 141026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 139159 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 139234 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 141757 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69121 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 68349 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69146 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 69473 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 69281 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 69052 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68358 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 67825 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 67029 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 69533 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 69302 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 69105 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 68630 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 68505 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 68911 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 506353933500 # Total gap between requests +system.physmem.numWrRetry 3595 # Number of times wr buffer was full causing retry +system.physmem.totGap 517386097500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2247186 # Categorize read packet sizes +system.physmem.readPktSize::6 2246504 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1100812 # categorize write packet sizes +system.physmem.writePktSize::6 1104161 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1577555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 446581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 156376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 65982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1563469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 451045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68688 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,69 +138,69 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 44097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 27009597750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 102747541750 # Sum of mem lat for all requests -system.physmem.totBusLat 8986056000 # Total cycles spent in databus access -system.physmem.totBankLat 66751888000 # Total cycles spent in bank access -system.physmem.avgQLat 12022.89 # Average queueing delay per request -system.physmem.avgBankLat 29713.54 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 45736.44 # Average memory access latency -system.physmem.avgRdBW 284.03 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 139.14 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 284.03 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 139.14 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.64 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 11.52 # Average write queue length over time -system.physmem.readRowHits 914505 # Number of row buffer hits during reads -system.physmem.writeRowHits 189005 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 17.17 # Row buffer hit rate for writes -system.physmem.avgGap 151240.81 # Average gap between requests -system.cpu.branchPred.lookups 301930111 # Number of BP lookups -system.cpu.branchPred.condPredicted 248173247 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15201095 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 171785530 # Number of BTB lookups -system.cpu.branchPred.BTBHits 160276899 # Number of BTB hits +system.physmem.totQLat 51687050307 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 131176334057 # Sum of mem lat for all requests +system.physmem.totBusLat 11229265000 # Total cycles spent in databus access +system.physmem.totBankLat 68260018750 # Total cycles spent in bank access +system.physmem.avgQLat 23014.44 # Average queueing delay per request +system.physmem.avgBankLat 30393.81 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 58408.25 # Average memory access latency +system.physmem.avgRdBW 277.89 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 136.14 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 277.89 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 136.14 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.23 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.25 # Average read queue length over time +system.physmem.avgWrQLen 10.38 # Average write queue length over time +system.physmem.readRowHits 827421 # Number of row buffer hits during reads +system.physmem.writeRowHits 271011 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 24.62 # Row buffer hit rate for writes +system.physmem.avgGap 154578.81 # Average gap between requests +system.cpu.branchPred.lookups 303247532 # Number of BP lookups +system.cpu.branchPred.condPredicted 249450034 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15218023 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 175041543 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161435617 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.300582 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17551988 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.227030 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17558020 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 197 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,237 +244,238 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1012707994 # number of cpu cycles simulated +system.cpu.numCycles 1034772355 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 296178013 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2176838116 # Number of instructions fetch has processed -system.cpu.fetch.Branches 301930111 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 177828887 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 433076308 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 86433742 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 153009166 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 127 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 286734480 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5522368 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 951217236 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.532975 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.216056 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 298171037 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2186159989 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303247532 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 178993637 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435067157 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 87822274 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 155469980 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 663 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 288529454 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5728473 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 958589014 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.523348 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.213310 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 518141000 54.47% 54.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25031243 2.63% 57.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39020791 4.10% 61.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48260411 5.07% 66.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 42551008 4.47% 70.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46329866 4.87% 75.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38408585 4.04% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18543654 1.95% 81.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174930678 18.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 523521931 54.61% 54.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25504837 2.66% 57.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39086427 4.08% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48350867 5.04% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43002654 4.49% 70.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46446539 4.85% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38408277 4.01% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18709630 1.95% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175557852 18.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 951217236 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.298141 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.149522 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 327471231 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 131306156 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403441377 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20045518 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68952954 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46012127 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 693 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2358019040 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68952954 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 350612417 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61250936 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16584 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 398830274 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71554071 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2297211554 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 127534 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5036199 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58405264 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2272168650 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10608574023 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10608571065 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2958 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 958589014 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.293057 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.112697 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 329732299 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 133726687 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405163333 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20087198 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69879497 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46055159 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 678 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2366957956 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2458 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69879497 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 353264569 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 63487571 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18775 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400193247 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71745355 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2304463172 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 133379 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5038858 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58609164 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 17 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2279851599 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10642208168 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10642204755 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3413 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 565848720 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 855 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 852 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 158388501 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 623121269 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220470896 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86042540 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70771050 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2196546407 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 888 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2016009796 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3969588 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 468927262 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1107841980 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 718 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 951217236 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.119400 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906359 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 573531669 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 681 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 678 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 158828994 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624462299 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220966139 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86157140 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71007424 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2201342631 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 714 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018151759 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3999657 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 473702297 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1125076843 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 544 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 958589014 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.105336 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906417 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 271448438 28.54% 28.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 150881497 15.86% 44.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160823100 16.91% 61.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119315575 12.54% 73.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124031902 13.04% 86.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73881034 7.77% 94.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38429694 4.04% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9823536 1.03% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2582460 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 277560944 28.96% 28.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151408943 15.79% 44.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161184316 16.81% 61.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119741050 12.49% 74.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124054843 12.94% 87.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73850392 7.70% 94.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38407609 4.01% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9813288 1.02% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2567629 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 951217236 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 958589014 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 875964 3.67% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5764 0.02% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18242361 76.45% 80.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4736544 19.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 872793 3.65% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5710 0.02% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18283969 76.42% 80.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4762893 19.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1235492979 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925544 0.05% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 40 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 586540633 29.09% 90.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193050569 9.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236667909 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925774 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 51 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 24 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587469094 29.11% 90.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193088896 9.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2016009796 # Type of FU issued -system.cpu.iq.rate 1.990712 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23860633 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011836 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5011066759 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2665664471 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1956606463 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 290 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 554 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2039870285 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 144 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64705720 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018151759 # Type of FU issued +system.cpu.iq.rate 1.950334 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23925365 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011855 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5022817228 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2675235301 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957490366 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 326 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042076961 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 163 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64626006 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 137194500 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 273797 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192943 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45623851 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138535530 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 270863 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192819 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46119094 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3807412 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4653355 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68952954 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27155997 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1495704 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2196547422 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6100181 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 623121269 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220470896 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 826 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 473871 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 90052 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192943 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8142096 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9608050 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17750146 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1986410888 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573023734 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29598908 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69879497 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28935964 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1499081 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2201343583 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6151222 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624462299 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220966139 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 652 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 473850 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 90091 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192819 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8153540 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9614603 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17768143 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988132356 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573881676 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30019403 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 127 # number of nop insts executed -system.cpu.iew.exec_refs 763190345 # number of memory reference insts executed -system.cpu.iew.exec_branches 238305534 # Number of branches executed -system.cpu.iew.exec_stores 190166611 # Number of stores executed -system.cpu.iew.exec_rate 1.961484 # Inst execution rate -system.cpu.iew.wb_sent 1965043499 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1956606576 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295701772 # num instructions producing a value -system.cpu.iew.wb_consumers 2060221208 # num instructions consuming a value +system.cpu.iew.exec_nop 238 # number of nop insts executed +system.cpu.iew.exec_refs 764075762 # number of memory reference insts executed +system.cpu.iew.exec_branches 238335526 # Number of branches executed +system.cpu.iew.exec_stores 190194086 # Number of stores executed +system.cpu.iew.exec_rate 1.921323 # Inst execution rate +system.cpu.iew.wb_sent 1965930006 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957490498 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296385031 # num instructions producing a value +system.cpu.iew.wb_consumers 2061135459 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.932054 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.628914 # average fanout of values written-back +system.cpu.iew.wb_rate 1.891711 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.628966 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 473572340 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 478367692 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15200427 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 882264282 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.953013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.733344 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15217365 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 888709517 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.938849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.727981 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 395036396 44.78% 44.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 191994213 21.76% 66.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72477507 8.21% 74.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35260039 4.00% 78.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18947912 2.15% 80.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30765236 3.49% 84.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20067867 2.27% 86.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11401417 1.29% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106313695 12.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 401294450 45.15% 45.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192123349 21.62% 66.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72572906 8.17% 74.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35244916 3.97% 78.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18969010 2.13% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30763331 3.46% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20056672 2.26% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11441847 1.29% 88.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106243036 11.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 882264282 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 888709517 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -485,192 +486,192 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106313695 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106243036 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2972596181 # The number of ROB reads -system.cpu.rob.rob_writes 4462393115 # The number of ROB writes -system.cpu.timesIdled 1008109 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 61490758 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2983907427 # The number of ROB reads +system.cpu.rob.rob_writes 4472910463 # The number of ROB writes +system.cpu.timesIdled 1017511 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76183341 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.655660 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.655660 # CPI: Total CPI of All Threads -system.cpu.ipc 1.525181 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.525181 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9949148949 # number of integer regfile reads -system.cpu.int_regfile_writes 1936492974 # number of integer regfile writes -system.cpu.fp_regfile_reads 113 # number of floating regfile reads -system.cpu.fp_regfile_writes 115 # number of floating regfile writes -system.cpu.misc_regfile_reads 737540247 # number of misc regfile reads +system.cpu.cpi 0.669945 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.669945 # CPI: Total CPI of All Threads +system.cpu.ipc 1.492660 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.492660 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956386896 # number of integer regfile reads +system.cpu.int_regfile_writes 1937427158 # number of integer regfile writes +system.cpu.fp_regfile_reads 137 # number of floating regfile reads +system.cpu.fp_regfile_writes 146 # number of floating regfile writes +system.cpu.misc_regfile_reads 737590270 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.icache.replacements 23 # number of replacements -system.cpu.icache.tagsinuse 625.185145 # Cycle average of tags in use -system.cpu.icache.total_refs 286733320 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 778 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 368551.825193 # Average number of references to valid blocks. +system.cpu.icache.replacements 21 # number of replacements +system.cpu.icache.tagsinuse 626.247624 # Cycle average of tags in use +system.cpu.icache.total_refs 288528273 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 370382.892169 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 625.185145 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.305266 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.305266 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 286733320 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286733320 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286733320 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 286733320 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 286733320 # number of overall hits -system.cpu.icache.overall_hits::total 286733320 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1160 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1160 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1160 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1160 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1160 # number of overall misses -system.cpu.icache.overall_misses::total 1160 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 59910000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 59910000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 59910000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 59910000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 59910000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 59910000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 286734480 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 286734480 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 286734480 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 286734480 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 286734480 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 286734480 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 626.247624 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.305785 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.305785 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 288528273 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 288528273 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 288528273 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 288528273 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 288528273 # number of overall hits +system.cpu.icache.overall_hits::total 288528273 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1181 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1181 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1181 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1181 # number of overall misses +system.cpu.icache.overall_misses::total 1181 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66140500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66140500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66140500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66140500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66140500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66140500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 288529454 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 288529454 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 288529454 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 288529454 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 288529454 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 288529454 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51646.551724 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51646.551724 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51646.551724 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51646.551724 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56003.810330 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56003.810330 # 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number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 1100566 # number of writebacks +system.cpu.l2cache.writebacks::total 1100566 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 750 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419746 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1420496 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826690 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 826690 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419098 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1419848 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826656 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 826656 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 750 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2246436 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2247186 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2245754 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2246504 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 750 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2246436 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2247186 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32919184 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80176207714 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80209126898 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48315790009 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48315790009 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32919184 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128491997723 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 128524916907 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32919184 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128491997723 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 128524916907 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184166 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184245 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436614 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436614 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233943 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.234003 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233943 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.234003 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43892.245333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56472.219477 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56465.577445 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58444.870519 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58444.870519 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43892.245333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57198.156423 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57193.715566 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43892.245333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57198.156423 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57193.715566 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 2245754 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2246504 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35808198 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96120907910 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96156716108 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60148132877 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60148132877 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35808198 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156269040787 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 156304848985 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35808198 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156269040787 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 156304848985 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962773 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184096 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184175 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436587 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436587 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962773 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233886 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233945 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962773 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233886 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233945 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47744.264000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67733.805495 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67723.246508 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72760.777006 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72760.777006 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47744.264000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69584.220171 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69576.928857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47744.264000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69584.220171 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69576.928857 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9598379 # number of replacements -system.cpu.dcache.tagsinuse 4087.934747 # Cycle average of tags in use -system.cpu.dcache.total_refs 656008169 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9602475 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.316571 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3424422000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.934747 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 488954223 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 488954223 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167053823 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167053823 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.replacements 9597826 # number of replacements +system.cpu.dcache.tagsinuse 4088.019917 # Cycle average of tags in use +system.cpu.dcache.total_refs 656092202 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9601922 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.329258 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3440649000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4088.019917 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998052 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 489045122 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489045122 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167046955 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167046955 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656008046 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656008046 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656008046 # number of overall hits -system.cpu.dcache.overall_hits::total 656008046 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11476242 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11476242 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5532224 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5532224 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656092077 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656092077 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656092077 # number of overall hits +system.cpu.dcache.overall_hits::total 656092077 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11476427 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11476427 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5539092 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5539092 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17008466 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17008466 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17008466 # number of overall misses -system.cpu.dcache.overall_misses::total 17008466 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 299283762000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 299283762000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 216949721927 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 216949721927 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 516233483927 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 516233483927 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 516233483927 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 516233483927 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500430465 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500430465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17015519 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17015519 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17015519 # number of overall misses +system.cpu.dcache.overall_misses::total 17015519 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 322914399500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 322914399500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 229337265001 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 229337265001 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 552251664501 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 552251664501 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 552251664501 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 552251664501 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500521549 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500521549 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673016512 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673016512 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673016512 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673016512 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032055 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032055 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025272 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025272 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025272 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025272 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26078.550975 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26078.550975 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39215.643099 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39215.643099 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30351.560448 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30351.560448 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30351.560448 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30351.560448 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19781174 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 987477 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1172505 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64541 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.870865 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15.299995 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673107596 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673107596 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673107596 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673107596 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022929 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022929 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032095 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025279 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025279 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025279 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025279 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28137.189345 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28137.189345 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41403.404204 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41403.404204 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32455.763736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32455.763736 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26327984 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1057907 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1182334 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64553 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.267806 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16.388193 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781550 # number of writebacks -system.cpu.dcache.writebacks::total 3781550 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767179 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3767179 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638811 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3638811 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3781250 # number of writebacks +system.cpu.dcache.writebacks::total 3781250 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767955 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3767955 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645642 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3645642 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7405990 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7405990 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7405990 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7405990 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709063 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7709063 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893413 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893413 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9602476 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9602476 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9602476 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9602476 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170550521000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 170550521000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71842126604 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71842126604 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242392647604 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 242392647604 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242392647604 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 242392647604 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7413597 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7413597 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7413597 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7413597 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708472 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708472 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893450 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893450 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9601922 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9601922 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9601922 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9601922 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186178488500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 186178488500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508071510 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508071510 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269686560010 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 269686560010 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269686560010 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 269686560010 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22123.378808 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22123.378808 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37943.188625 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37943.188625 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24152.450512 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24152.450512 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44103.658143 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44103.658143 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |