diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/long/se/60.bzip2 | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/long/se/60.bzip2')
18 files changed, 1788 insertions, 1788 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 4a4e79f41..38e3365ee 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout index 74ab835bf..1e72565e9 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:25:40 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 10:10:01 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 991340143500 because target called exit() +Exiting @ tick 996061088500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 35d38838f..def42a9fe 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.991340 # Number of seconds simulated -sim_ticks 991340143500 # Number of ticks simulated -final_tick 991340143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.996061 # Number of seconds simulated +sim_ticks 996061088500 # Number of ticks simulated +final_tick 996061088500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147354 # Simulator instruction rate (inst/s) -host_op_rate 147354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 80272080 # Simulator tick rate (ticks/s) -host_mem_usage 218972 # Number of bytes of host memory used -host_seconds 12349.75 # Real time elapsed on the host +host_inst_rate 139633 # Simulator instruction rate (inst/s) +host_op_rate 139633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76428343 # Simulator tick rate (ticks/s) +host_mem_usage 218940 # Number of bytes of host memory used +host_seconds 13032.61 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137579712 # Number of bytes read from this memory -system.physmem.bytes_read::total 137634688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137579648 # Number of bytes read from this memory +system.physmem.bytes_read::total 137634624 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67105088 # Number of bytes written to this memory -system.physmem.bytes_written::total 67105088 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67105024 # Number of bytes written to this memory +system.physmem.bytes_written::total 67105024 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2149683 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2150542 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048517 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048517 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 138781540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138836996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 67691285 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 67691285 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 67691285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 138781540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 206528281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 2149682 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2150541 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048516 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048516 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 55193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 138123705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138178898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55193 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55193 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 67370390 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 67370390 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 67370390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 138123705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 205549288 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444614343 # DTB read hits +system.cpu.dtb.read_hits 444620723 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449511421 # DTB read accesses -system.cpu.dtb.write_hits 160920087 # DTB write hits +system.cpu.dtb.read_accesses 449517801 # DTB read accesses +system.cpu.dtb.write_hits 160920434 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162621391 # DTB write accesses -system.cpu.dtb.data_hits 605534430 # DTB hits +system.cpu.dtb.write_accesses 162621738 # DTB write accesses +system.cpu.dtb.data_hits 605541157 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612132812 # DTB accesses -system.cpu.itb.fetch_hits 232194533 # ITB hits +system.cpu.dtb.data_accesses 612139539 # DTB accesses +system.cpu.itb.fetch_hits 232151959 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232194555 # ITB accesses +system.cpu.itb.fetch_accesses 232151981 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1982680288 # number of cpu cycles simulated +system.cpu.numCycles 1992122178 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 328915928 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 253819011 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140072488 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 231593889 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 138169193 # Number of BTB hits +system.cpu.branch_predictor.lookups 328832264 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 253784019 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 139998376 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 232594122 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 138120343 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 59.660120 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 175201939 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 153713989 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669764044 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 59.382560 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 175107833 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 153724431 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1669698374 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3045966661 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 236 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3045900991 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 581 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651015392 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617989806 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 121318277 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 12155753 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133474030 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81726039 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.023228 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139614733 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651085046 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617993265 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 121277812 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 12122106 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133399918 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81800180 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.988781 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139625101 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746574278 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1749883167 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7486032 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 405569141 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1577111147 # Number of cycles cpu stages are processed. -system.cpu.activity 79.544400 # Percentage of cycles cpu is active +system.cpu.timesIdled 7972682 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 415150633 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576971545 # Number of cycles cpu stages are processed. +system.cpu.activity 79.160383 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.089516 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.094705 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.089516 # CPI: Total CPI of All Threads -system.cpu.ipc 0.917838 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.094705 # CPI: Total CPI of All Threads +system.cpu.ipc 0.913488 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.917838 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 791779407 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190900881 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.065200 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1050371352 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932308936 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 47.022656 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1008674680 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 974005608 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.125702 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1572973951 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409706337 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.664266 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 959730175 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022950113 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.594305 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.913488 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 801357098 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190765080 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.773697 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1059714238 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932407940 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.804757 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1018188148 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 973934030 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.889272 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1582467246 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409654932 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.563745 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 969329070 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022793108 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.341887 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 666.725255 # Cycle average of tags in use -system.cpu.icache.total_refs 232193463 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 666.783228 # Cycle average of tags in use +system.cpu.icache.total_refs 232150871 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270306.708964 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270257.125728 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 666.725255 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325549 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325549 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232193463 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232193463 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232193463 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232193463 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232193463 # number of overall hits -system.cpu.icache.overall_hits::total 232193463 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1067 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1067 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1067 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1067 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1067 # number of overall misses -system.cpu.icache.overall_misses::total 1067 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58495000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58495000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58495000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58495000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58495000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58495000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232194530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232194530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232194530 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232194530 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232194530 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232194530 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 666.783228 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325578 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325578 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 232150871 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232150871 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232150871 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232150871 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232150871 # number of overall hits +system.cpu.icache.overall_hits::total 232150871 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1085 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1085 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1085 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1085 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1085 # number of overall misses +system.cpu.icache.overall_misses::total 1085 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60468000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60468000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60468000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60468000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60468000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60468000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232151956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232151956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232151956 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232151956 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232151956 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232151956 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54821.930647 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54821.930647 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54821.930647 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54821.930647 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54821.930647 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54821.930647 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55730.875576 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55730.875576 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55730.875576 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55730.875576 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55730.875576 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55730.875576 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 85000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 114500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 28333.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 22900 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 208 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 208 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 208 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 226 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 226 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 226 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 226 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47379000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47379000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47379000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53474.970896 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53474.970896 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53474.970896 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53474.970896 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53474.970896 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53474.970896 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55155.995343 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55155.995343 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107366 # number of replacements -system.cpu.dcache.tagsinuse 4082.290547 # Cycle average of tags in use -system.cpu.dcache.total_refs 595076211 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111462 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310727 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12667784000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.290547 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996653 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996653 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271439 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271439 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157804772 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157804772 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595076211 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595076211 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595076211 # number of overall hits -system.cpu.dcache.overall_hits::total 595076211 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324224 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324224 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2923730 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2923730 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10247954 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10247954 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10247954 # number of overall misses -system.cpu.dcache.overall_misses::total 10247954 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 162150578000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 162150578000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 105068682500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 105068682500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 267219260500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 267219260500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 267219260500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 267219260500 # number of overall miss cycles +system.cpu.dcache.replacements 9107309 # number of replacements +system.cpu.dcache.tagsinuse 4082.354199 # Cycle average of tags in use +system.cpu.dcache.total_refs 595073835 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111405 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.310875 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12655884000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.354199 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996669 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437271435 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437271435 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 157802400 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157802400 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595073835 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 130053734500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 130053734500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 296550291000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 296550291000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 296550291000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 296550291000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -262,54 +262,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # 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average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35936.520301 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26075.376656 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26075.376656 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26075.376656 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26075.376656 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10790500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7928721000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2625 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 208163 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4110.666667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 38089.002368 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018205 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.018205 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016934 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016934 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016934 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016934 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.301138 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.301138 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44446.070062 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44446.070062 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28930.804277 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28930.804277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28930.804277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28930.804277 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 76478500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8150814500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14619 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 208452 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5231.445379 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39101.637307 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3389687 # number of writebacks -system.cpu.dcache.writebacks::total 3389687 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101944 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101944 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1034548 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1034548 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1136492 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1136492 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1136492 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1136492 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 3389633 # number of writebacks +system.cpu.dcache.writebacks::total 3389633 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101948 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101948 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1036977 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1036977 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1138925 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1138925 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1138925 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1138925 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111462 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111462 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111462 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111462 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137265020500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 137265020500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54890953000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 54890953000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192155973500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 192155973500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 192155973500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 192155973500 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86122652500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 2149682 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2150541 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35698000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54780311000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54816009000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32410594000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32410594000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35698000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87190905000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87226603000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35698000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87190905000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87226603000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188435 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417455 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417455 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417466 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417466 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235933 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.236005 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.861467 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40024.167616 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.241229 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40086.156385 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40086.156385 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.861467 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40046.914592 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40046.952117 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.861467 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40046.914592 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40046.952117 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235933 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.236005 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41557.625146 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40254.422230 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40255.244321 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41086.918601 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41086.918601 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40559.908396 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40560.306918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40559.908396 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40560.306918 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index b3f63cedd..2f4837fe9 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 41442f622..3e5b31249 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:26:23 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 10:10:10 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 607216877500 because target called exit() +Exiting @ tick 621254733000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 66e8bd283..3ccb6ec23 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.607217 # Number of seconds simulated -sim_ticks 607216877500 # Number of ticks simulated -final_tick 607216877500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.621255 # Number of seconds simulated +sim_ticks 621254733000 # Number of ticks simulated +final_tick 621254733000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 209626 # Simulator instruction rate (inst/s) -host_op_rate 209626 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73321119 # Simulator tick rate (ticks/s) -host_mem_usage 219996 # Number of bytes of host memory used -host_seconds 8281.61 # Real time elapsed on the host +host_inst_rate 206958 # Simulator instruction rate (inst/s) +host_op_rate 206958 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74061263 # Simulator tick rate (ticks/s) +host_mem_usage 219968 # Number of bytes of host memory used +host_seconds 8388.39 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138164352 # Number of bytes read from this memory -system.physmem.bytes_read::total 138226304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67205952 # Number of bytes written to this memory -system.physmem.bytes_written::total 67205952 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2158818 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2159786 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050093 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050093 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 102026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 227537075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 227639101 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 102026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 102026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 110678663 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 110678663 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 110678663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 102026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 227537075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 338317764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138177216 # Number of bytes read from this memory +system.physmem.bytes_read::total 138239104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67208512 # Number of bytes written to this memory +system.physmem.bytes_written::total 67208512 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 967 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2159019 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2159986 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050133 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050133 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 99618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 222416359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 222515977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 99618 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 99618 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 108181891 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 108181891 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 108181891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 99618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 222416359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 330697869 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 612238035 # DTB read hits -system.cpu.dtb.read_misses 10898868 # DTB read misses +system.cpu.dtb.read_hits 614267388 # DTB read hits +system.cpu.dtb.read_misses 10994218 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 623136903 # DTB read accesses -system.cpu.dtb.write_hits 208056215 # DTB write hits -system.cpu.dtb.write_misses 6766994 # DTB write misses +system.cpu.dtb.read_accesses 625261606 # DTB read accesses +system.cpu.dtb.write_hits 208720588 # DTB write hits +system.cpu.dtb.write_misses 6852950 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 214823209 # DTB write accesses -system.cpu.dtb.data_hits 820294250 # DTB hits -system.cpu.dtb.data_misses 17665862 # DTB misses +system.cpu.dtb.write_accesses 215573538 # DTB write accesses +system.cpu.dtb.data_hits 822987976 # DTB hits +system.cpu.dtb.data_misses 17847168 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 837960112 # DTB accesses -system.cpu.itb.fetch_hits 401011528 # ITB hits -system.cpu.itb.fetch_misses 57 # ITB misses +system.cpu.dtb.data_accesses 840835144 # DTB accesses +system.cpu.itb.fetch_hits 402675877 # ITB hits +system.cpu.itb.fetch_misses 58 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 401011585 # ITB accesses +system.cpu.itb.fetch_accesses 402675935 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,247 +67,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1214433756 # number of cpu cycles simulated +system.cpu.numCycles 1242509467 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 380951023 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 293099658 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18933784 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 266477220 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 262392566 # Number of BTB hits +system.cpu.BPredUnit.lookups 383372990 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 295235565 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 19006052 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 268408458 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 264104025 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25151704 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6168 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 412376649 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3157323952 # Number of instructions fetch has processed -system.cpu.fetch.Branches 380951023 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 287544270 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 576306152 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 134891835 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 111419989 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1063 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 401011528 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10506825 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1209281794 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.610908 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.168401 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25197943 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6076 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 414160425 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3172269212 # Number of instructions fetch has processed +system.cpu.fetch.Branches 383372990 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 289301968 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 579083206 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 137694854 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 132940581 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1360 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 402675877 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10477889 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1238022002 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.562369 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.158541 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 632975642 52.34% 52.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43351030 3.58% 55.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22268396 1.84% 57.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40872577 3.38% 61.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 127179039 10.52% 71.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63789232 5.27% 76.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40665333 3.36% 80.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30280275 2.50% 82.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 207900270 17.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 658938796 53.23% 53.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43587849 3.52% 56.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22400320 1.81% 58.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 41027424 3.31% 61.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127967453 10.34% 72.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63937343 5.16% 77.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40820174 3.30% 80.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30420264 2.46% 83.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 208922379 16.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1209281794 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.313686 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.599832 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 441212287 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 97730865 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 545630156 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 15531465 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 109177021 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60290905 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1025 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3078047382 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2151 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 109177021 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 462067522 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 51929068 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5163 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 539154184 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46948836 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2995870549 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 446955 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1708785 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42808765 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2241183009 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3870137990 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3868740839 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1397151 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1238022002 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.308547 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.553115 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 444879640 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 117490931 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 546452553 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17363359 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 111835519 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 60534072 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 962 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3092225969 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2145 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 111835519 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 466447238 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 65379308 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5467 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 540801711 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53552759 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3009893694 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 588891 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2795172 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 47908313 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2251120190 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3888621958 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3887220740 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1401218 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 864980046 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 207 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 206 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 100505126 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 676579077 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 251278116 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 61563067 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 34698773 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2690247704 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 874917227 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 215 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 214 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112891088 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679356489 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 252372715 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 62271668 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36485662 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2703868851 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 183 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2489728191 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3267337 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 942739143 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 400071480 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 2499086402 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3468008 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 959949757 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 407382923 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 154 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1209281794 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.058849 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971213 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1238022002 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.018612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.960549 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 378679312 31.31% 31.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 195809975 16.19% 47.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 182681515 15.11% 62.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 152412696 12.60% 75.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 135959135 11.24% 86.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80206603 6.63% 93.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 63601344 5.26% 98.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14610233 1.21% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5320981 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 396920026 32.06% 32.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203237579 16.42% 48.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185771607 15.01% 63.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153281748 12.38% 75.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 136530779 11.03% 86.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79975547 6.46% 93.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 62882805 5.08% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14212604 1.15% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5209307 0.42% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1209281794 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1238022002 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1977743 10.56% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12229984 65.27% 75.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4528924 24.17% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1901972 10.18% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12247269 65.56% 75.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4530432 24.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1627060855 65.35% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 100 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 286 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 14 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 171 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 640749326 25.74% 91.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 221917384 8.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1633606519 65.37% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 96 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 295 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 168 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 36 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 642839630 25.72% 91.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 222639616 8.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2489728191 # Type of FU issued -system.cpu.iq.rate 2.050114 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18736651 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007526 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6208757898 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3631737993 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2386612184 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1984266 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1351861 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 870224 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2507489711 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 975131 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57077193 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2499086402 # Type of FU issued +system.cpu.iq.rate 2.011322 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18679673 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007475 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6256352202 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3662566047 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2395383662 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1990285 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1357397 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 872084 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2516787863 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 978212 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57513083 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 231983414 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 247523 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 104727 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 90549614 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234760826 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 254713 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 106352 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 91644213 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 172 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 177103 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 271 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 267185 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 109177021 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 19521566 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 973961 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2832586299 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17875212 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 676579077 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 251278116 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 111835519 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23640124 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1166146 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2847163562 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17865598 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679356489 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 252372715 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 183 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 178484 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13307 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 104727 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13292243 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8865054 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22157297 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2437364251 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 623138442 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 52363940 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 265739 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14899 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 106352 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13291147 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8879247 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22170394 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2446896238 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625263073 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 52190164 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142338412 # number of nop insts executed -system.cpu.iew.exec_refs 837961692 # number of memory reference insts executed -system.cpu.iew.exec_branches 298501873 # Number of branches executed -system.cpu.iew.exec_stores 214823250 # Number of stores executed -system.cpu.iew.exec_rate 2.006996 # Inst execution rate -system.cpu.iew.wb_sent 2416135407 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2387482408 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1367770503 # num instructions producing a value -system.cpu.iew.wb_consumers 1732591741 # num instructions consuming a value +system.cpu.iew.exec_nop 143294528 # number of nop insts executed +system.cpu.iew.exec_refs 840836661 # number of memory reference insts executed +system.cpu.iew.exec_branches 299907540 # Number of branches executed +system.cpu.iew.exec_stores 215573588 # Number of stores executed +system.cpu.iew.exec_rate 1.969318 # Inst execution rate +system.cpu.iew.wb_sent 2424978134 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2396255746 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1371174091 # num instructions producing a value +system.cpu.iew.wb_consumers 1736703047 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.965922 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789436 # average fanout of values written-back +system.cpu.iew.wb_rate 1.928561 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789527 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitCommittedOps 1819780126 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 773736355 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 793041487 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18932893 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1100104773 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.654188 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.513944 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 19005172 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1126186483 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.615878 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.496171 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 575678608 52.33% 52.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 180745216 16.43% 68.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90628498 8.24% 77.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53598095 4.87% 81.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36474012 3.32% 85.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28175112 2.56% 87.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22568883 2.05% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23092069 2.10% 91.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 89144280 8.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 601057240 53.37% 53.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 181431262 16.11% 69.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 90818871 8.06% 77.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53582935 4.76% 82.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36462614 3.24% 85.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28190767 2.50% 88.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22584019 2.01% 90.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22816288 2.03% 92.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89242487 7.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1100104773 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1126186483 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 89144280 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 89242487 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3518697774 # The number of ROB reads -system.cpu.rob.rob_writes 5296336807 # The number of ROB writes -system.cpu.timesIdled 353272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5151962 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3563986409 # The number of ROB reads +system.cpu.rob.rob_writes 5337596119 # The number of ROB writes +system.cpu.timesIdled 386257 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4487465 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.699541 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.699541 # CPI: Total CPI of All Threads -system.cpu.ipc 1.429509 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.429509 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3277031179 # number of integer regfile reads -system.cpu.int_regfile_writes 1915203405 # number of integer regfile writes -system.cpu.fp_regfile_reads 51821 # number of floating regfile reads -system.cpu.fp_regfile_writes 555 # number of floating regfile writes +system.cpu.cpi 0.715713 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.715713 # CPI: Total CPI of All Threads +system.cpu.ipc 1.397208 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.397208 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3289961910 # number of integer regfile reads +system.cpu.int_regfile_writes 1921843103 # number of integer regfile writes +system.cpu.fp_regfile_reads 52840 # number of floating regfile reads +system.cpu.fp_regfile_writes 576 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 769.354058 # Cycle average of tags in use -system.cpu.icache.total_refs 401010025 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 968 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 414266.554752 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 769.288412 # Cycle average of tags in use +system.cpu.icache.total_refs 402674417 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 967 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 416416.149948 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 769.354058 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.375661 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.375661 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 401010025 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 401010025 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 401010025 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 401010025 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 401010025 # number of overall hits -system.cpu.icache.overall_hits::total 401010025 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1503 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1503 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1503 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1503 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1503 # number of overall misses -system.cpu.icache.overall_misses::total 1503 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50592000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50592000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50592000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50592000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50592000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50592000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 401011528 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 401011528 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 401011528 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 401011528 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 401011528 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 401011528 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 769.288412 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.375629 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.375629 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 402674417 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 402674417 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 402674417 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 402674417 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 402674417 # number of overall hits +system.cpu.icache.overall_hits::total 402674417 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1460 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1460 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1460 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1460 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1460 # number of overall misses +system.cpu.icache.overall_misses::total 1460 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51984000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51984000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51984000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51984000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51984000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51984000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 402675877 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 402675877 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 402675877 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 402675877 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 402675877 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 402675877 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33660.678643 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 33660.678643 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 33660.678643 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 33660.678643 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 33660.678643 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 33660.678643 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35605.479452 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35605.479452 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35605.479452 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35605.479452 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35605.479452 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35605.479452 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,301 +390,301 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 535 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 535 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 535 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 535 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 535 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 535 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 968 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34430500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 34430500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34430500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 34430500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34430500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 34430500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 493 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 493 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 493 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 493 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 493 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 493 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 967 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 967 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 967 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 967 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 967 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 967 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36487500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36487500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36487500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36487500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36487500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36487500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35568.698347 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35568.698347 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35568.698347 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35568.698347 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35568.698347 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35568.698347 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37732.678387 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37732.678387 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37732.678387 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37732.678387 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37732.678387 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37732.678387 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176274 # number of replacements -system.cpu.dcache.tagsinuse 4085.917411 # Cycle average of tags in use -system.cpu.dcache.total_refs 700820301 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180370 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.339004 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5686444000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4085.917411 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997538 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997538 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 545002306 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 545002306 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155817990 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155817990 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 700820296 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 700820296 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 700820296 # number of overall hits -system.cpu.dcache.overall_hits::total 700820296 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10067033 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10067033 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4910512 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4910512 # number of WriteReq misses +system.cpu.dcache.replacements 9177386 # number of replacements +system.cpu.dcache.tagsinuse 4086.021231 # Cycle average of tags in use +system.cpu.dcache.total_refs 702056589 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9181482 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 76.464408 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5710472000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.021231 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997564 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997564 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 546233301 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 546233301 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155823284 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155823284 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 702056585 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 702056585 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 702056585 # number of overall hits +system.cpu.dcache.overall_hits::total 702056585 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10361176 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10361176 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4905218 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4905218 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 14977545 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 14977545 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 14977545 # number of overall misses -system.cpu.dcache.overall_misses::total 14977545 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 147978050000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 147978050000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 133621980034 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 133621980034 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 49500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 49500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 281600030034 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 281600030034 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 281600030034 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 281600030034 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 555069339 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 555069339 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 15266394 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15266394 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15266394 # number of overall misses +system.cpu.dcache.overall_misses::total 15266394 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 211386484000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 211386484000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 166231514528 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 166231514528 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 71000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 377617998528 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 377617998528 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 377617998528 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 377617998528 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 556594477 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 556594477 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 715797841 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 715797841 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 715797841 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 715797841 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018137 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.018137 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030552 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.030552 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.285714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.285714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.020924 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.020924 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.020924 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.020924 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14699.271374 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14699.271374 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27211.415028 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27211.415028 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 24750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 24750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18801.481153 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18801.481153 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18801.481153 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18801.481153 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 94480762 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2148368000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 33098 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65117 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2854.576168 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 32992.429012 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 717322979 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 717322979 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 717322979 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 717322979 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018615 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.018615 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030519 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.030519 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021282 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021282 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20401.784894 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20401.784894 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33888.710864 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33888.710864 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24735.245175 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24735.245175 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24735.245175 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24735.245175 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 705051055 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1696782500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 102430 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65119 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6883.247633 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26056.642455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3416687 # number of writebacks -system.cpu.dcache.writebacks::total 3416687 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2770476 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2770476 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3026700 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3026700 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3417165 # number of writebacks +system.cpu.dcache.writebacks::total 3417165 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3063278 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3063278 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3021635 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3021635 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 5797176 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 5797176 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 5797176 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 5797176 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296557 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296557 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883812 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883812 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 6084913 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6084913 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6084913 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6084913 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7297898 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7297898 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 35740755693 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 102735730193 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 102735730193 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 102735730193 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 102735730193 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013145 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013145 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # 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average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 18972.570348 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11190.806186 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11190.806186 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11190.806186 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11190.806186 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 9181481 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9181481 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9181481 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44665370500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26000882433 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26000882433 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32063500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 70634189433 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 70666252933 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32063500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 70634189433 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 70666252933 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188625 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188732 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415383 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415383 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188629 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188737 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415389 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235156 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235237 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235149 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.235230 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235156 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.235237 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31170.454545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31168.792523 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31168.793691 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31218.982505 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31218.982505 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31170.454545 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31186.984961 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31186.977552 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31170.454545 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31186.984961 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31186.977552 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235149 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.235230 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33157.704240 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32423.023363 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32423.539084 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33231.107393 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33231.107393 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33157.704240 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32715.872085 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32716.069888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33157.704240 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32715.872085 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32716.069888 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 51c5aee6c..c5fc5fd4c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout index 80ad9dac8..2743afc35 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:33:25 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 10:19:14 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2640486390000 because target called exit() +Exiting @ tick 2642007987000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 02104b02f..15b5a360c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.640486 # Number of seconds simulated -sim_ticks 2640486390000 # Number of ticks simulated -final_tick 2640486390000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.642008 # Number of seconds simulated +sim_ticks 2642007987000 # Number of ticks simulated +final_tick 2642007987000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2162683 # Simulator instruction rate (inst/s) -host_op_rate 2162683 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3138035754 # Simulator tick rate (ticks/s) -host_mem_usage 218976 # Number of bytes of host memory used -host_seconds 841.45 # Real time elapsed on the host +host_inst_rate 1913242 # Simulator instruction rate (inst/s) +host_op_rate 1913242 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2777698581 # Simulator tick rate (ticks/s) +host_mem_usage 217920 # Number of bytes of host memory used +host_seconds 951.15 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 2149692 # Nu system.physmem.num_reads::total 2150494 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1048525 # Number of write requests responded to by this memory system.physmem.num_writes::total 1048525 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52104146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52123585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19439 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19439 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 25414106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 25414106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 25414106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19439 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52104146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77537690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 19428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52074138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52093565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19428 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19428 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 25399469 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 25399469 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 25399469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52074138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77493034 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5280972780 # number of cpu cycles simulated +system.cpu.numCycles 5284015974 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -86,16 +86,16 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5280972780 # Number of busy cycles +system.cpu.num_busy_cycles 5284015974 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 612.518964 # Cycle average of tags in use +system.cpu.icache.tagsinuse 612.519467 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 612.518964 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 612.519467 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.299082 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.299082 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44912000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44912000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44912000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44912000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44912000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44912000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45149000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45149000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45149000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45149000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45149000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45149000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56295.511222 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56295.511222 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56295.511222 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56295.511222 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56295.511222 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56295.511222 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42506000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42506000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42506000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42506000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42506000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42506000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42743000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42743000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42743000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42743000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42743000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42743000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53295.511222 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53295.511222 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53295.511222 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53295.511222 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53295.511222 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53295.511222 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.tagsinuse 4079.363452 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.366966 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40985601000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4079.363452 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995938 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995938 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 40989979000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4079.366966 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995939 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995939 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 158270882000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 158270882000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 59580458000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 59580458000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 217851340000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 217851340000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 217851340000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 217851340000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 158759423000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 158759423000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59584620000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59584620000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 218344043000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 218344043000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 218344043000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 218344043000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21913.847918 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21913.847918 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31535.397921 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31535.397921 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23908.878376 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23908.878376 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23908.878376 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23908.878376 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21981.490261 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21981.490261 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31537.600830 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31537.600830 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23962.951838 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23962.951838 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23962.951838 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23962.951838 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136603640000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 136603640000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53912498000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53912498000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190516138000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 190516138000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190516138000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 190516138000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137092181000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 137092181000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53916660000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53916660000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191008841000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191008841000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191008841000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191008841000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18913.847918 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18913.847918 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28535.397921 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.397921 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20908.878376 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20908.878376 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20908.878376 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20908.878376 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18981.490261 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18981.490261 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28537.600830 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28537.600830 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20962.951838 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20962.951838 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20962.951838 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20962.951838 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2133721 # number of replacements -system.cpu.l2cache.tagsinuse 30166.064442 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30166.534681 # Cycle average of tags in use system.cpu.l2cache.total_refs 8449191 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2163414 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 3.905490 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 498208075000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14372.212156 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 37.660543 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15756.191744 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.438605 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 498438853000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14372.614424 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 37.649566 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15756.270691 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.438617 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001149 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.480841 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.920595 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.480843 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.920610 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 5861531 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5861531 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3389919 # number of Writeback hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index c94040a4a..cb0b4a9a4 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -497,7 +497,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -529,7 +529,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 1148e0586..963dfaf37 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:20:26 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 16:38:23 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 458035985000 because target called exit() +Exiting @ tick 479150606000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index f8f6b4a6a..9750f5933 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.458036 # Number of seconds simulated -sim_ticks 458035985000 # Number of ticks simulated -final_tick 458035985000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.479151 # Number of seconds simulated +sim_ticks 479150606000 # Number of ticks simulated +final_tick 479150606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 197390 # Simulator instruction rate (inst/s) -host_op_rate 220203 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58535443 # Simulator tick rate (ticks/s) -host_mem_usage 234800 # Number of bytes of host memory used -host_seconds 7824.93 # Real time elapsed on the host -sim_insts 1544563073 # Number of instructions simulated -sim_ops 1723073885 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156358784 # Number of bytes read from this memory -system.physmem.bytes_read::total 156407104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71946432 # Number of bytes written to this memory -system.physmem.bytes_written::total 71946432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2443106 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2443861 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1124163 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1124163 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 105494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 341367904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 341473398 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 105494 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 105494 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 157075938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 157075938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 157075938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 105494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 341367904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 498549336 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 194711 # Simulator instruction rate (inst/s) +host_op_rate 217215 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60402792 # Simulator tick rate (ticks/s) +host_mem_usage 234724 # Number of bytes of host memory used +host_seconds 7932.59 # Real time elapsed on the host +sim_insts 1544563028 # Number of instructions simulated +sim_ops 1723073840 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156296384 # Number of bytes read from this memory +system.physmem.bytes_read::total 156344896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71934976 # Number of bytes written to this memory +system.physmem.bytes_written::total 71934976 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2442131 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2442889 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1123984 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1123984 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 101246 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 326194691 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 326295937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101246 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101246 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 150130199 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 150130199 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 150130199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 326194691 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 476426136 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,322 +77,322 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 916071971 # number of cpu cycles simulated +system.cpu.numCycles 958301213 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 300386365 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 246254548 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16072669 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 170403157 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 156239351 # Number of BTB hits +system.cpu.BPredUnit.lookups 302333500 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 248015603 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16105989 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 168718741 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 157776197 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18292614 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 292465712 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2157283635 # Number of instructions fetch has processed -system.cpu.fetch.Branches 300386365 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174531965 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 428963032 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83531263 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119911343 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 109 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 283465873 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5375761 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 908345220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.641582 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.245010 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18362417 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 231 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 295110918 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2170236667 # Number of instructions fetch has processed +system.cpu.fetch.Branches 302333500 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 176138614 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 431684517 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 85621855 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 155290774 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 58 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 285908690 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5538082 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 950817611 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.537566 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.220819 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 479382246 52.78% 52.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23075019 2.54% 55.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38696357 4.26% 59.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47758356 5.26% 64.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40740735 4.49% 69.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46836926 5.16% 74.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39064245 4.30% 78.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18137906 2.00% 80.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174653430 19.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 519133170 54.60% 54.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23531871 2.47% 57.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38842821 4.09% 61.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47928811 5.04% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 41274787 4.34% 70.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 47187627 4.96% 75.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39143273 4.12% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18340446 1.93% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175434805 18.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 908345220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.327907 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.354928 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 321276302 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100437637 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403614016 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16012907 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 67004358 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46143588 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 709 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2345766913 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2404 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 67004358 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 342772787 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 44470406 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13938 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 396994343 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 57089388 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2288809868 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21597 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4587251 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 43867874 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2263371035 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10565210641 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10565207285 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3356 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706320010 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 557051025 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5363 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5361 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 133306732 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624412648 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 218802984 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85974356 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66146404 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2189209490 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1708 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2014638202 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4851094 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 461527844 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1075835396 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1528 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 908345220 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.217921 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.925838 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 950817611 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.315489 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.264671 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 327140938 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 132753088 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 402950990 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19241929 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 68730666 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46279846 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 704 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2359084469 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2481 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 68730666 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 349892865 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 63780880 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14141 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 397813217 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70585842 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2300380626 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 28739 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5556251 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 56445912 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2275326533 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10618275091 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10618272387 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2704 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319938 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 569006595 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5461 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5458 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 155601466 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 627528670 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 219567806 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 87006993 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68089228 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2199559403 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1526 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2020307102 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5002319 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 472139724 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1101721580 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1355 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 950817611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.124810 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.914497 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 244431658 26.91% 26.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 136114338 14.98% 41.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 157116427 17.30% 59.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 116129005 12.78% 71.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125782921 13.85% 85.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75959694 8.36% 94.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39392857 4.34% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10729861 1.18% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2688459 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 272456432 28.65% 28.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 148972541 15.67% 44.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161045064 16.94% 61.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 117808406 12.39% 73.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124487858 13.09% 86.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 74416152 7.83% 94.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38351621 4.03% 98.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10558999 1.11% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2720538 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 908345220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 950817611 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 792596 3.16% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4903 0.02% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19003801 75.87% 79.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5245876 20.94% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 866703 3.46% 3.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4868 0.02% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18978969 75.82% 79.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5181359 20.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1233307061 61.22% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 930228 0.05% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 49 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 28 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 10 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 586604414 29.12% 90.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193796407 9.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236552318 61.21% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 932322 0.05% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 41 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 588904292 29.15% 90.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193918099 9.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2014638202 # Type of FU issued -system.cpu.iq.rate 2.199214 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25047176 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012433 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4967519524 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2650923657 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1956580647 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 370 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2039685190 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 188 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63569960 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2020307102 # Type of FU issued +system.cpu.iq.rate 2.108217 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25031899 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012390 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5021465735 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2671886632 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1961215820 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 298 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 520 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2045338849 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 152 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63654285 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138485869 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 280074 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 188083 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 43955929 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 141601900 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 294123 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189203 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 44720760 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 515490 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1137177 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 67004358 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 19766452 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1127497 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2189219165 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5544678 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624412648 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 218802984 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1639 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 172089 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 43011 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 188083 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8607625 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10203792 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18811417 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1985083877 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 571977023 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29554325 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 68730666 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28026748 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1485770 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2199569564 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5556141 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 627528670 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 219567806 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1463 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 343326 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 56332 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189203 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8602483 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10215552 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18818035 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1990553449 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574287819 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29753653 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 7967 # number of nop insts executed -system.cpu.iew.exec_refs 762799722 # number of memory reference insts executed -system.cpu.iew.exec_branches 238022734 # Number of branches executed -system.cpu.iew.exec_stores 190822699 # Number of stores executed -system.cpu.iew.exec_rate 2.166952 # Inst execution rate -system.cpu.iew.wb_sent 1965575614 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1956580779 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296425776 # num instructions producing a value -system.cpu.iew.wb_consumers 2069436870 # num instructions consuming a value +system.cpu.iew.exec_nop 8635 # number of nop insts executed +system.cpu.iew.exec_refs 765252053 # number of memory reference insts executed +system.cpu.iew.exec_branches 238421113 # Number of branches executed +system.cpu.iew.exec_stores 190964234 # Number of stores executed +system.cpu.iew.exec_rate 2.077169 # Inst execution rate +system.cpu.iew.wb_sent 1970075771 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1961215932 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296581898 # num instructions producing a value +system.cpu.iew.wb_consumers 2068899277 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.135837 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626463 # average fanout of values written-back +system.cpu.iew.wb_rate 2.046555 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626701 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1544563091 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1723073903 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 466205393 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 180 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16072230 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 841340863 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.048009 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.762269 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1544563046 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1723073858 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 476570852 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 171 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16105557 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 882086946 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.953406 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.727739 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 352627350 41.91% 41.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193034897 22.94% 64.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73667996 8.76% 73.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35236864 4.19% 77.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18719576 2.22% 80.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30675778 3.65% 83.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19663987 2.34% 86.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10964014 1.30% 87.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106750401 12.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 391458685 44.38% 44.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 194911052 22.10% 66.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73858259 8.37% 74.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35176751 3.99% 78.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19156374 2.17% 81.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30712442 3.48% 84.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19230333 2.18% 86.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11318069 1.28% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106264981 12.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 841340863 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563091 # Number of instructions committed -system.cpu.commit.committedOps 1723073903 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 882086946 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563046 # Number of instructions committed +system.cpu.commit.committedOps 1723073858 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773834 # Number of memory references committed -system.cpu.commit.loads 485926779 # Number of loads committed +system.cpu.commit.refs 660773816 # Number of memory references committed +system.cpu.commit.loads 485926770 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462373 # Number of branches committed +system.cpu.commit.branches 213462364 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941881 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941845 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106750401 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106264981 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2923869159 # The number of ROB reads -system.cpu.rob.rob_writes 4445740607 # The number of ROB writes -system.cpu.timesIdled 753914 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7726751 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563073 # Number of Instructions Simulated -system.cpu.committedOps 1723073885 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563073 # Number of Instructions Simulated -system.cpu.cpi 0.593095 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.593095 # CPI: Total CPI of All Threads -system.cpu.ipc 1.686072 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.686072 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9944305109 # number of integer regfile reads -system.cpu.int_regfile_writes 1936656463 # number of integer regfile writes -system.cpu.fp_regfile_reads 139 # number of floating regfile reads -system.cpu.fp_regfile_writes 147 # number of floating regfile writes -system.cpu.misc_regfile_reads 2896410924 # number of misc regfile reads -system.cpu.misc_regfile_writes 144 # number of misc regfile writes -system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.tagsinuse 627.053723 # Cycle average of tags in use -system.cpu.icache.total_refs 283464725 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 785 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 361101.560510 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2975466076 # The number of ROB reads +system.cpu.rob.rob_writes 4468185114 # The number of ROB writes +system.cpu.timesIdled 802459 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7483602 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563028 # Number of Instructions Simulated +system.cpu.committedOps 1723073840 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563028 # Number of Instructions Simulated +system.cpu.cpi 0.620435 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.620435 # CPI: Total CPI of All Threads +system.cpu.ipc 1.611772 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.611772 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9971004084 # number of integer regfile reads +system.cpu.int_regfile_writes 1941069131 # number of integer regfile writes +system.cpu.fp_regfile_reads 114 # number of floating regfile reads +system.cpu.fp_regfile_writes 123 # number of floating regfile writes +system.cpu.misc_regfile_reads 2910834876 # number of misc regfile reads +system.cpu.misc_regfile_writes 126 # number of misc regfile writes +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.tagsinuse 634.471646 # Cycle average of tags in use +system.cpu.icache.total_refs 285907562 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 789 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 362366.998733 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 627.053723 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.306179 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.306179 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 283464725 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 283464725 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 283464725 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 283464725 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 283464725 # number of overall hits -system.cpu.icache.overall_hits::total 283464725 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1148 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1148 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1148 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1148 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1148 # number of overall misses -system.cpu.icache.overall_misses::total 1148 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38598000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38598000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38598000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38598000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38598000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38598000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 283465873 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 283465873 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 283465873 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 283465873 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 283465873 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 283465873 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 634.471646 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.309801 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.309801 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 285907562 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 285907562 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 285907562 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 285907562 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 285907562 # number of overall hits +system.cpu.icache.overall_hits::total 285907562 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1128 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1128 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1128 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1128 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1128 # number of overall misses +system.cpu.icache.overall_misses::total 1128 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 40115500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 40115500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 40115500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 40115500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 40115500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 40115500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 285908690 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 285908690 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 285908690 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 285908690 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 285908690 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 285908690 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33621.951220 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 33621.951220 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 33621.951220 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 33621.951220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 33621.951220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 33621.951220 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35563.386525 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35563.386525 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35563.386525 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35563.386525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35563.386525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35563.386525 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,309 +401,309 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 363 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 363 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 363 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 363 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 363 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 785 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 785 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 785 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28841500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28841500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28841500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28841500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34396.178344 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36554.499366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9618836 # number of replacements -system.cpu.dcache.tagsinuse 4087.631943 # Cycle average of tags in use -system.cpu.dcache.total_refs 660703184 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9622932 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.659239 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3346369000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.631943 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997957 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997957 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 493290864 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 493290864 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167412157 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167412157 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 92 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 92 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 71 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 71 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 660703021 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 660703021 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 660703021 # number of overall hits -system.cpu.dcache.overall_hits::total 660703021 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10330521 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10330521 # 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number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167394718 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167394718 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 84 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 84 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 62 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 62 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 661857915 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 661857915 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 661857915 # number of overall hits +system.cpu.dcache.overall_hits::total 661857915 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10787388 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10787388 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5191329 # 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number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 288076807837 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 288076807837 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 288076807837 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 288076807837 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 503621385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 503621385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 15978717 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15978717 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15978717 # number of overall misses +system.cpu.dcache.overall_misses::total 15978717 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 258680588500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 258680588500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 196204904993 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 196204904993 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 118500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 118500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 454885493493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 454885493493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 454885493493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 454885493493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 505250585 # 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number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020512 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020512 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029979 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029979 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.031579 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.031579 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022928 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.022928 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.022928 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.022928 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15800.194346 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15800.194346 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24131.276146 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24131.276146 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18580.312908 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18580.312908 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18580.312908 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18580.312908 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 200292336 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 119500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 73738 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2716.270254 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14937.500000 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 87 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 87 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 62 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 62 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 677836632 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 677836632 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 677836632 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 677836632 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021351 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021351 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030080 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.030080 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023573 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023573 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023573 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023573 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23979.909548 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23979.909548 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37794.735220 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37794.735220 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 39500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 39500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28468.211402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28468.211402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28468.211402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28468.211402 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2516165984 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 147500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 424894 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5921.867534 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16388.888889 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3473805 # number of writebacks -system.cpu.dcache.writebacks::total 3473805 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2601467 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2601467 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3280012 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 42766465749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 42766465749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 121751862249 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 121751862249 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 121751862249 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 121751862249 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015347 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015347 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 6356757 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6356757 # 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number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 4354 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 2976 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8490.009187 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7834.757392 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1124163 # number of writebacks -system.cpu.l2cache.writebacks::total 1124163 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1123984 # number of writebacks +system.cpu.l2cache.writebacks::total 1123984 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 755 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1612172 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1612927 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830934 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 830934 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 755 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2443106 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2443861 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 755 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2443106 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2443861 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50285384000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 50308930000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26141067500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26141067500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76426451500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 76449997500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76426451500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 76449997500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208586 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208662 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438747 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438747 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253884 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.253941 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253884 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.253941 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31186.754967 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31191.078868 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31191.076844 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31459.860230 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31459.860230 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31186.754967 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31282.495111 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31282.465533 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31186.754967 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31282.495111 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31282.465533 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 758 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611343 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1612101 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830788 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 830788 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 758 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2442131 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2442889 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 758 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2442131 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2442889 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25025500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 52778176000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52803201500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 29830819408 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 29830819408 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25025500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82608995408 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 82634020908 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25025500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82608995408 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 82634020908 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960710 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208507 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438655 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438655 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960710 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253808 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.253866 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960710 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253808 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.253866 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33015.171504 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32754.153523 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32754.276252 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35906.656581 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35906.656581 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33015.171504 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33826.602835 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33826.351057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33015.171504 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33826.602835 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33826.351057 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index e66f558e0..d5edd6037 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -166,7 +166,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -198,7 +198,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 4ec39cba0..2722378bf 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:25:17 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 16:44:36 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2408512388000 because target called exit() +Exiting @ tick 2409361491000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index c9d66243a..906e755f1 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.408512 # Number of seconds simulated -sim_ticks 2408512388000 # Number of ticks simulated -final_tick 2408512388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.409361 # Number of seconds simulated +sim_ticks 2409361491000 # Number of ticks simulated +final_tick 2409361491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1431405 # Simulator instruction rate (inst/s) -host_op_rate 1597462 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2240478292 # Simulator tick rate (ticks/s) -host_mem_usage 233776 # Number of bytes of host memory used -host_seconds 1075.00 # Real time elapsed on the host +host_inst_rate 1494553 # Simulator instruction rate (inst/s) +host_op_rate 1667935 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2340143235 # Simulator tick rate (ticks/s) +host_mem_usage 233700 # Number of bytes of host memory used +host_seconds 1029.58 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 2153435 # Nu system.physmem.num_reads::total 2154051 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1050331 # Number of write requests responded to by this memory system.physmem.num_writes::total 1050331 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 57221977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 57238345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16369 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16369 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27909835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27909835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27909835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16369 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 57221977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 85148181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 16363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 57201811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 57218174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16363 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16363 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27899999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27899999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27899999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 57201811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 85118173 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4817024776 # number of cpu cycles simulated +system.cpu.numCycles 4818722982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759601 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 660773815 # nu system.cpu.num_load_insts 485926769 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4817024776 # Number of busy cycles +system.cpu.num_busy_cycles 4818722982 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 7 # number of replacements -system.cpu.icache.tagsinuse 515.022606 # Cycle average of tags in use +system.cpu.icache.tagsinuse 515.026762 # Cycle average of tags in use system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 515.022606 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.251476 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.251476 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 515.026762 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.251478 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.251478 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34804000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34804000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34804000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34804000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34804000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34804000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34951000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34951000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34951000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34951000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34951000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34951000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54551.724138 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54551.724138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54551.724138 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54782.131661 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54782.131661 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54782.131661 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54782.131661 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54782.131661 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54782.131661 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32890000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32890000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32890000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32890000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32890000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32890000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33037000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33037000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33037000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33037000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33037000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33037000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51551.724138 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51551.724138 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51782.131661 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51782.131661 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51782.131661 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51782.131661 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51782.131661 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51782.131661 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9111140 # number of replacements -system.cpu.dcache.tagsinuse 4083.603265 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4083.605959 # Cycle average of tags in use system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25922973000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4083.603265 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996973 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996973 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 25924036000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4083.605959 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996974 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996974 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115236 # n system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 158470312000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 158470312000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 59587262000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 59587262000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 218057574000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 218057574000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 218057574000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 218057574000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 158944725000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 158944725000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59599499000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59599499000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 218544224000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 218544224000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 218544224000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 218544224000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21930.307786 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21930.307786 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31541.854031 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31541.854031 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23922.317974 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23922.317974 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23922.317974 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23922.317974 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21995.960608 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21995.960608 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31548.331550 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31548.331550 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23975.706608 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23975.706608 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23975.706608 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23975.706608 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136792051000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 136792051000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53919815000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53919815000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190711866000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 190711866000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190711866000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 190711866000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137266464000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 137266464000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53932052000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53932052000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191198516000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191198516000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191198516000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191198516000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18930.307786 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18930.307786 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28541.854031 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28541.854031 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20922.317974 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20922.317974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20922.317974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20922.317974 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18995.960608 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18995.960608 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28548.331550 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28548.331550 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20975.706608 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20975.706608 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20975.706608 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20975.706608 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2138446 # number of replacements -system.cpu.l2cache.tagsinuse 30628.680390 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30629.012311 # Cycle average of tags in use system.cpu.l2cache.total_refs 8443619 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2168151 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 3.894387 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 437045285000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14782.399882 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 15.716042 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15830.564466 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.451123 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000480 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.483110 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.934713 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 437178443000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14783.850246 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 15.711580 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15829.450485 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.451167 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000479 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.483076 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.934723 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 5861680 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5861702 # number of ReadReq hits diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index 643e6799d..f840aa9a4 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -169,7 +169,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -201,7 +201,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 5dc44ec4f..05d9e4afd 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:08:09 -gem5 started Jun 28 2012 23:47:42 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 14:08:03 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 5900695290000 because target called exit() +Exiting @ tick 5901048931000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index faa206e56..50b0e856f 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.900695 # Number of seconds simulated -sim_ticks 5900695290000 # Number of ticks simulated -final_tick 5900695290000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.901049 # Number of seconds simulated +sim_ticks 5901048931000 # Number of ticks simulated +final_tick 5901048931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1070782 # Simulator instruction rate (inst/s) -host_op_rate 1668375 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2100461088 # Simulator tick rate (ticks/s) -host_mem_usage 228516 # Number of bytes of host memory used -host_seconds 2809.24 # Real time elapsed on the host +host_inst_rate 821481 # Simulator instruction rate (inst/s) +host_op_rate 1279942 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1611526350 # Simulator tick rate (ticks/s) +host_mem_usage 228472 # Number of bytes of host memory used +host_seconds 3661.78 # Real time elapsed on the host sim_insts 3008081057 # Number of instructions simulated sim_ops 4686862651 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory @@ -24,18 +24,18 @@ system.physmem.num_reads::total 2173231 # Nu system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 7321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 23563932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 23571253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 23562520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 23569841 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7321 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7321 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11421342 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11421342 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11421342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 11420657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11420657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11420657 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 23563932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 34992595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 23562520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 34990498 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11801390580 # number of cpu cycles simulated +system.cpu.numCycles 11802097862 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081057 # Number of instructions committed @@ -54,16 +54,16 @@ system.cpu.num_mem_refs 1677713086 # nu system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_store_insts 438528337 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11801390580 # Number of busy cycles +system.cpu.num_busy_cycles 11802097862 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 555.745205 # Cycle average of tags in use +system.cpu.icache.tagsinuse 555.745883 # Cycle average of tags in use system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 555.745205 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 555.745883 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.271360 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.271360 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37800000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37800000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37800000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37800000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37800000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37800000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37868000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37868000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37868000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37868000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37868000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37868000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4013232927 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4013232927 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4013232927 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56100.740741 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56100.740741 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56100.740741 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56100.740741 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,32 +116,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675 system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35775000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35775000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35775000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35775000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35775000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35775000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35843000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 35843000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35843000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 35843000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35843000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 35843000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53100.740741 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53100.740741 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.tagsinuse 4084.618409 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4084.618075 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58862653000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4084.618409 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 58864243000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4084.618075 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997221 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997221 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1231961899 # number of ReadReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 159193930000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 159193930000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 59630900000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 59630900000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 218824830000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 218824830000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 218824830000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 218824830000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 159195313000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 159195313000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59631053000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59631053000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 218826366000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 218826366000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 218826366000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 218826366000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1239184749 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1239184749 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.320649 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.320649 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.628983 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.628983 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.232336 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24013.232336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.232336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24013.232336 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.512125 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.512125 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.709943 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.709943 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24013.400892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24013.400892 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525380000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525380000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961419000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961419000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486799000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191486799000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486799000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191486799000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137526763000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 137526763000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961572000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961572000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191488335000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191488335000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191488335000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191488335000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses @@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.320649 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.320649 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.628983 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.628983 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.232336 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.232336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.232336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.232336 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.512125 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.512125 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.709943 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.709943 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2158210 # number of replacements -system.cpu.l2cache.tagsinuse 30851.506102 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30851.471232 # Cycle average of tags in use system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1317336331000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14661.525978 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 21.582601 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16168.397523 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.447434 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 1317386171000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14661.795010 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 21.581563 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16168.094659 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.447442 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.000659 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.493420 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.941513 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.493411 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.941512 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 5840135 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5840135 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3375759 # number of Writeback hits |