diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
| commit | 4bc7dfb697bd779b12f1fd95fbe72144ae134055 (patch) | |
| tree | 532cea8e118ac27336792282c7023bb1b2d01be4 /tests/long/se/60.bzip2 | |
| parent | cea1d14a937f27fa49423bd01eb900e578993a43 (diff) | |
| download | gem5-4bc7dfb697bd779b12f1fd95fbe72144ae134055.tar.xz | |
stats: Update MinorCPU regressions after accounting fix
Diffstat (limited to 'tests/long/se/60.bzip2')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt | 1036 | ||||
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt | 1031 |
2 files changed, 1035 insertions, 1032 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 520a2b090..959bae132 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.211624 # Number of seconds simulated -sim_ticks 1211624479500 # Number of ticks simulated -final_tick 1211624479500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.211096 # Number of seconds simulated +sim_ticks 1211096219500 # Number of ticks simulated +final_tick 1211096219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 333436 # Simulator instruction rate (inst/s) -host_op_rate 333436 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 221202175 # Simulator tick rate (ticks/s) -host_mem_usage 295444 # Number of bytes of host memory used -host_seconds 5477.45 # Real time elapsed on the host +host_inst_rate 325701 # Simulator instruction rate (inst/s) +host_op_rate 325701 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215976885 # Simulator tick rate (ticks/s) +host_mem_usage 296636 # Number of bytes of host memory used +host_seconds 5607.53 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125444544 # Number of bytes read from this memory -system.physmem.bytes_read::total 125505792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65167616 # Number of bytes written to this memory -system.physmem.bytes_written::total 65167616 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 957 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960071 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961028 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018244 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018244 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 50550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 103534178 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 103584728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 50550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 50550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 53785325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 53785325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 53785325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 50550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 103534178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 157370053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961028 # Number of read requests accepted -system.physmem.writeReqs 1018244 # Number of write requests accepted -system.physmem.readBursts 1961028 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1018244 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125424064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 81728 # Total number of bytes read from write queue -system.physmem.bytesWritten 65166336 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125505792 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65167616 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1277 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125445568 # Number of bytes read from this memory +system.physmem.bytes_read::total 125506880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65168832 # Number of bytes written to this memory +system.physmem.bytes_written::total 65168832 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960087 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961045 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018263 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018263 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 50625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 103580183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103630808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 50625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 50625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 53809789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 53809789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 53809789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 50625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 103580183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 157440597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961045 # Number of read requests accepted +system.physmem.writeReqs 1018263 # Number of write requests accepted +system.physmem.readBursts 1961045 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018263 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125425280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81600 # Total number of bytes read from write queue +system.physmem.bytesWritten 65167232 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125506880 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65168832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1275 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118746 # Per bank write bursts -system.physmem.perBankRdBursts::1 114093 # Per bank write bursts -system.physmem.perBankRdBursts::2 116238 # Per bank write bursts -system.physmem.perBankRdBursts::3 117765 # Per bank write bursts -system.physmem.perBankRdBursts::4 117832 # Per bank write bursts -system.physmem.perBankRdBursts::5 117522 # Per bank write bursts -system.physmem.perBankRdBursts::6 119888 # Per bank write bursts -system.physmem.perBankRdBursts::7 124523 # Per bank write bursts +system.physmem.perBankRdBursts::0 118758 # Per bank write bursts +system.physmem.perBankRdBursts::1 114090 # Per bank write bursts +system.physmem.perBankRdBursts::2 116233 # Per bank write bursts +system.physmem.perBankRdBursts::3 117775 # Per bank write bursts +system.physmem.perBankRdBursts::4 117826 # Per bank write bursts +system.physmem.perBankRdBursts::5 117520 # Per bank write bursts +system.physmem.perBankRdBursts::6 119879 # Per bank write bursts +system.physmem.perBankRdBursts::7 124540 # Per bank write bursts system.physmem.perBankRdBursts::8 126979 # Per bank write bursts -system.physmem.perBankRdBursts::9 130092 # Per bank write bursts -system.physmem.perBankRdBursts::10 128645 # Per bank write bursts -system.physmem.perBankRdBursts::11 130343 # Per bank write bursts -system.physmem.perBankRdBursts::12 126054 # Per bank write bursts -system.physmem.perBankRdBursts::13 125251 # Per bank write bursts -system.physmem.perBankRdBursts::14 122593 # Per bank write bursts -system.physmem.perBankRdBursts::15 123187 # Per bank write bursts -system.physmem.perBankWrBursts::0 61219 # Per bank write bursts -system.physmem.perBankWrBursts::1 61484 # Per bank write bursts -system.physmem.perBankWrBursts::2 60571 # Per bank write bursts -system.physmem.perBankWrBursts::3 61239 # Per bank write bursts -system.physmem.perBankWrBursts::4 61659 # Per bank write bursts +system.physmem.perBankRdBursts::9 130098 # Per bank write bursts +system.physmem.perBankRdBursts::10 128644 # Per bank write bursts +system.physmem.perBankRdBursts::11 130342 # Per bank write bursts +system.physmem.perBankRdBursts::12 126070 # Per bank write bursts +system.physmem.perBankRdBursts::13 125249 # Per bank write bursts +system.physmem.perBankRdBursts::14 122589 # Per bank write bursts +system.physmem.perBankRdBursts::15 123178 # Per bank write bursts +system.physmem.perBankWrBursts::0 61223 # Per bank write bursts +system.physmem.perBankWrBursts::1 61482 # Per bank write bursts +system.physmem.perBankWrBursts::2 60569 # Per bank write bursts +system.physmem.perBankWrBursts::3 61241 # Per bank write bursts +system.physmem.perBankWrBursts::4 61665 # Per bank write bursts system.physmem.perBankWrBursts::5 63100 # Per bank write bursts -system.physmem.perBankWrBursts::6 64152 # Per bank write bursts -system.physmem.perBankWrBursts::7 65616 # Per bank write bursts -system.physmem.perBankWrBursts::8 65335 # Per bank write bursts -system.physmem.perBankWrBursts::9 65774 # Per bank write bursts -system.physmem.perBankWrBursts::10 65298 # Per bank write bursts -system.physmem.perBankWrBursts::11 65641 # Per bank write bursts -system.physmem.perBankWrBursts::12 64170 # Per bank write bursts -system.physmem.perBankWrBursts::13 64210 # Per bank write bursts -system.physmem.perBankWrBursts::14 64569 # Per bank write bursts -system.physmem.perBankWrBursts::15 64187 # Per bank write bursts +system.physmem.perBankWrBursts::6 64149 # Per bank write bursts +system.physmem.perBankWrBursts::7 65619 # Per bank write bursts +system.physmem.perBankWrBursts::8 65334 # Per bank write bursts +system.physmem.perBankWrBursts::9 65779 # Per bank write bursts +system.physmem.perBankWrBursts::10 65299 # Per bank write bursts +system.physmem.perBankWrBursts::11 65645 # Per bank write bursts +system.physmem.perBankWrBursts::12 64166 # Per bank write bursts +system.physmem.perBankWrBursts::13 64211 # Per bank write bursts +system.physmem.perBankWrBursts::14 64570 # Per bank write bursts +system.physmem.perBankWrBursts::15 64186 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1211624362000 # Total gap between requests +system.physmem.totGap 1211096102000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961028 # Read request sizes (log2) +system.physmem.readPktSize::6 1961045 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018244 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1838105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121629 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1018263 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1837965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121788 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,30 +144,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 59979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 59990 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 59955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 59970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 59992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -193,130 +193,129 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1839318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.618163 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.033976 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.636069 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1460921 79.43% 79.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 261839 14.24% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49211 2.68% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20654 1.12% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12987 0.71% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7330 0.40% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5324 0.29% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4553 0.25% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16499 0.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1839318 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59419 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.981269 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 162.030420 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59379 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1839625 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.602019 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.031630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 129.543213 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1461173 79.43% 79.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 261967 14.24% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48998 2.66% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20657 1.12% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13124 0.71% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7476 0.41% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5272 0.29% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4494 0.24% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16464 0.89% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1839625 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59444 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.966456 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 164.214090 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59406 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 8 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59419 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59419 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.136337 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.100269 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.116106 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27590 46.43% 46.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1250 2.10% 48.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26098 43.92% 92.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3967 6.68% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 431 0.73% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 63 0.11% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 13 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59419 # Writes before turning the bus around for reads -system.physmem.totQLat 36831870500 # Total ticks spent queuing -system.physmem.totMemAccLat 73577201750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798755000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18794.16 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59444 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59444 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.129365 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.093444 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.113658 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27743 46.67% 46.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1259 2.12% 48.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26068 43.85% 92.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3874 6.52% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 419 0.70% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 52 0.09% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 24 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59444 # Writes before turning the bus around for reads +system.physmem.totQLat 36839321750 # Total ticks spent queuing +system.physmem.totMemAccLat 73585009250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798850000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18797.78 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37544.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 103.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 53.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 103.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 53.79 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37547.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 103.56 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 53.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 103.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 53.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing -system.physmem.readRowHits 725319 # Number of row buffer hits during reads -system.physmem.writeRowHits 413326 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.96 # Average write queue length when enqueuing +system.physmem.readRowHits 725244 # Number of row buffer hits during reads +system.physmem.writeRowHits 413130 # Number of row buffer hits during writes system.physmem.readRowHitRate 37.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.59 # Row buffer hit rate for writes -system.physmem.avgGap 406684.71 # Average gap between requests -system.physmem.pageHitRate 38.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6747405840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3681620250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7383487800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3233733840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 79137021600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 416124660195 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 361949541750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 878257471275 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.862968 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 599359370250 # Time in different power states -system.physmem_0.memoryStateTime::REF 40458600000 # Time in different power states +system.physmem.writeRowHitRate 40.57 # Row buffer hit rate for writes +system.physmem.avgGap 406502.48 # Average gap between requests +system.physmem.pageHitRate 38.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6747186600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3681500625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7383597000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3233831040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 79102439520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 416789244855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361048893750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 877986693390 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.956282 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 597858043000 # Time in different power states +system.physmem_0.memoryStateTime::REF 40440920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 571802499750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 572793401000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7157785320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3905537625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7902000600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3364254000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 79137021600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 427714080030 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 351783384000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 880964063175 # Total energy per rank (pJ) -system.physmem_1.averagePower 727.096833 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 582370760250 # Time in different power states -system.physmem_1.memoryStateTime::REF 40458600000 # Time in different power states +system.physmem_1.actEnergy 7160348160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3906936000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7901891400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3364351200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 79102439520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 428401624860 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 350862595500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 880700186640 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.196822 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 580834507250 # Time in different power states +system.physmem_1.memoryStateTime::REF 40440920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 588789276000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 589813744000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 246245862 # Number of BP lookups -system.cpu.branchPred.condPredicted 186459693 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15680292 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 167860438 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165233261 # Number of BTB hits +system.cpu.branchPred.lookups 246195404 # Number of BP lookups +system.cpu.branchPred.condPredicted 186411563 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15682149 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167682775 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165241760 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.434904 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18428492 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104737 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.544266 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18427120 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104306 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452534136 # DTB read hits -system.cpu.dtb.read_misses 4979812 # DTB read misses +system.cpu.dtb.read_hits 452923392 # DTB read hits +system.cpu.dtb.read_misses 4979932 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457513948 # DTB read accesses -system.cpu.dtb.write_hits 161377662 # DTB write hits -system.cpu.dtb.write_misses 1710258 # DTB write misses +system.cpu.dtb.read_accesses 457903324 # DTB read accesses +system.cpu.dtb.write_hits 161377581 # DTB write hits +system.cpu.dtb.write_misses 1710142 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163087920 # DTB write accesses -system.cpu.dtb.data_hits 613911798 # DTB hits -system.cpu.dtb.data_misses 6690070 # DTB misses +system.cpu.dtb.write_accesses 163087723 # DTB write accesses +system.cpu.dtb.data_hits 614300973 # DTB hits +system.cpu.dtb.data_misses 6690074 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620601868 # DTB accesses -system.cpu.itb.fetch_hits 598519306 # ITB hits +system.cpu.dtb.data_accesses 620991047 # DTB accesses +system.cpu.itb.fetch_hits 598257344 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 598519325 # ITB accesses +system.cpu.itb.fetch_accesses 598257363 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -330,82 +329,82 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2423248959 # number of cpu cycles simulated +system.cpu.numCycles 2422192439 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 52407440 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 52052944 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.326805 # CPI: cycles per instruction -system.cpu.ipc 0.753690 # IPC: instructions per cycle -system.cpu.tickCycles 2077336659 # Number of cycles that the object actually ticked -system.cpu.idleCycles 345912300 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9122013 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.749026 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601822613 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126109 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.945148 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16826930000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.749026 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996277 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996277 # Average percentage of cache occupancy +system.cpu.cpi 1.326227 # CPI: cycles per instruction +system.cpu.ipc 0.754019 # IPC: instructions per cycle +system.cpu.tickCycles 2076133627 # Number of cycles that the object actually ticked +system.cpu.idleCycles 346058812 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9121955 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.744039 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601604629 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126051 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.921682 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16824784000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.744039 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996275 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996275 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1544 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2417 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231838683 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231838683 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 443338219 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443338219 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158484394 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158484394 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 601822613 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601822613 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 601822613 # number of overall hits -system.cpu.dcache.overall_hits::total 601822613 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7289566 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289566 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2244108 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2244108 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9533674 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9533674 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9533674 # number of overall misses -system.cpu.dcache.overall_misses::total 9533674 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 186798880750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 186798880750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108940864000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108940864000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 295739744750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 295739744750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 295739744750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 295739744750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 450627785 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450627785 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231402079 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231402079 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 443119981 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443119981 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158484648 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158484648 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 601604629 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601604629 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 601604629 # number of overall hits +system.cpu.dcache.overall_hits::total 601604629 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7289531 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289531 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2243854 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2243854 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9533385 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9533385 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9533385 # number of overall misses +system.cpu.dcache.overall_misses::total 9533385 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 186817706000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 186817706000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108924057250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108924057250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 295741763250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 295741763250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 295741763250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 295741763250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 450409512 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450409512 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 611356287 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611356287 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 611356287 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611356287 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016176 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016176 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013962 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013962 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015594 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015594 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015594 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015594 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.514708 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.514708 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48545.285699 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48545.285699 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31020.543051 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31020.543051 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31020.543051 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31020.543051 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 611138014 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611138014 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 611138014 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611138014 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016184 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016184 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013961 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013961 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015599 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015599 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015599 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015599 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25628.220252 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25628.220252 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48543.290807 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48543.290807 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31021.695153 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31021.695153 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31021.695153 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31021.695153 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -414,100 +413,101 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700625 # number of writebacks -system.cpu.dcache.writebacks::total 3700625 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50791 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50791 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 356774 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 356774 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 407565 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 407565 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 407565 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 407565 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238775 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238775 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887334 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887334 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126109 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126109 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126109 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126109 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 174334776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 174334776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82397045250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 82397045250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 256731821250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 256731821250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 256731821250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 256731821250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016064 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016064 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 3700563 # number of writebacks +system.cpu.dcache.writebacks::total 3700563 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50798 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50798 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 356536 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 356536 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 407334 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 407334 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 407334 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 407334 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238733 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238733 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887318 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887318 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126051 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126051 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126051 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126051 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 174355280750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 174355280750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82395435500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 82395435500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 256750716250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 256750716250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 256750716250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 256750716250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016071 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016071 # 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average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28131.575160 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28131.575160 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28131.575160 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28131.575160 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014933 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014933 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014933 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014933 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24086.436224 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24086.436224 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43657.420477 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43657.420477 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28133.824395 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28133.824395 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28133.824395 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28133.824395 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 751.304686 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 598518349 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 957 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 625411.022989 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 751.308351 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 598256386 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 624484.745303 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 751.304686 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.366848 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.366848 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 751.308351 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.366850 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.366850 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1197039569 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1197039569 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 598518349 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 598518349 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 598518349 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 598518349 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 598518349 # number of overall hits -system.cpu.icache.overall_hits::total 598518349 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses -system.cpu.icache.overall_misses::total 957 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 77501250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 77501250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 77501250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 77501250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 77501250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 77501250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 598519306 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 598519306 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 598519306 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 598519306 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 598519306 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 598519306 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1196515646 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1196515646 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 598256386 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 598256386 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 598256386 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 598256386 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 598256386 # number of overall hits +system.cpu.icache.overall_hits::total 598256386 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses +system.cpu.icache.overall_misses::total 958 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 76776500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 76776500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 76776500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 76776500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 76776500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 76776500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 598257344 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 598257344 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 598257344 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 598257344 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 598257344 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 598257344 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80983.542320 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80983.542320 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80983.542320 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80983.542320 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80983.542320 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80983.542320 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80142.484342 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80142.484342 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80142.484342 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80142.484342 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80142.484342 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80142.484342 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -516,120 +516,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 957 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 957 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 957 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 957 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75665250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75665250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75665250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75665250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75665250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75665250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74938500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 74938500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74938500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 74938500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74938500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 74938500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79065.047022 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79065.047022 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58963288250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58963288250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61981000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147528849500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 147590830500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61981000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147528849500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 147590830500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163097 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163208 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412989 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412989 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163101 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163212 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412988 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412988 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214776 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214779 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214862 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214776 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214859 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65538.923720 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74998.570670 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74990.908995 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75649.873372 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75649.873372 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65538.923720 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75257.569751 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75252.826961 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65538.923720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75257.569751 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75252.826961 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214779 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214862 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64698.329854 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75014.366052 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75006.002212 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75648.367929 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75648.367929 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64698.329854 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75266.480263 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75261.317563 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64698.329854 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75266.480263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75261.317563 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7239732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887334 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952843 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954757 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820910976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820972224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7239691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700563 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887318 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887318 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952665 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954581 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820903296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820964608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12827691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12827572 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12827691 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12827572 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12827691 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10114470500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12827572 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10114349000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1635750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1637500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14015207750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14015266250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1181580 # Transaction distribution -system.membus.trans_dist::ReadResp 1181580 # Transaction distribution -system.membus.trans_dist::Writeback 1018244 # Transaction distribution -system.membus.trans_dist::ReadExReq 779448 # Transaction distribution -system.membus.trans_dist::ReadExResp 779448 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940300 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940300 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190673408 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1181606 # Transaction distribution +system.membus.trans_dist::ReadResp 1181606 # Transaction distribution +system.membus.trans_dist::Writeback 1018263 # Transaction distribution +system.membus.trans_dist::ReadExReq 779439 # Transaction distribution +system.membus.trans_dist::ReadExResp 779439 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940353 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940353 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190675712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190675712 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2979272 # Request fanout histogram +system.membus.snoop_fanout::samples 2979308 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2979272 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2979308 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2979272 # Request fanout histogram -system.membus.reqLayer0.occupancy 7744840000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2979308 # Request fanout histogram +system.membus.reqLayer0.occupancy 7754390500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 10727612750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10727987500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index fd03f6311..fd798006f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.121265 # Number of seconds simulated -sim_ticks 1121265462500 # Number of ticks simulated -final_tick 1121265462500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.119236 # Number of seconds simulated +sim_ticks 1119236001500 # Number of ticks simulated +final_tick 1119236001500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 238084 # Simulator instruction rate (inst/s) -host_op_rate 256500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 172835636 # Simulator tick rate (ticks/s) -host_mem_usage 314372 # Number of bytes of host memory used -host_seconds 6487.47 # Real time elapsed on the host +host_inst_rate 240571 # Simulator instruction rate (inst/s) +host_op_rate 259178 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174324523 # Simulator tick rate (ticks/s) +host_mem_usage 314620 # Number of bytes of host memory used +host_seconds 6420.42 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 50816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 131531264 # Number of bytes read from this memory -system.physmem.bytes_read::total 131582080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66976320 # Number of bytes written to this memory -system.physmem.bytes_written::total 66976320 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 794 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2055176 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2055970 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046505 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046505 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 45320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117306087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 117351407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45320 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45320 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 59732795 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 59732795 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 59732795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 45320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117306087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 177084202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2055970 # Number of read requests accepted -system.physmem.writeReqs 1046505 # Number of write requests accepted -system.physmem.readBursts 2055970 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046505 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131497344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 84736 # Total number of bytes read from write queue -system.physmem.bytesWritten 66974720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131582080 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66976320 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1324 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 50432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 131457472 # Number of bytes read from this memory +system.physmem.bytes_read::total 131507904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66959680 # Number of bytes written to this memory +system.physmem.bytes_written::total 66959680 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 788 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2054023 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2054811 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046245 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046245 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 45059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117452862 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117497922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45059 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45059 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 59826239 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 59826239 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 59826239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117452862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177324160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2054811 # Number of read requests accepted +system.physmem.writeReqs 1046245 # Number of write requests accepted +system.physmem.readBursts 2054811 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046245 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131422592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 85312 # Total number of bytes read from write queue +system.physmem.bytesWritten 66958080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131507904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66959680 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1333 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 128088 # Per bank write bursts -system.physmem.perBankRdBursts::1 125235 # Per bank write bursts -system.physmem.perBankRdBursts::2 122283 # Per bank write bursts -system.physmem.perBankRdBursts::3 124122 # Per bank write bursts -system.physmem.perBankRdBursts::4 123237 # Per bank write bursts -system.physmem.perBankRdBursts::5 123404 # Per bank write bursts -system.physmem.perBankRdBursts::6 123754 # Per bank write bursts -system.physmem.perBankRdBursts::7 124260 # Per bank write bursts -system.physmem.perBankRdBursts::8 132002 # Per bank write bursts -system.physmem.perBankRdBursts::9 134077 # Per bank write bursts -system.physmem.perBankRdBursts::10 132455 # Per bank write bursts -system.physmem.perBankRdBursts::11 133729 # Per bank write bursts -system.physmem.perBankRdBursts::12 133726 # Per bank write bursts -system.physmem.perBankRdBursts::13 133924 # Per bank write bursts -system.physmem.perBankRdBursts::14 129890 # Per bank write bursts -system.physmem.perBankRdBursts::15 130460 # Per bank write bursts -system.physmem.perBankWrBursts::0 65849 # Per bank write bursts -system.physmem.perBankWrBursts::1 64148 # Per bank write bursts -system.physmem.perBankWrBursts::2 62390 # Per bank write bursts -system.physmem.perBankWrBursts::3 62849 # Per bank write bursts -system.physmem.perBankWrBursts::4 62818 # Per bank write bursts -system.physmem.perBankWrBursts::5 62997 # Per bank write bursts -system.physmem.perBankWrBursts::6 64238 # Per bank write bursts -system.physmem.perBankWrBursts::7 65252 # Per bank write bursts -system.physmem.perBankWrBursts::8 67098 # Per bank write bursts -system.physmem.perBankWrBursts::9 67598 # Per bank write bursts -system.physmem.perBankWrBursts::10 67270 # Per bank write bursts -system.physmem.perBankWrBursts::11 67670 # Per bank write bursts -system.physmem.perBankWrBursts::12 67009 # Per bank write bursts -system.physmem.perBankWrBursts::13 67470 # Per bank write bursts -system.physmem.perBankWrBursts::14 66159 # Per bank write bursts -system.physmem.perBankWrBursts::15 65665 # Per bank write bursts +system.physmem.perBankRdBursts::0 127863 # Per bank write bursts +system.physmem.perBankRdBursts::1 125217 # Per bank write bursts +system.physmem.perBankRdBursts::2 122173 # Per bank write bursts +system.physmem.perBankRdBursts::3 124176 # Per bank write bursts +system.physmem.perBankRdBursts::4 123271 # Per bank write bursts +system.physmem.perBankRdBursts::5 123280 # Per bank write bursts +system.physmem.perBankRdBursts::6 123668 # Per bank write bursts +system.physmem.perBankRdBursts::7 124134 # Per bank write bursts +system.physmem.perBankRdBursts::8 131770 # Per bank write bursts +system.physmem.perBankRdBursts::9 134069 # Per bank write bursts +system.physmem.perBankRdBursts::10 132400 # Per bank write bursts +system.physmem.perBankRdBursts::11 133571 # Per bank write bursts +system.physmem.perBankRdBursts::12 133882 # Per bank write bursts +system.physmem.perBankRdBursts::13 133894 # Per bank write bursts +system.physmem.perBankRdBursts::14 129882 # Per bank write bursts +system.physmem.perBankRdBursts::15 130228 # Per bank write bursts +system.physmem.perBankWrBursts::0 65769 # Per bank write bursts +system.physmem.perBankWrBursts::1 64155 # Per bank write bursts +system.physmem.perBankWrBursts::2 62373 # Per bank write bursts +system.physmem.perBankWrBursts::3 62858 # Per bank write bursts +system.physmem.perBankWrBursts::4 62829 # Per bank write bursts +system.physmem.perBankWrBursts::5 62965 # Per bank write bursts +system.physmem.perBankWrBursts::6 64230 # Per bank write bursts +system.physmem.perBankWrBursts::7 65234 # Per bank write bursts +system.physmem.perBankWrBursts::8 67002 # Per bank write bursts +system.physmem.perBankWrBursts::9 67576 # Per bank write bursts +system.physmem.perBankWrBursts::10 67286 # Per bank write bursts +system.physmem.perBankWrBursts::11 67640 # Per bank write bursts +system.physmem.perBankWrBursts::12 67022 # Per bank write bursts +system.physmem.perBankWrBursts::13 67467 # Per bank write bursts +system.physmem.perBankWrBursts::14 66208 # Per bank write bursts +system.physmem.perBankWrBursts::15 65606 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1121265368000 # Total gap between requests +system.physmem.totGap 1119235907000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2055970 # Read request sizes (log2) +system.physmem.readPktSize::6 2054811 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046505 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1926795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046245 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1925781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127679 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61214 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 60967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,105 +193,108 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1920747 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.329698 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.701744 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 124.647307 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1495902 77.88% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305625 15.91% 93.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52698 2.74% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21305 1.11% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13173 0.69% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7131 0.37% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5450 0.28% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5094 0.27% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14369 0.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1920747 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60965 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.654375 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.846066 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60925 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 15 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1918760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.389572 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.724365 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 124.748032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1494097 77.87% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305195 15.91% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52958 2.76% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21140 1.10% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13031 0.68% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7420 0.39% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5500 0.29% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5087 0.27% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14332 0.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1918760 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60963 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.636353 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.963797 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60925 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60965 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.165259 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.130353 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.096188 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27136 44.51% 44.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1324 2.17% 46.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28285 46.40% 93.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3807 6.24% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 355 0.58% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 47 0.08% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60963 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60963 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.161557 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.126473 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.099462 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27343 44.85% 44.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1128 1.85% 46.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28298 46.42% 93.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3779 6.20% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 354 0.58% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 49 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60965 # Writes before turning the bus around for reads -system.physmem.totQLat 38466601000 # Total ticks spent queuing -system.physmem.totMemAccLat 76991213500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10273230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18721.77 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60963 # Writes before turning the bus around for reads +system.physmem.totQLat 38392697500 # Total ticks spent queuing +system.physmem.totMemAccLat 76895410000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10267390000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18696.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37471.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 117.28 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 59.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 117.35 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 59.73 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37446.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 117.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 59.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 117.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 59.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.38 # Data bus utilization in percentage system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.95 # Average write queue length when enqueuing -system.physmem.readRowHits 774547 # Number of row buffer hits during reads -system.physmem.writeRowHits 405822 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.78 # Row buffer hit rate for writes -system.physmem.avgGap 361409.96 # Average gap between requests -system.physmem.pageHitRate 38.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7084922040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3865780875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7755875400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3308305680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 73235182800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 422966689965 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 301732094250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 819948851010 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.275041 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 499232206000 # Time in different power states -system.physmem_0.memoryStateTime::REF 37441300000 # Time in different power states +system.physmem.avgWrQLen 25.22 # Average write queue length when enqueuing +system.physmem.readRowHits 774740 # Number of row buffer hits during reads +system.physmem.writeRowHits 406194 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.82 # Row buffer hit rate for writes +system.physmem.avgGap 360920.90 # Average gap between requests +system.physmem.pageHitRate 38.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7079751000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3862959375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7751413800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3307476240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 73102957200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 422173404720 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301213311750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 818491274085 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.295434 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 498371051250 # Time in different power states +system.physmem_0.memoryStateTime::REF 37373700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 584588629000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 583490028750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7435910160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4057292250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8269996800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3472884720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 73235182800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 431711081055 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 294061575750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 822243923535 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.321912 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 486423236500 # Time in different power states -system.physmem_1.memoryStateTime::REF 37441300000 # Time in different power states +system.physmem_1.actEnergy 7426074600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4051925625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8265605400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3472029360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 73102957200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 430406880300 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 293990964750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 820716437235 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.283545 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 486308465000 # Time in different power states +system.physmem_1.memoryStateTime::REF 37373700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 597397500000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 595553667000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 240144458 # Number of BP lookups -system.cpu.branchPred.condPredicted 186748856 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14594265 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132793559 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122289853 # Number of BTB hits +system.cpu.branchPred.lookups 239764270 # Number of BP lookups +system.cpu.branchPred.condPredicted 186476421 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14595676 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 130796554 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122091083 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.090199 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15658823 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 93.344266 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15654091 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -411,68 +414,68 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2242530925 # number of cpu cycles simulated +system.cpu.numCycles 2238472003 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 40067412 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41626992 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.451887 # CPI: cycles per instruction -system.cpu.ipc 0.688759 # IPC: instructions per cycle -system.cpu.tickCycles 1838970368 # Number of cycles that the object actually ticked -system.cpu.idleCycles 403560557 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9223420 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.640559 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624065637 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9227516 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.630946 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9814734000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.640559 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997471 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997471 # Average percentage of cache occupancy +system.cpu.cpi 1.449259 # CPI: cycles per instruction +system.cpu.ipc 0.690008 # IPC: instructions per cycle +system.cpu.tickCycles 1834950604 # Number of cycles that the object actually ticked +system.cpu.idleCycles 403521399 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9221835 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.627405 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624240644 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9225931 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.661534 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9809256250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.627405 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997468 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997468 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1219 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 244 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1227 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276541490 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276541490 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453733959 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453733959 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331555 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331555 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276887063 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276887063 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453909121 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453909121 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331400 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331400 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624065514 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624065514 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624065515 # number of overall hits -system.cpu.dcache.overall_hits::total 624065515 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7336856 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7336856 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254492 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254492 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624240521 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624240521 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624240522 # number of overall hits +system.cpu.dcache.overall_hits::total 624240522 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7335273 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7335273 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254647 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9591348 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9591348 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9591350 # number of overall misses -system.cpu.dcache.overall_misses::total 9591350 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 192473949996 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 192473949996 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109728776250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109728776250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 302202726246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 302202726246 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 302202726246 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 302202726246 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461070815 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461070815 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9589920 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9589920 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9589922 # number of overall misses +system.cpu.dcache.overall_misses::total 9589922 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 192354012246 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 192354012246 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109627439500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109627439500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 301981451746 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 301981451746 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 301981451746 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 301981451746 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461244394 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461244394 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -481,28 +484,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633656862 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633656862 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633656865 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633656865 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013063 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013063 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 633830441 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633830441 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633830444 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633830444 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015903 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015903 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013064 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013064 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015137 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015137 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015137 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015137 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26233.845941 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26233.845941 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48671.175702 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48671.175702 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31507.847098 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31507.847098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31507.840528 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31507.840528 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26223.156554 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26223.156554 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48622.883981 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48622.883981 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31489.465162 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31489.465162 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31489.458595 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31489.458595 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,109 +514,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700612 # number of writebacks -system.cpu.dcache.writebacks::total 3700612 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 212 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 212 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363621 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 363621 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 363833 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 363833 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 363833 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 363833 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336644 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7336644 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890871 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890871 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3700642 # number of writebacks +system.cpu.dcache.writebacks::total 3700642 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363775 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 363775 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 363990 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 363990 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 363990 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 363990 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7335058 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7335058 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890872 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890872 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9227515 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9227515 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9227516 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9227516 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181052332504 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 181052332504 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83984263000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83984263000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9225930 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9225930 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9225931 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9225931 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180934230004 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 180934230004 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83925664500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83925664500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 73750 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 73750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265036595504 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 265036595504 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265036669254 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 265036669254 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015912 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015912 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264859894504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 264859894504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264859968254 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 264859968254 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015903 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015903 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24677.813521 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24677.813521 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44415.649190 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44415.649190 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014556 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014556 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014556 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014556 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24667.048305 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24667.048305 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44384.635502 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44384.635502 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73750 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73750 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28722.423697 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28722.423697 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28722.428577 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28722.428577 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28708.205515 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28708.205515 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28708.210397 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28708.210397 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 35 # number of replacements -system.cpu.icache.tags.tagsinuse 662.614734 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466141021 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 828 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 562972.247585 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 29 # number of replacements +system.cpu.icache.tags.tagsinuse 662.446494 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 465464024 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 821 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 566947.654080 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 662.614734 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.323542 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.323542 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 793 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 662.446494 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.323460 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.323460 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 792 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76737.209501 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76737.209501 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76737.209501 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -622,123 +625,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 828 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 828 # 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number of replacements -system.cpu.l2cache.tags.tagsinuse 31261.991003 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8984313 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2053040 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.376102 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 59841737750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14971.940870 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.910061 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16263.140072 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.456907 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000821 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.496312 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87756.490119 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76398.288973 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87760.853071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87756.490119 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -747,8 +750,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1046505 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60466755500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60466755500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51069250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154451794250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 154502863500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51069250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154451794250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 154502863500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958937 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171068 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74884.658272 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74877.978243 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75572.864174 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75572.864174 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64318.954660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75152.587540 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75148.403673 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64318.954660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75152.587540 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75148.403673 # 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number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 50399250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93887019000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 93937418250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60414024000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60414024000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50399250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154301043000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 154351442250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50399250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154301043000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 154351442250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.170969 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171058 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222636 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222701 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222636 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222701 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63958.439086 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74865.851986 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74859.002572 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75521.966916 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75521.966916 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63958.439086 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75121.380335 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75117.099456 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63958.439086 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75121.380335 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75117.099456 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7337473 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7337473 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890871 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890871 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1656 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22155644 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22157300 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827400192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827453184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7335880 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7335880 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700642 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890872 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1642 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22152504 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22154146 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827300672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827353216 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12928956 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12927394 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12928956 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12927394 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12928956 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10165090000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12927394 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10164339000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1409749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1397749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14190252246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14187903746 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1255858 # Transaction distribution -system.membus.trans_dist::ReadResp 1255858 # Transaction distribution -system.membus.trans_dist::Writeback 1046505 # Transaction distribution -system.membus.trans_dist::ReadExReq 800112 # Transaction distribution -system.membus.trans_dist::ReadExResp 800112 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5158445 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198558400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198558400 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1254858 # Transaction distribution +system.membus.trans_dist::ReadResp 1254858 # Transaction distribution +system.membus.trans_dist::Writeback 1046245 # Transaction distribution +system.membus.trans_dist::ReadExReq 799953 # Transaction distribution +system.membus.trans_dist::ReadExResp 799953 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5155867 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5155867 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198467584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198467584 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3102475 # Request fanout histogram +system.membus.snoop_fanout::samples 3101056 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3102475 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3101056 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3102475 # Request fanout histogram -system.membus.reqLayer0.occupancy 7945005500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3101056 # Request fanout histogram +system.membus.reqLayer0.occupancy 7929911000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 11244435500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11237799750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |