diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/long/se/60.bzip2 | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/long/se/60.bzip2')
6 files changed, 2950 insertions, 2805 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 38d19f012..e7cd333d6 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.200149 # Number of seconds simulated -sim_ticks 1200148658000 # Number of ticks simulated -final_tick 1200148658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.199774 # Number of seconds simulated +sim_ticks 1199774280000 # Number of ticks simulated +final_tick 1199774280000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 401299 # Simulator instruction rate (inst/s) -host_op_rate 401299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 263701147 # Simulator tick rate (ticks/s) -host_mem_usage 236908 # Number of bytes of host memory used -host_seconds 4551.17 # Real time elapsed on the host +host_inst_rate 344306 # Simulator instruction rate (inst/s) +host_op_rate 344306 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 226179780 # Simulator tick rate (ticks/s) +host_mem_usage 294788 # Number of bytes of host memory used +host_seconds 5304.52 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 125506304 # Number of bytes read from this memory -system.physmem.bytes_read::total 125506304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 125505984 # Number of bytes read from this memory +system.physmem.bytes_read::total 125505984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65167488 # Number of bytes written to this memory system.physmem.bytes_written::total 65167488 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1961036 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1961031 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961031 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018242 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018242 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 104575632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 104575632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 51087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54299513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54299513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54299513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 104575632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 158875145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961036 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 104607997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 104607997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 51156 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 51156 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54316457 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54316457 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54316457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 104607997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 158924454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961031 # Number of read requests accepted system.physmem.writeReqs 1018242 # Number of write requests accepted -system.physmem.readBursts 1961036 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 1961031 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1018242 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125423936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82368 # Total number of bytes read from write queue -system.physmem.bytesWritten 65165888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125506304 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 125423808 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 82176 # Total number of bytes read from write queue +system.physmem.bytesWritten 65166208 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125505984 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 65167488 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1287 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 1284 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118759 # Per bank write bursts -system.physmem.perBankRdBursts::1 114099 # Per bank write bursts -system.physmem.perBankRdBursts::2 116224 # Per bank write bursts -system.physmem.perBankRdBursts::3 117761 # Per bank write bursts -system.physmem.perBankRdBursts::4 117826 # Per bank write bursts -system.physmem.perBankRdBursts::5 117519 # Per bank write bursts -system.physmem.perBankRdBursts::6 119878 # Per bank write bursts -system.physmem.perBankRdBursts::7 124524 # Per bank write bursts -system.physmem.perBankRdBursts::8 126972 # Per bank write bursts -system.physmem.perBankRdBursts::9 130092 # Per bank write bursts -system.physmem.perBankRdBursts::10 128660 # Per bank write bursts -system.physmem.perBankRdBursts::11 130342 # Per bank write bursts +system.physmem.perBankRdBursts::0 118757 # Per bank write bursts +system.physmem.perBankRdBursts::1 114096 # Per bank write bursts +system.physmem.perBankRdBursts::2 116226 # Per bank write bursts +system.physmem.perBankRdBursts::3 117770 # Per bank write bursts +system.physmem.perBankRdBursts::4 117824 # Per bank write bursts +system.physmem.perBankRdBursts::5 117523 # Per bank write bursts +system.physmem.perBankRdBursts::6 119882 # Per bank write bursts +system.physmem.perBankRdBursts::7 124516 # Per bank write bursts +system.physmem.perBankRdBursts::8 126973 # Per bank write bursts +system.physmem.perBankRdBursts::9 130090 # Per bank write bursts +system.physmem.perBankRdBursts::10 128654 # Per bank write bursts +system.physmem.perBankRdBursts::11 130347 # Per bank write bursts system.physmem.perBankRdBursts::12 126055 # Per bank write bursts -system.physmem.perBankRdBursts::13 125250 # Per bank write bursts -system.physmem.perBankRdBursts::14 122599 # Per bank write bursts -system.physmem.perBankRdBursts::15 123189 # Per bank write bursts +system.physmem.perBankRdBursts::13 125249 # Per bank write bursts +system.physmem.perBankRdBursts::14 122591 # Per bank write bursts +system.physmem.perBankRdBursts::15 123194 # Per bank write bursts system.physmem.perBankWrBursts::0 61222 # Per bank write bursts -system.physmem.perBankWrBursts::1 61486 # Per bank write bursts -system.physmem.perBankWrBursts::2 60565 # Per bank write bursts +system.physmem.perBankWrBursts::1 61485 # Per bank write bursts +system.physmem.perBankWrBursts::2 60564 # Per bank write bursts system.physmem.perBankWrBursts::3 61239 # Per bank write bursts -system.physmem.perBankWrBursts::4 61662 # Per bank write bursts -system.physmem.perBankWrBursts::5 63103 # Per bank write bursts +system.physmem.perBankWrBursts::4 61658 # Per bank write bursts +system.physmem.perBankWrBursts::5 63101 # Per bank write bursts system.physmem.perBankWrBursts::6 64148 # Per bank write bursts -system.physmem.perBankWrBursts::7 65614 # Per bank write bursts -system.physmem.perBankWrBursts::8 65330 # Per bank write bursts -system.physmem.perBankWrBursts::9 65779 # Per bank write bursts -system.physmem.perBankWrBursts::10 65300 # Per bank write bursts -system.physmem.perBankWrBursts::11 65644 # Per bank write bursts -system.physmem.perBankWrBursts::12 64162 # Per bank write bursts -system.physmem.perBankWrBursts::13 64212 # Per bank write bursts -system.physmem.perBankWrBursts::14 64570 # Per bank write bursts -system.physmem.perBankWrBursts::15 64181 # Per bank write bursts +system.physmem.perBankWrBursts::7 65617 # Per bank write bursts +system.physmem.perBankWrBursts::8 65332 # Per bank write bursts +system.physmem.perBankWrBursts::9 65778 # Per bank write bursts +system.physmem.perBankWrBursts::10 65295 # Per bank write bursts +system.physmem.perBankWrBursts::11 65646 # Per bank write bursts +system.physmem.perBankWrBursts::12 64171 # Per bank write bursts +system.physmem.perBankWrBursts::13 64211 # Per bank write bursts +system.physmem.perBankWrBursts::14 64568 # Per bank write bursts +system.physmem.perBankWrBursts::15 64187 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1200148547500 # Total gap between requests +system.physmem.totGap 1199774169500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961036 # Read request sizes (log2) +system.physmem.readPktSize::6 1961031 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1018242 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1833978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 125753 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1834284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 125445 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,35 +140,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 29968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -189,128 +189,129 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1837714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.708116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.073776 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.879385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1458610 79.37% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 262385 14.28% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49383 2.69% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20628 1.12% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12966 0.71% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7221 0.39% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5354 0.29% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4357 0.24% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16810 0.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1837714 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59460 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.957232 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.327917 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59419 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1838370 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.671596 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.054008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 129.842659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1459678 79.40% 79.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 262161 14.26% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49287 2.68% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20645 1.12% 97.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12893 0.70% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7143 0.39% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5357 0.29% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4451 0.24% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16755 0.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1838370 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59429 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.975652 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.968947 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59388 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59460 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59460 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.124403 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.088362 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.116973 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27861 46.86% 46.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1344 2.26% 49.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 25901 43.56% 92.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3838 6.45% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 438 0.74% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 56 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59460 # Writes before turning the bus around for reads -system.physmem.totQLat 37078229500 # Total ticks spent queuing -system.physmem.totMemAccLat 73823523250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18919.89 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59429 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59429 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.133420 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.097680 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.110939 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27565 46.38% 46.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1269 2.14% 48.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26249 44.17% 92.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3908 6.58% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 362 0.61% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 56 0.09% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 12 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59429 # Writes before turning the bus around for reads +system.physmem.totQLat 36751953000 # Total ticks spent queuing +system.physmem.totMemAccLat 73497209250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798735000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18753.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37669.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 104.51 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 54.30 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 104.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 54.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37503.42 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 104.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 54.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 104.61 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 54.32 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.24 # Data bus utilization in percentage system.physmem.busUtilRead 0.82 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing -system.physmem.readRowHits 726316 # Number of row buffer hits during reads -system.physmem.writeRowHits 413927 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.65 # Row buffer hit rate for writes -system.physmem.avgGap 402832.01 # Average gap between requests -system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 393584177750 # Time in different power states -system.physmem.memoryStateTime::REF 40075360000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 766482185250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6742219680 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 7150867920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3678790500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 3901763250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7383355200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 7901907000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3233772720 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3364273440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 78387404160 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 78387404160 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 410122352430 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 423496116225 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 360328576500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 348597204750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 869876471190 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 872799536745 # Total energy per rank (pJ) -system.physmem.averagePower::0 724.811465 # Core power per rank (mW) -system.physmem.averagePower::1 727.247065 # Core power per rank (mW) -system.cpu.branchPred.lookups 246247636 # Number of BP lookups -system.cpu.branchPred.condPredicted 186450048 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15699340 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 168260719 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165258168 # Number of BTB hits +system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing +system.physmem.readRowHits 726418 # Number of row buffer hits during reads +system.physmem.writeRowHits 413172 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.58 # Row buffer hit rate for writes +system.physmem.avgGap 402707.03 # Average gap between requests +system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6745500720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3680580750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7383386400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3233733840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 409753789290 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 360427621500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 869587605780 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.796496 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 596865139750 # Time in different power states +system.physmem_0.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 562842538250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 7152516000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3902662500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7901961600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3364241040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 422708761260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 349063611000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 872456746680 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.187909 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 577877428500 # Time in different power states +system.physmem_1.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 581827655250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 246222594 # Number of BP lookups +system.cpu.branchPred.condPredicted 186441188 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15682162 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167748253 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165224895 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.215537 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18428845 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104881 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.495747 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18427327 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104678 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452532318 # DTB read hits -system.cpu.dtb.read_misses 4979776 # DTB read misses +system.cpu.dtb.read_hits 452533853 # DTB read hits +system.cpu.dtb.read_misses 4979561 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457512094 # DTB read accesses -system.cpu.dtb.write_hits 161379130 # DTB write hits -system.cpu.dtb.write_misses 1710165 # DTB write misses +system.cpu.dtb.read_accesses 457513414 # DTB read accesses +system.cpu.dtb.write_hits 161377742 # DTB write hits +system.cpu.dtb.write_misses 1710117 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163089295 # DTB write accesses -system.cpu.dtb.data_hits 613911448 # DTB hits -system.cpu.dtb.data_misses 6689941 # DTB misses +system.cpu.dtb.write_accesses 163087859 # DTB write accesses +system.cpu.dtb.data_hits 613911595 # DTB hits +system.cpu.dtb.data_misses 6689678 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620601389 # DTB accesses -system.cpu.itb.fetch_hits 598579568 # ITB hits +system.cpu.dtb.data_accesses 620601273 # DTB accesses +system.cpu.itb.fetch_hits 598493672 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 598579587 # ITB accesses +system.cpu.itb.fetch_accesses 598493691 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -324,66 +325,66 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2400297316 # number of cpu cycles simulated +system.cpu.numCycles 2399548560 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 52410829 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 52395177 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.314239 # CPI: cycles per instruction -system.cpu.ipc 0.760897 # IPC: instructions per cycle -system.cpu.tickCycles 2077436531 # Number of cycles that the object actually ticked -system.cpu.idleCycles 322860785 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9121980 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.680046 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601827690 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126076 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.945943 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16791074000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.680046 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.996260 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996260 # Average percentage of cache occupancy +system.cpu.cpi 1.313829 # CPI: cycles per instruction +system.cpu.ipc 0.761134 # IPC: instructions per cycle +system.cpu.tickCycles 2077217503 # Number of cycles that the object actually ticked +system.cpu.idleCycles 322331057 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9121997 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.675710 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601828569 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126093 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.945917 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16789907000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.675710 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.996259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996259 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1617 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1613 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2310 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231838176 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231838176 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 443337984 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443337984 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 158489706 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158489706 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 601827690 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601827690 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 601827690 # number of overall hits -system.cpu.dcache.overall_hits::total 601827690 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7289564 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289564 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2238796 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238796 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9528360 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9528360 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9528360 # number of overall misses -system.cpu.dcache.overall_misses::total 9528360 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 178244544500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 178244544500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101115441000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 101115441000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 279359985500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 279359985500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 279359985500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 279359985500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 450627548 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450627548 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231839903 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231839903 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 443338834 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443338834 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 158489735 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158489735 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 601828569 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601828569 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 601828569 # number of overall hits +system.cpu.dcache.overall_hits::total 601828569 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7289569 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289569 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2238767 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2238767 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9528336 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9528336 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9528336 # number of overall misses +system.cpu.dcache.overall_misses::total 9528336 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 178039686000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 178039686000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100958450500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 100958450500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 278998136500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 278998136500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 278998136500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 278998136500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 450628403 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450628403 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 611356050 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611356050 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 611356050 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611356050 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 611356905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611356905 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 611356905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611356905 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016176 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016176 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013929 # miss rate for WriteReq accesses @@ -392,14 +393,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.015586 system.cpu.dcache.demand_miss_rate::total 0.015586 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.015586 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015586 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24452.017226 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24452.017226 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45165.098115 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45165.098115 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29318.789960 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29318.789960 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29318.789960 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29318.789960 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24423.897490 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24423.897490 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45095.559520 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45095.559520 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29280.887712 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29280.887712 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29280.887712 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29280.887712 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,32 +409,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700593 # number of writebacks -system.cpu.dcache.writebacks::total 3700593 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50804 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50804 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 351480 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 351480 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 402284 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 402284 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 402284 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 402284 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238760 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238760 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887316 # 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number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6058136 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3700624 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700624 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1107885 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1107885 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7166021 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7166021 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7166021 # number of overall hits +system.cpu.l2cache.overall_hits::total 7166021 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1181581 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1181581 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 779450 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 779450 # 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number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.163208 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163208 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.412990 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.412990 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.214859 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214859 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214859 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214859 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79821.314197 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79821.314197 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80741.377895 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80741.377895 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80187.011450 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80187.011450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80187.011450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80187.011450 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -617,91 +618,91 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1018242 # number of writebacks system.cpu.l2cache.writebacks::total 1018242 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181592 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1181592 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779444 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 779444 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961036 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1961036 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961036 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1961036 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79676806000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79676806000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53247448000 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214860 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214860 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67431.741244 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67431.741244 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68314.655062 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68314.655062 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67782.668957 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67782.668957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67782.668957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67782.668957 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1181581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779450 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 779450 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961031 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1961031 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79473588750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79473588750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53122771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53122771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132596359750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 132596359750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132596359750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 132596359750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163208 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163208 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214859 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214859 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214859 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67260.381430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67260.381430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68154.174097 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68154.174097 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7239718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700593 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887316 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887316 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952745 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954661 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820906816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820968128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7239717 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239717 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887335 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887335 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1918 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952810 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954728 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820909888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820971264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12827627 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12827676 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12827627 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12827676 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12827627 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10114406500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12827676 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10114462000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1631750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1635250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14010883500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14011262000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1181592 # Transaction distribution -system.membus.trans_dist::ReadResp 1181592 # Transaction distribution +system.membus.trans_dist::ReadReq 1181581 # Transaction distribution +system.membus.trans_dist::ReadResp 1181581 # Transaction distribution system.membus.trans_dist::Writeback 1018242 # Transaction distribution -system.membus.trans_dist::ReadExReq 779444 # Transaction distribution -system.membus.trans_dist::ReadExResp 779444 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940314 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940314 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190673792 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 779450 # Transaction distribution +system.membus.trans_dist::ReadExResp 779450 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940304 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190673472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2979278 # Request fanout histogram +system.membus.snoop_fanout::samples 2979273 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2979278 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2979273 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2979278 # Request fanout histogram -system.membus.reqLayer0.occupancy 11833253000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2979273 # Request fanout histogram +system.membus.reqLayer0.occupancy 11833185000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18446066000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18446289250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 704344325..9b6ff7bd3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.662267 # Number of seconds simulated -sim_ticks 662266942000 # Number of ticks simulated -final_tick 662266942000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.662030 # Number of seconds simulated +sim_ticks 662030381000 # Number of ticks simulated +final_tick 662030381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189043 # Simulator instruction rate (inst/s) -host_op_rate 189043 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72116099 # Simulator tick rate (ticks/s) -host_mem_usage 239436 # Number of bytes of host memory used -host_seconds 9183.34 # Real time elapsed on the host +host_inst_rate 173779 # Simulator instruction rate (inst/s) +host_op_rate 173779 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66269486 # Simulator tick rate (ticks/s) +host_mem_usage 296312 # Number of bytes of host memory used +host_seconds 9989.97 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 62272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125973696 # Number of bytes read from this memory -system.physmem.bytes_read::total 126035968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65304064 # Number of bytes written to this memory -system.physmem.bytes_written::total 65304064 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1968339 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1969312 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1020376 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1020376 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 94029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 190215890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 190309919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 94029 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 94029 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98606861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98606861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98606861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 94029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 190215890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 288916779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1969312 # Number of read requests accepted -system.physmem.writeReqs 1020376 # Number of write requests accepted -system.physmem.readBursts 1969312 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1020376 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125955072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 80896 # Total number of bytes read from write queue -system.physmem.bytesWritten 65302080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126035968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65304064 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1264 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125964224 # Number of bytes read from this memory +system.physmem.bytes_read::total 126026048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65301568 # Number of bytes written to this memory +system.physmem.bytes_written::total 65301568 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1968191 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1969157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1020337 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1020337 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 190269552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 190362937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98638325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98638325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98638325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 190269552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 289001263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1969157 # Number of read requests accepted +system.physmem.writeReqs 1020337 # Number of write requests accepted +system.physmem.readBursts 1969157 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1020337 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125945216 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 80832 # Total number of bytes read from write queue +system.physmem.bytesWritten 65299584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126026048 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65301568 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1263 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119151 # Per bank write bursts -system.physmem.perBankRdBursts::1 114520 # Per bank write bursts -system.physmem.perBankRdBursts::2 116626 # Per bank write bursts -system.physmem.perBankRdBursts::3 118169 # Per bank write bursts -system.physmem.perBankRdBursts::4 118249 # Per bank write bursts -system.physmem.perBankRdBursts::5 117904 # Per bank write bursts -system.physmem.perBankRdBursts::6 120341 # Per bank write bursts -system.physmem.perBankRdBursts::7 125053 # Per bank write bursts -system.physmem.perBankRdBursts::8 127649 # Per bank write bursts -system.physmem.perBankRdBursts::9 130602 # Per bank write bursts -system.physmem.perBankRdBursts::10 129289 # Per bank write bursts -system.physmem.perBankRdBursts::11 130962 # Per bank write bursts -system.physmem.perBankRdBursts::12 126769 # Per bank write bursts -system.physmem.perBankRdBursts::13 125905 # Per bank write bursts -system.physmem.perBankRdBursts::14 123070 # Per bank write bursts -system.physmem.perBankRdBursts::15 123789 # Per bank write bursts -system.physmem.perBankWrBursts::0 61320 # Per bank write bursts +system.physmem.perBankRdBursts::0 119107 # Per bank write bursts +system.physmem.perBankRdBursts::1 114513 # Per bank write bursts +system.physmem.perBankRdBursts::2 116588 # Per bank write bursts +system.physmem.perBankRdBursts::3 118130 # Per bank write bursts +system.physmem.perBankRdBursts::4 118281 # Per bank write bursts +system.physmem.perBankRdBursts::5 117894 # Per bank write bursts +system.physmem.perBankRdBursts::6 120372 # Per bank write bursts +system.physmem.perBankRdBursts::7 125027 # Per bank write bursts +system.physmem.perBankRdBursts::8 127642 # Per bank write bursts +system.physmem.perBankRdBursts::9 130604 # Per bank write bursts +system.physmem.perBankRdBursts::10 129295 # Per bank write bursts +system.physmem.perBankRdBursts::11 130929 # Per bank write bursts +system.physmem.perBankRdBursts::12 126770 # Per bank write bursts +system.physmem.perBankRdBursts::13 125862 # Per bank write bursts +system.physmem.perBankRdBursts::14 123081 # Per bank write bursts +system.physmem.perBankRdBursts::15 123799 # Per bank write bursts +system.physmem.perBankWrBursts::0 61289 # Per bank write bursts system.physmem.perBankWrBursts::1 61597 # Per bank write bursts -system.physmem.perBankWrBursts::2 60678 # Per bank write bursts -system.physmem.perBankWrBursts::3 61357 # Per bank write bursts -system.physmem.perBankWrBursts::4 61793 # Per bank write bursts -system.physmem.perBankWrBursts::5 63216 # Per bank write bursts -system.physmem.perBankWrBursts::6 64269 # Per bank write bursts -system.physmem.perBankWrBursts::7 65744 # Per bank write bursts -system.physmem.perBankWrBursts::8 65524 # Per bank write bursts -system.physmem.perBankWrBursts::9 65904 # Per bank write bursts -system.physmem.perBankWrBursts::10 65459 # Per bank write bursts -system.physmem.perBankWrBursts::11 65777 # Per bank write bursts -system.physmem.perBankWrBursts::12 64349 # Per bank write bursts -system.physmem.perBankWrBursts::13 64362 # Per bank write bursts -system.physmem.perBankWrBursts::14 64665 # Per bank write bursts -system.physmem.perBankWrBursts::15 64331 # Per bank write bursts +system.physmem.perBankWrBursts::2 60658 # Per bank write bursts +system.physmem.perBankWrBursts::3 61339 # Per bank write bursts +system.physmem.perBankWrBursts::4 61821 # Per bank write bursts +system.physmem.perBankWrBursts::5 63209 # Per bank write bursts +system.physmem.perBankWrBursts::6 64289 # Per bank write bursts +system.physmem.perBankWrBursts::7 65739 # Per bank write bursts +system.physmem.perBankWrBursts::8 65503 # Per bank write bursts +system.physmem.perBankWrBursts::9 65920 # Per bank write bursts +system.physmem.perBankWrBursts::10 65439 # Per bank write bursts +system.physmem.perBankWrBursts::11 65771 # Per bank write bursts +system.physmem.perBankWrBursts::12 64363 # Per bank write bursts +system.physmem.perBankWrBursts::13 64352 # Per bank write bursts +system.physmem.perBankWrBursts::14 64685 # Per bank write bursts +system.physmem.perBankWrBursts::15 64332 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 662266852500 # Total gap between requests +system.physmem.totGap 662030291500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1969312 # Read request sizes (log2) +system.physmem.readPktSize::6 1969157 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1020376 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1619195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 248434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 76068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1020337 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1619145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 248303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 76115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,38 +144,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 64564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 63086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 64803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -193,151 +193,142 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1775882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.694867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.878503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 136.793796 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1380775 77.75% 77.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 271356 15.28% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53913 3.04% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21326 1.20% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12854 0.72% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6480 0.36% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5132 0.29% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3787 0.21% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20259 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1775882 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59943 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.788466 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.189780 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59903 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 15 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 9 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1776224 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.667141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.863857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 136.742577 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1381396 77.77% 77.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 271071 15.26% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53950 3.04% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21226 1.20% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12955 0.73% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6597 0.37% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5003 0.28% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3759 0.21% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20267 1.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1776224 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59925 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.795728 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 163.660245 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59887 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 9 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59943 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59943 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.021921 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.980571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.225631 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 33661 56.16% 56.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 25267 42.15% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 929 1.55% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 52 0.09% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59943 # Writes before turning the bus around for reads -system.physmem.totQLat 41251747750 # Total ticks spent queuing -system.physmem.totMemAccLat 78152647750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9840240000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20960.74 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59925 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59925 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.026383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.985304 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.212732 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 31950 53.32% 53.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1595 2.66% 55.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 20819 34.74% 90.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4577 7.64% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 750 1.25% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 154 0.26% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 27 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 19 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59925 # Writes before turning the bus around for reads +system.physmem.totQLat 40790268000 # Total ticks spent queuing +system.physmem.totMemAccLat 77688280500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9839470000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20727.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39710.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 190.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 98.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 190.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 98.61 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39477.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 190.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 98.64 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 190.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 98.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.26 # Data bus utilization in percentage system.physmem.busUtilRead 1.49 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.77 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 795732 # Number of row buffer hits during reads -system.physmem.writeRowHits 416769 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.84 # Row buffer hit rate for writes -system.physmem.avgGap 221517.05 # Average gap between requests -system.physmem.pageHitRate 40.57 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 126335534000 # Time in different power states -system.physmem.memoryStateTime::REF 22114300000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 513810229000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6510407400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 6915200040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3552305625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 3773174625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7409890800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 7939939800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3239831520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3372004080 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 43255570800 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 43255570800 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 299907401805 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 307252084365 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 134279187750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 127836483750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 498154595700 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 500344457460 # Total energy per rank (pJ) -system.physmem.averagePower::0 752.204234 # Core power per rank (mW) -system.physmem.averagePower::1 755.510885 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 1197969 # Transaction distribution -system.membus.trans_dist::ReadResp 1197969 # Transaction distribution -system.membus.trans_dist::Writeback 1020376 # Transaction distribution -system.membus.trans_dist::ReadExReq 771343 # Transaction distribution -system.membus.trans_dist::ReadExResp 771343 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4959000 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4959000 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191340032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191340032 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2989688 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2989688 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2989688 # Request fanout histogram -system.membus.reqLayer0.occupancy 11823557000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 18423875500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 410506798 # Number of BP lookups -system.cpu.branchPred.condPredicted 318826270 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16270103 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 283363020 # Number of BTB lookups -system.cpu.branchPred.BTBHits 279346814 # Number of BTB hits +system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing +system.physmem.readRowHits 795786 # Number of row buffer hits during reads +system.physmem.writeRowHits 416180 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.79 # Row buffer hit rate for writes +system.physmem.avgGap 221452.29 # Average gap between requests +system.physmem.pageHitRate 40.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6511261680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3552771750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7409259000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3239617680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 299928124440 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134120853750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 498002202300 # Total energy per rank (pJ) +system.physmem_0.averagePower 752.239455 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 221171423750 # Time in different power states +system.physmem_0.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 418748256250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6916946400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3774127500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7939518600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3371965200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 306633623535 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 128238837000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 500115332235 # Total energy per rank (pJ) +system.physmem_1.averagePower 755.431368 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 211341940750 # Time in different power states +system.physmem_1.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 428577885750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 410531758 # Number of BP lookups +system.cpu.branchPred.condPredicted 318847451 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16269165 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 283137932 # Number of BTB lookups +system.cpu.branchPred.BTBHits 279377578 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.582664 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26372853 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.671900 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26373623 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 646169518 # DTB read hits -system.cpu.dtb.read_misses 12159492 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 658329010 # DTB read accesses -system.cpu.dtb.write_hits 218199205 # DTB write hits -system.cpu.dtb.write_misses 7515385 # DTB write misses +system.cpu.dtb.read_hits 646133385 # DTB read hits +system.cpu.dtb.read_misses 12154937 # DTB read misses +system.cpu.dtb.read_acv 1 # DTB read access violations +system.cpu.dtb.read_accesses 658288322 # DTB read accesses +system.cpu.dtb.write_hits 218173916 # DTB write hits +system.cpu.dtb.write_misses 7514058 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225714590 # DTB write accesses -system.cpu.dtb.data_hits 864368723 # DTB hits -system.cpu.dtb.data_misses 19674877 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 884043600 # DTB accesses -system.cpu.itb.fetch_hits 422435766 # ITB hits -system.cpu.itb.fetch_misses 46 # ITB misses +system.cpu.dtb.write_accesses 225687974 # DTB write accesses +system.cpu.dtb.data_hits 864307301 # DTB hits +system.cpu.dtb.data_misses 19668995 # DTB misses +system.cpu.dtb.data_acv 1 # DTB access violations +system.cpu.dtb.data_accesses 883976296 # DTB accesses +system.cpu.itb.fetch_hits 422458110 # ITB hits +system.cpu.itb.fetch_misses 45 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 422435812 # ITB accesses +system.cpu.itb.fetch_accesses 422458155 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -351,98 +342,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1324533885 # number of cpu cycles simulated +system.cpu.numCycles 1324060763 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 433728129 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3419447982 # Number of instructions fetch has processed -system.cpu.fetch.Branches 410506798 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 305719667 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 867740174 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45999556 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 89 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1859 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 122 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 422435766 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8419815 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1324470151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.581748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.157662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 433748906 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3419441963 # Number of instructions fetch has processed +system.cpu.fetch.Branches 410531758 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 305751201 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 867248304 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45995858 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 88 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1804 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 422458110 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8422260 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1323997070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.582666 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.157790 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 697483370 52.66% 52.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48005474 3.62% 56.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24395138 1.84% 58.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45249876 3.42% 61.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142980828 10.80% 72.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 66219617 5.00% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43796288 3.31% 80.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29613001 2.24% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226726559 17.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 696991073 52.64% 52.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48002120 3.63% 56.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24407254 1.84% 58.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45263157 3.42% 61.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142993214 10.80% 72.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 66222276 5.00% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43788088 3.31% 80.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29616004 2.24% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226713884 17.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1324470151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309925 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.581624 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 355594570 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 385179518 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 525809516 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34887563 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22998984 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62292881 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 862 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3264034617 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2122 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22998984 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 373946851 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 205483814 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7143 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 538725666 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 183307693 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3181027912 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1764061 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19006533 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 140449897 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27939508 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2377346604 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4126580900 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4126409923 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 170976 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1323997070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310055 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.582542 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 355597650 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 384696746 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 525812607 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34892959 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22997108 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62293389 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 869 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3264034948 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2192 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22997108 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 373957968 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 205165673 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7731 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 538730067 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 183138523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3181033284 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1755579 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18983042 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 140285341 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27927823 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2377354751 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4126620289 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4126448707 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 171581 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1001143641 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 182 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 180 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99171579 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 719206222 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272877842 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90853191 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58764648 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2889718435 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 163 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2624030011 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1568714 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1139278450 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 505521247 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 134 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1324470151 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981192 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.151140 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1001151788 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 192 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 191 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99207749 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 719206023 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272877739 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90880933 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 59162115 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2889782486 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 178 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2624016708 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1570062 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1139342915 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 505618557 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 149 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1323997070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.981890 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.151111 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 520285766 39.28% 39.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169352294 12.79% 52.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158263377 11.95% 64.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149147598 11.26% 75.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126214674 9.53% 84.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84460771 6.38% 91.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68224303 5.15% 96.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33971144 2.56% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14550224 1.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 519747645 39.26% 39.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169377682 12.79% 52.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158338012 11.96% 64.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149173722 11.27% 75.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126185648 9.53% 84.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84437665 6.38% 91.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68199937 5.15% 96.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33982775 2.57% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14553984 1.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1324470151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1323997070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13169928 35.70% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13171575 35.70% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.70% # attempts to use FU when none available @@ -471,118 +462,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19111172 51.81% 87.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4608428 12.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19111155 51.80% 87.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4612971 12.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1719281995 65.52% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 111 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1719329788 65.52% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 125 0.00% 65.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896550 0.03% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 159 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 672977290 25.65% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230873835 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 895316 0.03% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 672939161 25.65% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230852080 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2624030011 # Type of FU issued -system.cpu.iq.rate 1.981097 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36889528 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014058 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6609007948 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4027844088 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2521909296 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1980467 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1299263 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 893137 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2659936163 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 983376 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69546745 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2624016708 # Type of FU issued +system.cpu.iq.rate 1.981795 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36895701 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014061 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6608517036 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4027973051 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2521923586 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1979213 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1297888 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 892539 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2659929620 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 982789 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69543206 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 274610559 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 379781 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 148802 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 112149340 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 274610360 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 379362 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 147727 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 112149237 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 343 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6024507 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6023017 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22998984 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 147954834 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18526434 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3040938881 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6690511 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 719206222 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272877842 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 163 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 822212 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17973283 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 148802 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10902941 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8845995 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19748936 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2578346915 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 658329015 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45683096 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22997108 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 147758887 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18474565 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3040988458 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6691344 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 719206023 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272877739 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 178 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 822290 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17921565 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 147727 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10901488 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8843129 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19744617 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2578330269 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 658288327 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45686439 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151220283 # number of nop insts executed -system.cpu.iew.exec_refs 884043668 # number of memory reference insts executed -system.cpu.iew.exec_branches 315967801 # Number of branches executed -system.cpu.iew.exec_stores 225714653 # Number of stores executed -system.cpu.iew.exec_rate 1.946607 # Inst execution rate -system.cpu.iew.wb_sent 2552803336 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2522802433 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1489230488 # num instructions producing a value -system.cpu.iew.wb_consumers 1920481156 # num instructions consuming a value +system.cpu.iew.exec_nop 151205794 # number of nop insts executed +system.cpu.iew.exec_refs 883976375 # number of memory reference insts executed +system.cpu.iew.exec_branches 315983093 # Number of branches executed +system.cpu.iew.exec_stores 225688048 # Number of stores executed +system.cpu.iew.exec_rate 1.947290 # Inst execution rate +system.cpu.iew.wb_sent 2552817971 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2522816125 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1489246506 # num instructions producing a value +system.cpu.iew.wb_consumers 1920479792 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.904672 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775447 # average fanout of values written-back +system.cpu.iew.wb_rate 1.905363 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775455 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1005079964 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1005136223 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16269309 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1185591559 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.534913 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.558094 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16268344 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1185116972 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.535528 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.558449 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 696399330 58.74% 58.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159901902 13.49% 72.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79790439 6.73% 78.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52118707 4.40% 83.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28427889 2.40% 85.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19400301 1.64% 87.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20045609 1.69% 89.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23104546 1.95% 91.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106402836 8.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 695949152 58.72% 58.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159874809 13.49% 72.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79784402 6.73% 78.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52116706 4.40% 83.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28440614 2.40% 85.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19407125 1.64% 87.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20027045 1.69% 89.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23110908 1.95% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106406211 8.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1185591559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1185116972 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -628,233 +619,339 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106402836 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106406211 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3818269613 # The number of ROB reads -system.cpu.rob.rob_writes 5788733936 # The number of ROB writes -system.cpu.timesIdled 729 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 63734 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3817847910 # The number of ROB reads +system.cpu.rob.rob_writes 5788846951 # The number of ROB writes +system.cpu.timesIdled 724 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 63693 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.762961 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.762961 # CPI: Total CPI of All Threads -system.cpu.ipc 1.310683 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.310683 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3467602221 # number of integer regfile reads -system.cpu.int_regfile_writes 2022271322 # number of integer regfile writes -system.cpu.fp_regfile_reads 45596 # number of floating regfile reads -system.cpu.fp_regfile_writes 565 # number of floating regfile writes +system.cpu.cpi 0.762689 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.762689 # CPI: Total CPI of All Threads +system.cpu.ipc 1.311151 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.311151 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3467581476 # number of integer regfile reads +system.cpu.int_regfile_writes 2022302956 # number of integer regfile writes +system.cpu.fp_regfile_reads 46080 # number of floating regfile reads +system.cpu.fp_regfile_writes 592 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 7335000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7335000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3742826 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879134 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879134 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1946 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22169148 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22171094 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829183168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 829245440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12957100 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12957100 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12957100 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10221444363 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1621500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14117208750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.cpu.dcache.tags.replacements 9209012 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.412521 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 713854428 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9213108 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.482477 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5099544250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.412521 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 751 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2935 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1472845170 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1472845170 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 558341279 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 558341279 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155513145 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155513145 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 713854424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 713854424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 713854424 # number of overall hits +system.cpu.dcache.overall_hits::total 713854424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12746245 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12746245 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5215357 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5215357 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 17961602 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17961602 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17961602 # number of overall misses +system.cpu.dcache.overall_misses::total 17961602 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 384451562750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 384451562750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289305166008 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289305166008 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 69500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 69500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 673756728758 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 673756728758 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 673756728758 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 673756728758 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 571087524 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 571087524 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 731816026 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731816026 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731816026 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731816026 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032448 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024544 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024544 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024544 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024544 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30161.946734 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30161.946734 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55471.785730 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55471.785730 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37510.948564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37510.948564 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14120110 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8634302 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1055091 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67341 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.382836 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 128.217609 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3742780 # number of writebacks +system.cpu.dcache.writebacks::total 3742780 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5412238 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5412238 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3336257 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3336257 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8748495 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8748495 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8748495 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8748495 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334007 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7334007 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879100 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879100 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9213107 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9213107 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9213107 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9213107 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168659488250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168659488250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77208966781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77208966781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 67500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 67500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245868455031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245868455031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245868455031 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245868455031 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22996.908545 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22996.908545 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41088.269268 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41088.269268 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 67500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 772.533395 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 422434249 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 973 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 434156.473792 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 770.158211 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 422456585 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 966 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 437325.657350 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 772.533395 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377214 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377214 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 972 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 907 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 844872503 # Number of tag accesses -system.cpu.icache.tags.data_accesses 844872503 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 422434249 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 422434249 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 422434249 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 422434249 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 422434249 # number of overall hits -system.cpu.icache.overall_hits::total 422434249 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1516 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1516 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1516 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1516 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1516 # number of overall misses -system.cpu.icache.overall_misses::total 1516 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 104441749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 104441749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 104441749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 104441749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 104441749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 104441749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 422435765 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 422435765 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 422435765 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 422435765 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 422435765 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 422435765 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 770.158211 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.376054 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.376054 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 899 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 844917184 # Number of tag accesses +system.cpu.icache.tags.data_accesses 844917184 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 422456585 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 422456585 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 422456585 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 422456585 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 422456585 # number of overall hits +system.cpu.icache.overall_hits::total 422456585 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1524 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1524 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1524 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1524 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1524 # number of overall misses +system.cpu.icache.overall_misses::total 1524 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 107000999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 107000999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 107000999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 107000999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 107000999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 107000999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 422458109 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 422458109 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 422458109 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 422458109 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 422458109 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 422458109 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68892.974274 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68892.974274 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68892.974274 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68892.974274 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68892.974274 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68892.974274 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70210.629265 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70210.629265 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70210.629265 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70210.629265 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70210.629265 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70210.629265 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 469 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 58.625000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 543 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 543 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 543 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 543 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 543 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 543 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 973 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 973 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 973 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 973 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 973 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 973 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72760499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 72760499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72760499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 72760499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72760499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 72760499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 558 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 558 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 558 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 558 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 558 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 558 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72141249 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 72141249 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72141249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 72141249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72141249 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 72141249 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74779.546763 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74779.546763 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74779.546763 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74779.546763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74779.546763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74779.546763 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74680.381988 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74680.381988 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74680.381988 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74680.381988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74680.381988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74680.381988 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1936599 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31406.671872 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9110908 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1966387 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.633324 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 27876757750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14558.085450 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.965177 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16821.621245 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.444278 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000823 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.513355 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958456 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29788 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 1936441 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31406.538176 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9110982 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1966231 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.633729 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 27876136750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14557.398525 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.847630 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16822.292021 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70332.903826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61182.939363 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70337.426886 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70332.903826 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213629 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.213712 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61075.310559 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70093.929761 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70086.656869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70121.790747 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70121.790747 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61075.310559 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61075.310559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9209065 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.415581 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 713883338 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9213161 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.485169 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5099544250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.415581 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997904 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997904 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 748 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2938 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1472907715 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1472907715 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 558369192 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 558369192 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155514142 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155514142 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 713883334 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 713883334 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 713883334 # number of overall hits -system.cpu.dcache.overall_hits::total 713883334 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12749578 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12749578 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5214360 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5214360 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17963938 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17963938 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17963938 # number of overall misses -system.cpu.dcache.overall_misses::total 17963938 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 385716453000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 385716453000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 289481531698 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 289481531698 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 71500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 675197984698 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 675197984698 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 675197984698 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 675197984698 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 571118770 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 571118770 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 731847272 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 731847272 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 731847272 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 731847272 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022324 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022324 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032442 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032442 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024546 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024546 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024546 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024546 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30253.272148 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30253.272148 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55516.215163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55516.215163 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37586.301216 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37586.301216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37586.301216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37586.301216 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14206702 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8627771 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1055420 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67280 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.460709 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 128.236787 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3742826 # number of writebacks -system.cpu.dcache.writebacks::total 3742826 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5415535 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5415535 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3335243 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3335243 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8750778 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8750778 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8750778 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8750778 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334043 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7334043 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879117 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879117 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9213160 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9213160 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9213160 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9213160 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168998137000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168998137000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77338215218 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77338215218 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 246336352218 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 246336352218 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 246336352218 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 246336352218 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23042.970569 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23042.970569 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41156.679024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41156.679024 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 7334962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7334962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3742780 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879112 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879112 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1932 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22170928 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829176832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 829238656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12957003 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12957003 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12957003 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10221354853 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1610750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14117356000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1197871 # Transaction distribution +system.membus.trans_dist::ReadResp 1197871 # Transaction distribution +system.membus.trans_dist::Writeback 1020337 # Transaction distribution +system.membus.trans_dist::ReadExReq 771286 # Transaction distribution +system.membus.trans_dist::ReadExResp 771286 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958651 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4958651 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191327616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191327616 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2989494 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2989494 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2989494 # Request fanout histogram +system.membus.reqLayer0.occupancy 11823428000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 18423304250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index b905eb22a..1d6a1c5a9 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.108945 # Number of seconds simulated -sim_ticks 1108944740000 # Number of ticks simulated -final_tick 1108944740000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.108725 # Number of seconds simulated +sim_ticks 1108725388000 # Number of ticks simulated +final_tick 1108725388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239014 # Simulator instruction rate (inst/s) -host_op_rate 257501 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171603826 # Simulator tick rate (ticks/s) -host_mem_usage 253696 # Number of bytes of host memory used -host_seconds 6462.24 # Real time elapsed on the host +host_inst_rate 243193 # Simulator instruction rate (inst/s) +host_op_rate 262004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174570169 # Simulator tick rate (ticks/s) +host_mem_usage 311428 # Number of bytes of host memory used +host_seconds 6351.17 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131625408 # Number of bytes read from this memory -system.physmem.bytes_read::total 131625408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 131558336 # Number of bytes read from this memory +system.physmem.bytes_read::total 131558336 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66989632 # Number of bytes written to this memory -system.physmem.bytes_written::total 66989632 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2056647 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2056647 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046713 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046713 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 118694289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 118694289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60408449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60408449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60408449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 118694289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 179102739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2056647 # Number of read requests accepted -system.physmem.writeReqs 1046713 # Number of write requests accepted -system.physmem.readBursts 2056647 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046713 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131542016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83392 # Total number of bytes read from write queue -system.physmem.bytesWritten 66988032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131625408 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66989632 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1303 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_written::writebacks 66970688 # Number of bytes written to this memory +system.physmem.bytes_written::total 66970688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2055599 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2055599 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046417 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046417 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 118657277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 118657277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60403314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60403314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60403314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 118657277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 179060592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2055599 # Number of read requests accepted +system.physmem.writeReqs 1046417 # Number of write requests accepted +system.physmem.readBursts 2055599 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046417 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131472320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue +system.physmem.bytesWritten 66969088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131558336 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66970688 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 128036 # Per bank write bursts -system.physmem.perBankRdBursts::1 125234 # Per bank write bursts -system.physmem.perBankRdBursts::2 122300 # Per bank write bursts -system.physmem.perBankRdBursts::3 124230 # Per bank write bursts -system.physmem.perBankRdBursts::4 123415 # Per bank write bursts -system.physmem.perBankRdBursts::5 123345 # Per bank write bursts -system.physmem.perBankRdBursts::6 123964 # Per bank write bursts -system.physmem.perBankRdBursts::7 124409 # Per bank write bursts -system.physmem.perBankRdBursts::8 131872 # Per bank write bursts -system.physmem.perBankRdBursts::9 134140 # Per bank write bursts -system.physmem.perBankRdBursts::10 132473 # Per bank write bursts -system.physmem.perBankRdBursts::11 133756 # Per bank write bursts -system.physmem.perBankRdBursts::12 133901 # Per bank write bursts -system.physmem.perBankRdBursts::13 134102 # Per bank write bursts -system.physmem.perBankRdBursts::14 129958 # Per bank write bursts -system.physmem.perBankRdBursts::15 130209 # Per bank write bursts -system.physmem.perBankWrBursts::0 65849 # Per bank write bursts -system.physmem.perBankWrBursts::1 64131 # Per bank write bursts -system.physmem.perBankWrBursts::2 62381 # Per bank write bursts -system.physmem.perBankWrBursts::3 62840 # Per bank write bursts -system.physmem.perBankWrBursts::4 62871 # Per bank write bursts -system.physmem.perBankWrBursts::5 62990 # Per bank write bursts -system.physmem.perBankWrBursts::6 64312 # Per bank write bursts -system.physmem.perBankWrBursts::7 65310 # Per bank write bursts -system.physmem.perBankWrBursts::8 67027 # Per bank write bursts -system.physmem.perBankWrBursts::9 67624 # Per bank write bursts -system.physmem.perBankWrBursts::10 67292 # Per bank write bursts -system.physmem.perBankWrBursts::11 67645 # Per bank write bursts -system.physmem.perBankWrBursts::12 67063 # Per bank write bursts -system.physmem.perBankWrBursts::13 67560 # Per bank write bursts -system.physmem.perBankWrBursts::14 66200 # Per bank write bursts -system.physmem.perBankWrBursts::15 65593 # Per bank write bursts +system.physmem.perBankRdBursts::0 127971 # Per bank write bursts +system.physmem.perBankRdBursts::1 125115 # Per bank write bursts +system.physmem.perBankRdBursts::2 122192 # Per bank write bursts +system.physmem.perBankRdBursts::3 124223 # Per bank write bursts +system.physmem.perBankRdBursts::4 123351 # Per bank write bursts +system.physmem.perBankRdBursts::5 123340 # Per bank write bursts +system.physmem.perBankRdBursts::6 123758 # Per bank write bursts +system.physmem.perBankRdBursts::7 124120 # Per bank write bursts +system.physmem.perBankRdBursts::8 131994 # Per bank write bursts +system.physmem.perBankRdBursts::9 134060 # Per bank write bursts +system.physmem.perBankRdBursts::10 132574 # Per bank write bursts +system.physmem.perBankRdBursts::11 133683 # Per bank write bursts +system.physmem.perBankRdBursts::12 133864 # Per bank write bursts +system.physmem.perBankRdBursts::13 133891 # Per bank write bursts +system.physmem.perBankRdBursts::14 129793 # Per bank write bursts +system.physmem.perBankRdBursts::15 130326 # Per bank write bursts +system.physmem.perBankWrBursts::0 65785 # Per bank write bursts +system.physmem.perBankWrBursts::1 64106 # Per bank write bursts +system.physmem.perBankWrBursts::2 62369 # Per bank write bursts +system.physmem.perBankWrBursts::3 62872 # Per bank write bursts +system.physmem.perBankWrBursts::4 62855 # Per bank write bursts +system.physmem.perBankWrBursts::5 62943 # Per bank write bursts +system.physmem.perBankWrBursts::6 64256 # Per bank write bursts +system.physmem.perBankWrBursts::7 65177 # Per bank write bursts +system.physmem.perBankWrBursts::8 67064 # Per bank write bursts +system.physmem.perBankWrBursts::9 67603 # Per bank write bursts +system.physmem.perBankWrBursts::10 67361 # Per bank write bursts +system.physmem.perBankWrBursts::11 67637 # Per bank write bursts +system.physmem.perBankWrBursts::12 67067 # Per bank write bursts +system.physmem.perBankWrBursts::13 67487 # Per bank write bursts +system.physmem.perBankWrBursts::14 66154 # Per bank write bursts +system.physmem.perBankWrBursts::15 65656 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1108944651500 # Total gap between requests +system.physmem.totGap 1108725299500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2056647 # Read request sizes (log2) +system.physmem.readPktSize::6 2055599 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046713 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1923205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132121 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046417 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1922438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131799 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,28 +140,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 79 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -189,104 +189,114 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1918209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.496643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.775288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.095886 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1492147 77.79% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 306422 15.97% 93.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52965 2.76% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21185 1.10% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13242 0.69% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7471 0.39% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5204 0.27% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3914 0.20% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15659 0.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1918209 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61025 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.632724 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.189303 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60982 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1917383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.495400 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.766538 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.134212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1491936 77.81% 77.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 306042 15.96% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52771 2.75% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21239 1.11% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13137 0.69% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7295 0.38% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5316 0.28% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4195 0.22% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15452 0.81% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1917383 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60970 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.645219 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 157.122880 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60927 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61025 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61025 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.151790 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.116821 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.097688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27581 45.20% 45.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1180 1.93% 47.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28172 46.16% 93.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3706 6.07% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 317 0.52% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 54 0.09% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60970 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.162408 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.127431 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.097398 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27276 44.74% 44.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1165 1.91% 46.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28420 46.61% 93.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3653 5.99% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 385 0.63% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 61 0.10% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 7 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61025 # Writes before turning the bus around for reads -system.physmem.totQLat 38537340500 # Total ticks spent queuing -system.physmem.totMemAccLat 77075040500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10276720000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18749.83 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 60970 # Writes before turning the bus around for reads +system.physmem.totQLat 38268969000 # Total ticks spent queuing +system.physmem.totMemAccLat 76786250250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10271275000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18629.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37499.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 118.62 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 60.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 118.69 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.41 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37379.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 118.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 60.40 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 118.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.40 # Data bus utilization in percentage system.physmem.busUtilRead 0.93 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing -system.physmem.readRowHits 777039 # Number of row buffer hits during reads -system.physmem.writeRowHits 406774 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.86 # Row buffer hit rate for writes -system.physmem.avgGap 357336.77 # Average gap between requests +system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing +system.physmem.readRowHits 776845 # Number of row buffer hits during reads +system.physmem.writeRowHits 406412 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.84 # Row buffer hit rate for writes +system.physmem.avgGap 357420.88 # Average gap between requests system.physmem.pageHitRate 38.16 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 313164826000 # Time in different power states -system.physmem.memoryStateTime::REF 37029980000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 758746776000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 7075638360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 7426006560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3860715375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 4051888500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7760165400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 8271151200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3309232320 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3473305920 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 72430640880 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 72430640880 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 416866648005 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 425333204280 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 299692308000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 292265504250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 810995348340 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 813251701590 # Total energy per rank (pJ) -system.physmem.averagePower::0 731.323936 # Core power per rank (mW) -system.physmem.averagePower::1 733.358627 # Core power per rank (mW) -system.cpu.branchPred.lookups 240152510 # Number of BP lookups -system.cpu.branchPred.condPredicted 186756179 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14598640 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131763268 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122287171 # Number of BTB hits +system.physmem_0.actEnergy 7070973840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3858170250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7753512000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3307152240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 416204777970 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 300142086750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 810753074250 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.249224 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 496624730250 # Time in different power states +system.physmem_0.memoryStateTime::REF 37022700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 575075912250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 7424434080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4051030500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8269419600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3473467920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 425140731810 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 292303530750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 813079015860 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.347080 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 483537101750 # Time in different power states +system.physmem_1.memoryStateTime::REF 37022700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 588165429250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 240158127 # Number of BP lookups +system.cpu.branchPred.condPredicted 186758642 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14604059 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 133657061 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122306338 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.808241 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15660181 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 91.507577 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15659556 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -308,6 +318,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -329,6 +347,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -350,6 +376,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -372,90 +406,90 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2217889480 # number of cpu cycles simulated +system.cpu.numCycles 2217450776 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563087 # Number of instructions committed system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed -system.cpu.discardedOps 40077128 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 40093383 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.435933 # CPI: cycles per instruction -system.cpu.ipc 0.696411 # IPC: instructions per cycle -system.cpu.tickCycles 1838736315 # Number of cycles that the object actually ticked -system.cpu.idleCycles 379153165 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9224311 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.608602 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624084220 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9228407 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.626430 # Average number of references to valid blocks. +system.cpu.cpi 1.435649 # CPI: cycles per instruction +system.cpu.ipc 0.696549 # IPC: instructions per cycle +system.cpu.tickCycles 1838812013 # Number of cycles that the object actually ticked +system.cpu.idleCycles 378638763 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9223724 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.606596 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624087400 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9227820 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.631076 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.608602 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.606596 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.997463 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1292 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2484 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1296 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2482 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276551305 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276551305 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 453737568 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453737568 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 170346530 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170346530 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276555670 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276555670 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 453740634 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453740634 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 170346644 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170346644 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 624084098 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624084098 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 624084098 # number of overall hits -system.cpu.dcache.overall_hits::total 624084098 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7337712 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7337712 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2239517 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2239517 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9577229 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9577229 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9577229 # number of overall misses -system.cpu.dcache.overall_misses::total 9577229 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183598363496 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183598363496 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101566510500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 101566510500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 285164873996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 285164873996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 285164873996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 285164873996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 461075280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461075280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 624087278 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624087278 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 624087278 # number of overall hits +system.cpu.dcache.overall_hits::total 624087278 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7337122 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7337122 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2239403 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2239403 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9576525 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9576525 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9576525 # number of overall misses +system.cpu.dcache.overall_misses::total 9576525 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183400270746 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 183400270746 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101399706750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 101399706750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 284799977496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 284799977496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 284799977496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 284799977496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 461077756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461077756 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 633661327 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633661327 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 633661327 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633661327 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.inst 633663803 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633663803 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 633663803 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633663803 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012976 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.015114 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015114 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.015114 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015114 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25021.200545 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25021.200545 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45351.971206 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45351.971206 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29775.300768 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29775.300768 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.015113 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015113 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.015113 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015113 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24996.213876 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24996.213876 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45279.794101 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45279.794101 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29739.386416 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29739.386416 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -464,101 +498,101 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700618 # number of writebacks -system.cpu.dcache.writebacks::total 3700618 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348609 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 348609 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 348822 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348822 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 348822 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348822 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7337499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7337499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890908 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890908 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9228407 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9228407 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9228407 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9228407 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168505826254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168505826254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77457723500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77457723500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245963549754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245963549754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245963549754 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245963549754 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015914 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015914 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 3701129 # number of writebacks +system.cpu.dcache.writebacks::total 3701129 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 221 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348484 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 348484 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 348705 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 348705 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 348705 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 348705 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7336901 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7336901 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890919 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890919 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9227820 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9227820 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9227820 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9227820 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168309061254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168309061254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77322111500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77322111500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245631172754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245631172754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245631172754 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245631172754 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014564 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014564 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014564 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014564 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22965.022040 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22965.022040 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40963.242791 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40963.242791 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26652.871915 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26652.871915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26652.871915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26652.871915 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22940.075279 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22940.075279 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40891.286988 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40891.286988 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26618.548341 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26618.548341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.026879 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466133968 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 661.153981 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466170177 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 568456.058537 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 568500.215854 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.026879 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322767 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322767 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 661.153981 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322829 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322829 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932270396 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932270396 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 466133968 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466133968 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466133968 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466133968 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466133968 # number of overall hits -system.cpu.icache.overall_hits::total 466133968 # number of overall hits +system.cpu.icache.tags.tag_accesses 932342814 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932342814 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 466170177 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466170177 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466170177 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466170177 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466170177 # number of overall hits +system.cpu.icache.overall_hits::total 466170177 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses system.cpu.icache.overall_misses::total 820 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58416499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58416499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58416499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58416499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58416499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58416499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466134788 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466134788 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466134788 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466134788 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466134788 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466134788 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58360249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58360249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58360249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58360249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58360249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58360249 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 466170997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466170997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466170997 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466170997 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466170997 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466170997 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71239.632927 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71239.632927 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71239.632927 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71239.632927 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71239.632927 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71239.632927 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71171.035366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71171.035366 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71171.035366 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71171.035366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71171.035366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71171.035366 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,97 +607,97 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 820 system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56453501 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 56453501 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56453501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 56453501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56453501 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 56453501 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56400751 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 56400751 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56400751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 56400751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56400751 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 56400751 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68845.732927 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68845.732927 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68845.732927 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68845.732927 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68845.732927 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68845.732927 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68781.403659 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68781.403659 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68781.403659 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68781.403659 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68781.403659 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68781.403659 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2023942 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31254.337993 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8984488 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2053718 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.374743 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2022895 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31254.140512 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8985448 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2052670 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.377444 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 59502848750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14996.949277 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 16257.388715 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.457671 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496136 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.953807 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 14999.285776 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 16254.854737 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.457742 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496059 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.953801 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12850 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107383386 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107383386 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6081991 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6081991 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3700618 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3700618 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090584 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1090584 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7172575 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7172575 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7172575 # number of overall hits -system.cpu.l2cache.overall_hits::total 7172575 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1256328 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1256328 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 800324 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 800324 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2056652 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2056652 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2056652 # number of overall misses -system.cpu.l2cache.overall_misses::total 2056652 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100398878250 # 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number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890908 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1890908 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9229227 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9229227 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9229227 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9229227 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171201 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.171201 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423249 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.423249 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222841 # 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average overall miss latency +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 107381741 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 107381741 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 6082213 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6082213 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3701129 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3701129 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090823 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1090823 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7173036 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7173036 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7173036 # number of overall hits +system.cpu.l2cache.overall_hits::total 7173036 # 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number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 164667754000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 164667754000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 164667754000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 164667754000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7337721 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7337721 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3701129 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3701129 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890919 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1890919 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 9228640 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9228640 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9228640 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9228640 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171103 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.171103 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423125 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.423125 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222742 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222742 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.222742 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79808.657531 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79808.657531 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80574.513558 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80574.513558 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80106.749160 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80106.749160 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80106.749160 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80106.749160 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -672,60 +706,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1046713 # number of writebacks -system.cpu.l2cache.writebacks::total 1046713 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1046417 # number of writebacks +system.cpu.l2cache.writebacks::total 1046417 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1256323 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1256323 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800324 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 800324 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2056647 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2056647 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2056647 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2056647 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84521118250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84521118250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54527231750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54527231750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139048350000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 139048350000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139048350000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 139048350000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171200 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171200 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423249 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423249 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.222841 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.222841 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67276.582734 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67276.582734 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68131.446452 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68131.446452 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255503 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1255503 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800096 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 800096 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055599 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2055599 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055599 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2055599 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84332667000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84332667000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54391877500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54391877500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138724544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 138724544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138724544500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 138724544500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222741 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222741 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67170.422532 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67170.422532 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67981.689072 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67981.689072 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7338319 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7338319 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890908 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7337721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7337721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3701129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890919 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890919 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22157432 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22159072 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156769 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22158409 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827457600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827510080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827452736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827505216 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12929845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12929769 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -734,41 +768,41 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 12929845 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 12929769 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12929845 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10165540500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12929769 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10166013500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1391499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1389749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14187091746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14186681246 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1256323 # Transaction distribution -system.membus.trans_dist::ReadResp 1256323 # Transaction distribution -system.membus.trans_dist::Writeback 1046713 # Transaction distribution -system.membus.trans_dist::ReadExReq 800324 # Transaction distribution -system.membus.trans_dist::ReadExResp 800324 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5160007 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5160007 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198615040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198615040 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1255503 # Transaction distribution +system.membus.trans_dist::ReadResp 1255503 # Transaction distribution +system.membus.trans_dist::Writeback 1046417 # Transaction distribution +system.membus.trans_dist::ReadExReq 800096 # Transaction distribution +system.membus.trans_dist::ReadExResp 800096 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157615 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5157615 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198529024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198529024 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3103360 # Request fanout histogram +system.membus.snoop_fanout::samples 3102016 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3103360 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3102016 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3103360 # Request fanout histogram -system.membus.reqLayer0.occupancy 12130659500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3102016 # Request fanout histogram +system.membus.reqLayer0.occupancy 12126859000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 19439818500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 19430032500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index dd7b09a8e..2039a5a26 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.753004 # Number of seconds simulated -sim_ticks 753003557500 # Number of ticks simulated -final_tick 753003557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.756343 # Number of seconds simulated +sim_ticks 756342731500 # Number of ticks simulated +final_tick 756342731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139146 # Simulator instruction rate (inst/s) -host_op_rate 149909 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67836303 # Simulator tick rate (ticks/s) -host_mem_usage 311432 # Number of bytes of host memory used -host_seconds 11100.30 # Real time elapsed on the host +host_inst_rate 137786 # Simulator instruction rate (inst/s) +host_op_rate 148444 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67471289 # Simulator tick rate (ticks/s) +host_mem_usage 311496 # Number of bytes of host memory used +host_seconds 11209.85 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1664032415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 14592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 231381248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 95077696 # Number of bytes read from this memory -system.physmem.bytes_read::total 326473536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 14592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 14592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 107048704 # Number of bytes written to this memory -system.physmem.bytes_written::total 107048704 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 228 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3615332 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1485589 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5101149 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1672636 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1672636 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 307277762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 126264604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 433561744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 142162282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 142162282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 142162282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 307277762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 126264604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 575724026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5101149 # Number of read requests accepted -system.physmem.writeReqs 1672636 # Number of write requests accepted -system.physmem.readBursts 5101149 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1672636 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 326003456 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 470080 # Total number of bytes read from write queue -system.physmem.bytesWritten 107046272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 326473536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 107048704 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7345 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 238887296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63148480 # Number of bytes read from this memory +system.physmem.bytes_read::total 302102080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104863424 # Number of bytes written to this memory +system.physmem.bytes_written::total 104863424 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3732614 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 986695 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4720345 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1638491 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1638491 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 87664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 315845299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 83491885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 399424847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 87664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 87664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 138645378 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 138645378 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 138645378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 87664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 315845299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 83491885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 538070225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4720345 # Number of read requests accepted +system.physmem.writeReqs 1638491 # Number of write requests accepted +system.physmem.readBursts 4720345 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1638491 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 301644480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 457600 # Total number of bytes read from write queue +system.physmem.bytesWritten 104860480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 302102080 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104863424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7150 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 320458 # Per bank write bursts -system.physmem.perBankRdBursts::1 318552 # Per bank write bursts -system.physmem.perBankRdBursts::2 312159 # Per bank write bursts -system.physmem.perBankRdBursts::3 320321 # Per bank write bursts -system.physmem.perBankRdBursts::4 313091 # Per bank write bursts -system.physmem.perBankRdBursts::5 313451 # Per bank write bursts -system.physmem.perBankRdBursts::6 306429 # Per bank write bursts -system.physmem.perBankRdBursts::7 300886 # Per bank write bursts -system.physmem.perBankRdBursts::8 320656 # Per bank write bursts -system.physmem.perBankRdBursts::9 326914 # Per bank write bursts -system.physmem.perBankRdBursts::10 318873 # Per bank write bursts -system.physmem.perBankRdBursts::11 328947 # Per bank write bursts -system.physmem.perBankRdBursts::12 326980 # Per bank write bursts -system.physmem.perBankRdBursts::13 328236 # Per bank write bursts -system.physmem.perBankRdBursts::14 322345 # Per bank write bursts -system.physmem.perBankRdBursts::15 315506 # Per bank write bursts -system.physmem.perBankWrBursts::0 106372 # Per bank write bursts -system.physmem.perBankWrBursts::1 103970 # Per bank write bursts -system.physmem.perBankWrBursts::2 101390 # Per bank write bursts -system.physmem.perBankWrBursts::3 102163 # Per bank write bursts -system.physmem.perBankWrBursts::4 101308 # Per bank write bursts -system.physmem.perBankWrBursts::5 100856 # Per bank write bursts -system.physmem.perBankWrBursts::6 104858 # Per bank write bursts -system.physmem.perBankWrBursts::7 106447 # Per bank write bursts -system.physmem.perBankWrBursts::8 107624 # Per bank write bursts -system.physmem.perBankWrBursts::9 106732 # Per bank write bursts -system.physmem.perBankWrBursts::10 104273 # Per bank write bursts -system.physmem.perBankWrBursts::11 105282 # Per bank write bursts -system.physmem.perBankWrBursts::12 105198 # Per bank write bursts -system.physmem.perBankWrBursts::13 104874 # Per bank write bursts -system.physmem.perBankWrBursts::14 106564 # Per bank write bursts -system.physmem.perBankWrBursts::15 104687 # Per bank write bursts +system.physmem.perBankRdBursts::0 296862 # Per bank write bursts +system.physmem.perBankRdBursts::1 294626 # Per bank write bursts +system.physmem.perBankRdBursts::2 288270 # Per bank write bursts +system.physmem.perBankRdBursts::3 292812 # Per bank write bursts +system.physmem.perBankRdBursts::4 290199 # Per bank write bursts +system.physmem.perBankRdBursts::5 289793 # Per bank write bursts +system.physmem.perBankRdBursts::6 284872 # Per bank write bursts +system.physmem.perBankRdBursts::7 281493 # Per bank write bursts +system.physmem.perBankRdBursts::8 297311 # Per bank write bursts +system.physmem.perBankRdBursts::9 303290 # Per bank write bursts +system.physmem.perBankRdBursts::10 295469 # Per bank write bursts +system.physmem.perBankRdBursts::11 301855 # Per bank write bursts +system.physmem.perBankRdBursts::12 303298 # Per bank write bursts +system.physmem.perBankRdBursts::13 302373 # Per bank write bursts +system.physmem.perBankRdBursts::14 297652 # Per bank write bursts +system.physmem.perBankRdBursts::15 293020 # Per bank write bursts +system.physmem.perBankWrBursts::0 104131 # Per bank write bursts +system.physmem.perBankWrBursts::1 101826 # Per bank write bursts +system.physmem.perBankWrBursts::2 99098 # Per bank write bursts +system.physmem.perBankWrBursts::3 99979 # Per bank write bursts +system.physmem.perBankWrBursts::4 99438 # Per bank write bursts +system.physmem.perBankWrBursts::5 99115 # Per bank write bursts +system.physmem.perBankWrBursts::6 102674 # Per bank write bursts +system.physmem.perBankWrBursts::7 104427 # Per bank write bursts +system.physmem.perBankWrBursts::8 105209 # Per bank write bursts +system.physmem.perBankWrBursts::9 104570 # Per bank write bursts +system.physmem.perBankWrBursts::10 102342 # Per bank write bursts +system.physmem.perBankWrBursts::11 102683 # Per bank write bursts +system.physmem.perBankWrBursts::12 102787 # Per bank write bursts +system.physmem.perBankWrBursts::13 102808 # Per bank write bursts +system.physmem.perBankWrBursts::14 104630 # Per bank write bursts +system.physmem.perBankWrBursts::15 102728 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 753003515500 # Total gap between requests +system.physmem.totGap 756342591500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5101149 # Read request sizes (log2) +system.physmem.readPktSize::6 4720345 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1672636 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2761902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1096580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 406963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 307813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 214927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 130899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 69362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 43944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 31968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 12494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 6876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 4504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 473 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1638491 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2764600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1036830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 329452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 239558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 162691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 91104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 40419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,38 +148,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 25442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 58935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 74795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 100234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 105264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 108420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 110279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 111519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 112924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 114921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 116959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 109523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 106852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 104984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 103460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 22698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 59650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 74848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 91913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 98459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 106253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 107840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 108834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 109988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 110978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 113431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 107071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 104798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 103128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -197,140 +197,132 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4344411 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 99.679291 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.657847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 113.406930 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3407328 78.43% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 696147 16.02% 94.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 107309 2.47% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 43326 1.00% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 33261 0.77% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16273 0.37% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9699 0.22% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6677 0.15% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24391 0.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4344411 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 100519 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 50.674768 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.618065 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.194987 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 98006 97.50% 97.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1235 1.23% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 738 0.73% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 394 0.39% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 104 0.10% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 26 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 7 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3327 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 100519 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 100519 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.639620 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.599991 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.204272 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 73763 73.38% 73.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1810 1.80% 75.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 17937 17.84% 93.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4183 4.16% 97.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1485 1.48% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 646 0.64% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 326 0.32% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 183 0.18% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 100 0.10% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 51 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 16 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 100519 # Writes before turning the bus around for reads -system.physmem.totQLat 147032532073 # Total ticks spent queuing -system.physmem.totMemAccLat 242541357073 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 25469020000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28864.98 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 4285614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.853108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.948636 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 101.693693 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3410667 79.58% 79.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 676414 15.78% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 97051 2.26% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35005 0.82% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22710 0.53% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12276 0.29% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7200 0.17% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5155 0.12% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19136 0.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4285614 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98802 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.703225 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 32.303831 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 97.301104 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 94981 96.13% 96.13% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1362 1.38% 97.51% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-383 759 0.77% 98.28% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 434 0.44% 98.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 380 0.38% 99.10% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 348 0.35% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 273 0.28% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 148 0.15% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 67 0.07% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 20 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 9 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 8 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1663 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1920-2047 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2687 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-2943 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 98802 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98802 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.583116 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.550078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.089696 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 73349 74.24% 74.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1793 1.81% 76.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18295 18.52% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3696 3.74% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 920 0.93% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 398 0.40% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 161 0.16% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 94 0.10% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 50 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 24 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 14 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 98802 # Writes before turning the bus around for reads +system.physmem.totQLat 132475907765 # Total ticks spent queuing +system.physmem.totMemAccLat 220848314015 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23565975000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28107.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47614.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 432.94 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 142.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 433.56 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 142.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46857.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 398.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 138.64 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 399.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 138.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.49 # Data bus utilization in percentage -system.physmem.busUtilRead 3.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.11 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing -system.physmem.readRowHits 2056015 # Number of row buffer hits during reads -system.physmem.writeRowHits 365966 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.88 # Row buffer hit rate for writes -system.physmem.avgGap 111164.37 # Average gap between requests -system.physmem.pageHitRate 35.79 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 77100737509 # Time in different power states -system.physmem.memoryStateTime::REF 25144340000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 650755672741 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 16285857840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 16557549120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 8886132750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 9034377000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 19540895400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 20189722800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 5361143760 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5476960800 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 49182329040 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 49182329040 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 403433749845 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 404376910605 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 97911188250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 97083854250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 600601296885 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 601901703615 # Total energy per rank (pJ) -system.physmem.averagePower::0 797.610503 # Core power per rank (mW) -system.physmem.averagePower::1 799.337469 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 4164250 # Transaction distribution -system.membus.trans_dist::ReadResp 4164249 # Transaction distribution -system.membus.trans_dist::Writeback 1672636 # Transaction distribution -system.membus.trans_dist::ReadExReq 936899 # Transaction distribution -system.membus.trans_dist::ReadExResp 936899 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11874933 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11874933 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 433522176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 433522176 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6773785 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6773785 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6773785 # Request fanout histogram -system.membus.reqLayer0.occupancy 21336071694 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 47387677526 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.3 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 286237274 # Number of BP lookups -system.cpu.branchPred.condPredicted 223376247 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14631258 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157873028 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150326972 # Number of BTB hits +system.physmem.busUtil 4.20 # Data bus utilization in percentage +system.physmem.busUtilRead 3.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.08 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing +system.physmem.readRowHits 1712938 # Number of row buffer hits during reads +system.physmem.writeRowHits 353078 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.55 # Row buffer hit rate for writes +system.physmem.avgGap 118943.56 # Average gap between requests +system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16066436400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8766408750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18087404400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5253193440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 400853320515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 102178887750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 600606152535 # Total energy per rank (pJ) +system.physmem_0.averagePower 794.094387 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 167492103071 # Time in different power states +system.physmem_0.memoryStateTime::REF 25255880000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 563593117929 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 16332729840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8911707750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18675259200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5363826480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 402415744095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100808340750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 601908109395 # Total energy per rank (pJ) +system.physmem_1.averagePower 795.815775 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165215512876 # Time in different power states +system.physmem_1.memoryStateTime::REF 25255880000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 565869633374 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 286251205 # Number of BP lookups +system.cpu.branchPred.condPredicted 223383370 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14630986 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158738952 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150334108 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.220174 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16640209 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.705242 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16640646 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -352,6 +344,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -373,6 +373,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -394,6 +402,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -416,233 +432,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1506007116 # number of cpu cycles simulated +system.cpu.numCycles 1512685464 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13915908 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067206547 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286237274 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166967181 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1477423210 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29286859 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656844028 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 587 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1505982817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.470565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.223309 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13925295 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067334861 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286251205 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166974754 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1484044715 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29286501 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 170 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1090 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656878260 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 961 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1512614520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.464203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.224459 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 423738570 28.14% 28.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465347942 30.90% 59.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101390896 6.73% 65.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515505409 34.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 430302331 28.45% 28.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465370544 30.77% 59.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101420857 6.71% 65.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515520788 34.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1505982817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.190064 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.372641 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74738188 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 508470466 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849951241 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58180203 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14642719 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42195522 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 748 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037029518 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52402529 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14642719 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139800206 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 434773312 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14137 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837909741 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 78842702 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976226014 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26698193 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45123172 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125355 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1314299 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18015097 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985707207 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9127389229 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432660668 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 146 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1512614520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.189234 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.366665 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74740374 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 515177494 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849893259 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58160845 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14642548 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42195150 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2036986769 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52385989 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14642548 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139815435 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 436624028 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12701 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837804287 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 83715521 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976173031 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26689335 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45146280 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125414 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1394915 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22818803 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985649062 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9127137269 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432583454 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 143 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310808262 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 156 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 144 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111604908 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542499825 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199292304 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26858708 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28865215 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947820848 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 310750117 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 155 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111721700 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542489680 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199288909 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26826914 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28715919 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947778041 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857727691 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13537484 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 279225798 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 646033301 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1857580897 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13541153 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 279193675 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 645796508 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1505982817 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.233565 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.149736 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1512614520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.228060 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150014 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 553461726 36.75% 36.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325286672 21.60% 58.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378400557 25.13% 83.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219701727 14.59% 98.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29125951 1.93% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6184 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 560160519 37.03% 37.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325201183 21.50% 58.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378431439 25.02% 83.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219774852 14.53% 98.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29040355 1.92% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6172 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1505982817 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1512614520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166582994 41.01% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1992 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191579576 47.17% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 48024706 11.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166509117 41.02% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1974 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191277328 47.12% 88.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 48123931 11.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138365513 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800977 0.04% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 27 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 26 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532245079 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186316069 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138363415 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801029 0.04% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532094788 28.64% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186321614 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857727691 # Type of FU issued -system.cpu.iq.rate 1.233545 # Inst issue rate -system.cpu.iq.fu_busy_cnt 406189268 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218648 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5641164724 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2227059400 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805827330 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 67 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2263916833 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17868715 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857580897 # Type of FU issued +system.cpu.iq.rate 1.228002 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405912350 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218517 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5647229580 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2226984572 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805831958 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2263493115 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17832338 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84193491 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66602 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12979 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24445259 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84183346 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66238 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13114 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24441864 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4569389 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5015263 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4579390 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4849629 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14642719 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25280273 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1153411 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947821148 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14642548 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25281228 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1183865 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947778336 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542499825 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199292304 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 542489680 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199288909 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 152 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 158606 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 993784 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12979 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7710323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8723960 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16434283 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1828067374 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 517076026 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29660317 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 158613 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1024253 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13114 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7709445 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8723908 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16433353 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827918594 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516926976 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29662303 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 86 # number of nop insts executed -system.cpu.iew.exec_refs 698832649 # number of memory reference insts executed -system.cpu.iew.exec_branches 229600081 # Number of branches executed -system.cpu.iew.exec_stores 181756623 # Number of stores executed -system.cpu.iew.exec_rate 1.213850 # Inst execution rate -system.cpu.iew.wb_sent 1808848691 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805827397 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169333238 # num instructions producing a value -system.cpu.iew.wb_consumers 1689629138 # num instructions consuming a value +system.cpu.iew.exec_nop 81 # number of nop insts executed +system.cpu.iew.exec_refs 698686621 # number of memory reference insts executed +system.cpu.iew.exec_branches 229598858 # Number of branches executed +system.cpu.iew.exec_stores 181759645 # Number of stores executed +system.cpu.iew.exec_rate 1.208393 # Inst execution rate +system.cpu.iew.wb_sent 1808851456 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805832027 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169265268 # num instructions producing a value +system.cpu.iew.wb_consumers 1689455879 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.199083 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692065 # average fanout of values written-back +system.cpu.iew.wb_rate 1.193792 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 257853927 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 257820227 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14630548 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1466512041 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.134687 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.044179 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14630284 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1473146552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.129577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.040655 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 886829793 60.47% 60.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250699029 17.09% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 109472668 7.46% 85.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55016344 3.75% 88.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29216480 1.99% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 33954895 2.32% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24874922 1.70% 94.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18134171 1.24% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58313739 3.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 893288218 60.64% 60.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250810214 17.03% 77.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 109558722 7.44% 85.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55058301 3.74% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29206870 1.98% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 33934631 2.30% 93.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24884814 1.69% 94.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18117903 1.23% 96.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58286879 3.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1466512041 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1473146552 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -688,390 +704,77 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction -system.cpu.commit.bw_lim_events 58313739 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 58286879 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3330084063 # The number of ROB reads -system.cpu.rob.rob_writes 3883248692 # The number of ROB writes -system.cpu.timesIdled 433 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24299 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3336711734 # The number of ROB reads +system.cpu.rob.rob_writes 3883178493 # The number of ROB writes +system.cpu.timesIdled 871 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 70944 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.975038 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.975038 # CPI: Total CPI of All Threads -system.cpu.ipc 1.025601 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.025601 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2176017062 # number of integer regfile reads -system.cpu.int_regfile_writes 1261587528 # number of integer regfile writes +system.cpu.cpi 0.979361 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.979361 # CPI: Total CPI of All Threads +system.cpu.ipc 1.021073 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.021073 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175874054 # number of integer regfile reads +system.cpu.int_regfile_writes 1261590215 # number of integer regfile writes system.cpu.fp_regfile_reads 38 # number of floating regfile reads -system.cpu.fp_regfile_writes 49 # number of floating regfile writes -system.cpu.cc_regfile_reads 6966468810 # number of cc regfile reads -system.cpu.cc_regfile_writes 551975360 # number of cc regfile writes -system.cpu.misc_regfile_reads 675847678 # number of misc regfile reads +system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cc_regfile_reads 6966029517 # number of cc regfile reads +system.cpu.cc_regfile_writes 551971474 # number of cc regfile writes +system.cpu.misc_regfile_reads 675853074 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 14271352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 14271352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4800041 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2156446 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737659 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2176 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38815887 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 38818063 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1395709696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1395779328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2156446 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23967212 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.089975 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.286146 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 21810766 91.00% 91.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 2156446 9.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23967212 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15706134446 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1655247 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25977831897 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 600 # number of replacements -system.cpu.icache.tags.tagsinuse 446.759697 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656842791 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1088 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 603715.800551 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 446.759697 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.872578 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.872578 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313689140 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313689140 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656842791 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656842791 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656842791 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656842791 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656842791 # number of overall hits -system.cpu.icache.overall_hits::total 656842791 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1235 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1235 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1235 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1235 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1235 # number of overall misses -system.cpu.icache.overall_misses::total 1235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31675742 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31675742 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31675742 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31675742 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31675742 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31675742 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656844026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656844026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656844026 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656844026 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656844026 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656844026 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25648.374089 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25648.374089 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25648.374089 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25648.374089 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25648.374089 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25648.374089 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3135 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 123 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.487805 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 147 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 147 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 147 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 147 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 147 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 147 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1088 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1088 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1088 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1088 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1088 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1088 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25912248 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25912248 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25912248 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25912248 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25912248 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25912248 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23816.404412 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23816.404412 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23816.404412 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23816.404412 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23816.404412 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23816.404412 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 15355050 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 500576 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 12135733 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 866797 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 351771 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 1500173 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 5090638 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 5094046 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16133.549273 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 15376042 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5109996 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.009013 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 29446587000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 4939.304770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3.959471 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6800.251946 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 4390.033086 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.301471 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000242 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.415054 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.267946 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.984714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1027 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14923 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 102 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 570 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 346 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 521 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2353 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1208 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9340 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.062683 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.910828 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 356792487 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 356792487 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 832 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 11525794 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11526626 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 4800041 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 4800041 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1796540 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1796540 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 832 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13322334 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13323166 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 832 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13322334 # number of overall hits -system.cpu.l2cache.overall_hits::total 13323166 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 256 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 2744470 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2744726 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 941119 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 941119 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 256 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3685589 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3685845 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 256 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3685589 # number of overall misses -system.cpu.l2cache.overall_misses::total 3685845 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19831249 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 216838606544 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 216858437793 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93637023447 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 93637023447 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19831249 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 310475629991 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 310495461240 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19831249 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 310475629991 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 310495461240 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1088 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 14270264 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 14271352 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 4800041 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 4800041 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737659 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2737659 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1088 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 17007923 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17009011 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1088 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17007923 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17009011 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.235294 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.192321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.192324 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.343768 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.343768 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235294 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.216698 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.216700 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235294 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.216698 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.216700 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77465.816406 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79009.282865 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79009.138906 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 99495.412851 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 99495.412851 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77465.816406 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84240.437550 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84239.967020 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77465.816406 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84240.437550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84239.967020 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 114068 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 3696 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 30.862554 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1672636 # number of writebacks -system.cpu.l2cache.writebacks::total 1672636 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67618 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 67646 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 4482 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 4482 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 72100 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 72128 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 72100 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 72128 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2676852 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2677080 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1500168 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1500168 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 936637 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 936637 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3613489 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3613717 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3613489 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1500168 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5113885 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16681749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 190526161225 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 190542842974 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 108098150766 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 108098150766 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85432139513 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85432139513 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16681749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275958300738 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 275974982487 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16681749 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275958300738 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 108098150766 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 384073133253 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.209559 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.187583 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.187584 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.342131 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.342131 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.209559 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212459 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.212459 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.209559 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212459 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.300657 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73165.565789 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71175.455806 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71175.625298 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72057.363419 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72057.363419 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91211.578779 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91211.578779 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73165.565789 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76368.933388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76368.731278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73165.565789 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76368.933388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72057.363419 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75103.983225 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 17007411 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.965023 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638377840 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17007923 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.534145 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 77012000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.965023 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 17007297 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.963762 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638259274 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17007809 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.527425 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 79888000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.963762 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 449 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 405 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335546211 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335546211 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469430568 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469430568 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168947154 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168947154 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335624835 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335624835 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469463783 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469463783 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168795373 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168795373 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638377722 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638377722 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638377722 # number of overall hits -system.cpu.dcache.overall_hits::total 638377722 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17252405 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17252405 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3638893 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3638893 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638259156 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638259156 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638259156 # number of overall hits +system.cpu.dcache.overall_hits::total 638259156 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17258559 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17258559 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3790674 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3790674 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 20891298 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20891298 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20891300 # number of overall misses -system.cpu.dcache.overall_misses::total 20891300 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 389285003128 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 389285003128 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129453998118 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129453998118 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 384750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 384750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 518739001246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 518739001246 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 518739001246 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 518739001246 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486682973 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486682973 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21049233 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21049233 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21049235 # number of overall misses +system.cpu.dcache.overall_misses::total 21049235 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 392276819281 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 392276819281 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 143202458834 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 143202458834 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 535479278115 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 535479278115 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 535479278115 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 535479278115 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486722342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486722342 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -1080,92 +783,421 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659269020 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659269020 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659269022 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659269022 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035449 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035449 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.021085 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659308389 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659308389 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659308391 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659308391 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035459 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021964 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.021964 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.031689 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.031689 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.031689 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.031689 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22564.100665 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22564.100665 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35575.104329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35575.104329 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 96187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 96187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24830.386376 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24830.386376 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24830.383999 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24830.383999 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20820542 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1650046 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1039120 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 52884 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.036706 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 31.201233 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.031926 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.031926 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.031926 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.031926 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22729.407437 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22729.407437 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37777.571702 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37777.571702 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25439.372452 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25439.372452 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25439.370035 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25439.370035 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19976216 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2938205 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1014245 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 66761 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.695651 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 44.010800 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4800041 # number of writebacks -system.cpu.dcache.writebacks::total 4800041 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2982110 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2982110 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 901266 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 901266 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 4837992 # number of writebacks +system.cpu.dcache.writebacks::total 4837992 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2988204 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2988204 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1053221 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17008888 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1079 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 17007809 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 17008888 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960148 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.195665 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.195723 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359890 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.359890 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960148 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.222098 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.222145 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960148 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.222098 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.222145 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66458.252896 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78493.622318 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 78489.158453 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97416.844097 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97416.844097 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66458.252896 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83429.047042 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83424.393859 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66458.252896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83429.047042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83424.393859 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 69 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 1638491 # number of writebacks +system.cpu.l2cache.writebacks::total 1638491 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43338 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 43338 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3740 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3740 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 47078 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 47078 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 47078 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 47078 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1036 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2748865 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2749901 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993225 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 993225 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981455 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 981455 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1036 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3730320 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3731356 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1036 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3730320 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993225 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4724581 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 59969750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 193568757616 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 193628727366 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 68540364307 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 68540364307 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87429015038 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87429015038 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59969750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 280997772654 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 281057742404 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59969750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 280997772654 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 68540364307 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 349598106711 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192628 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192686 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358524 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358524 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.219377 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.277771 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57885.859073 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70417.702439 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70412.981182 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69007.892781 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89081.022602 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89081.022602 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75323.218263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73995.579018 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 14271401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 14271401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4837992 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1352607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737487 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737487 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38853610 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 38855768 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1398131264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1398200320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1352607 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 23199492 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.058303 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.234316 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 21846885 94.17% 94.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 1352607 5.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 23199492 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15761436995 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1798250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 26002804288 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3738412 # Transaction distribution +system.membus.trans_dist::ReadResp 3738412 # Transaction distribution +system.membus.trans_dist::Writeback 1638491 # Transaction distribution +system.membus.trans_dist::ReadExReq 981933 # Transaction distribution +system.membus.trans_dist::ReadExResp 981933 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11079181 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11079181 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406965504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 406965504 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6358836 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6358836 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6358836 # Request fanout histogram +system.membus.reqLayer0.occupancy 20942586092 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 44003891862 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index fc3ec094e..c26ad4c6d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490000 # Number of ticks simulated final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2048371 # Simulator instruction rate (inst/s) -host_op_rate 2206809 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1103406177 # Simulator tick rate (ticks/s) -host_mem_usage 296712 # Number of bytes of host memory used -host_seconds 754.04 # Real time elapsed on the host +host_inst_rate 1680600 # Simulator instruction rate (inst/s) +host_op_rate 1810592 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 905297170 # Simulator tick rate (ticks/s) +host_mem_usage 301428 # Number of bytes of host memory used +host_seconds 919.05 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1664032433 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 750174605 # Wr system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution -system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution -system.membus.trans_dist::WriteReq 172586047 # Transaction distribution -system.membus.trans_dist::WriteResp 172586047 # Transaction distribution -system.membus.trans_dist::SoftPFReq 1 # Transaction distribution -system.membus.trans_dist::SoftPFResp 1 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution -system.membus.trans_dist::StoreCondReq 61 # Transaction distribution -system.membus.trans_dist::StoreCondResp 61 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram -system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram -system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 2172060894 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032480 # Class of executed instruction +system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution +system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution +system.membus.trans_dist::WriteReq 172586047 # Transaction distribution +system.membus.trans_dist::WriteResp 172586047 # Transaction distribution +system.membus.trans_dist::SoftPFReq 1 # Transaction distribution +system.membus.trans_dist::SoftPFResp 1 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution +system.membus.trans_dist::StoreCondReq 61 # Transaction distribution +system.membus.trans_dist::StoreCondResp 61 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram +system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram +system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 2172060894 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 1aeb45981..89012dc1c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.363671 # Nu sim_ticks 2363670998000 # Number of ticks simulated final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1205605 # Simulator instruction rate (inst/s) -host_op_rate 1299208 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1851916301 # Simulator tick rate (ticks/s) -host_mem_usage 306192 # Number of bytes of host memory used -host_seconds 1276.34 # Real time elapsed on the host +host_inst_rate 1113267 # Simulator instruction rate (inst/s) +host_op_rate 1199701 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1710076181 # Simulator tick rate (ticks/s) +host_mem_usage 309628 # Number of bytes of host memory used +host_seconds 1382.20 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1658228914 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks 27542188 # To system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1177898 # Transaction distribution -system.membus.trans_dist::ReadResp 1177898 # Transaction distribution -system.membus.trans_dist::Writeback 1017198 # Transaction distribution -system.membus.trans_dist::ReadExReq 780876 # Transaction distribution -system.membus.trans_dist::ReadExResp 780876 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2975972 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2975972 # Request fanout histogram -system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -206,6 +214,137 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032480 # Class of executed instruction +system.cpu.dcache.tags.replacements 9111140 # number of replacements +system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits +system.cpu.dcache.overall_hits::total 618379947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses +system.cpu.dcache.overall_misses::total 9115236 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks +system.cpu.dcache.writebacks::total 3697418 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. @@ -438,137 +577,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits -system.cpu.dcache.overall_hits::total 618379947 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses -system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks -system.cpu.dcache.writebacks::total 3697418 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution @@ -602,5 +610,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 957000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1177898 # Transaction distribution +system.membus.trans_dist::ReadResp 1177898 # Transaction distribution +system.membus.trans_dist::Writeback 1017198 # Transaction distribution +system.membus.trans_dist::ReadExReq 780876 # Transaction distribution +system.membus.trans_dist::ReadExResp 780876 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2975972 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2975972 # Request fanout histogram +system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- |