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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-05 20:26:18 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-05 20:26:18 -0500 |
| commit | 381e9191ddcacb78f2f1e72040d9843d43b3461b (patch) | |
| tree | 4916dbc13db6a6823a0f37552fc45918ad4bd89a /tests/long/se/60.bzip2 | |
| parent | 9954eb74df98c4749651eb78098595f78d642105 (diff) | |
| download | gem5-381e9191ddcacb78f2f1e72040d9843d43b3461b.tar.xz | |
stats: x86: update stats missed out on in preivous changeset
Diffstat (limited to 'tests/long/se/60.bzip2')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini | 8 | ||||
| -rw-r--r-- | tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini | 22 |
2 files changed, 19 insertions, 11 deletions
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 48f81d429..5a87f20e3 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -179,11 +180,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index 50782f925..b2f63d5fa 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -92,7 +93,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -103,7 +104,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -143,7 +143,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -154,7 +154,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -210,7 +209,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -221,7 +220,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -240,8 +238,11 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 @@ -295,11 +296,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master |