diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-07-28 01:48:21 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-07-28 01:48:21 -0400 |
| commit | cbf417c71322de6aee0afd9ca11444f935c1cd80 (patch) | |
| tree | d33ad25edec0508ddaeb81a553064adfe0ebbdd0 /tests/long/se/60.bzip2 | |
| parent | 5d0b25ba3f82b6d563b3fabd3de71f3ceabb140d (diff) | |
| download | gem5-cbf417c71322de6aee0afd9ca11444f935c1cd80.tar.xz | |
stats: Bump stats for the regressions using the minor CPU
Updating the stats to match the current behaviour.
Diffstat (limited to 'tests/long/se/60.bzip2')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt | 1169 |
1 files changed, 585 insertions, 584 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 8b5bdef98..fd5fa200e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,533 +1,100 @@ ---------- Begin Simulation Statistics ---------- -final_tick 1183291184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 268503 # Simulator instruction rate (inst/s) -host_mem_usage 248104 # Number of bytes of host memory used -host_op_rate 268503 # Simulator op (including micro ops) rate (op/s) -host_seconds 6802.08 # Real time elapsed on the host -host_tick_rate 173960186 # Simulator tick rate (ticks/s) +sim_seconds 1.181828 # Number of seconds simulated +sim_ticks 1181828044500 # Number of ticks simulated +final_tick 1181828044500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 296156 # Simulator instruction rate (inst/s) +host_op_rate 296156 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191639126 # Simulator tick rate (ticks/s) +host_mem_usage 241048 # Number of bytes of host memory used +host_seconds 6166.95 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated -sim_seconds 1.183291 # Number of seconds simulated -sim_ticks 1183291184500 # Number of ticks simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.726550 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 164028132 # Number of BTB hits -system.cpu.branchPred.BTBLookups 166143892 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 101063 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 15659000 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 184956948 # Number of conditional branches predicted -system.cpu.branchPred.lookups 244507485 # Number of BP lookups -system.cpu.branchPred.usedRAS 18318035 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 1826378509 # Number of instructions committed -system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.cpi 1.295779 # CPI: cycles per instruction -system.cpu.dcache.ReadReq_accesses::cpu.inst 448787942 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 448787942 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24412.387640 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24412.387640 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22378.762178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22378.762178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 441498317 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 441498317 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 177957151250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177957151250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016243 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016243 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 7289625 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289625 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50799 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50799 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 161995965500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 161995965500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016130 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016130 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238826 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238826 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses::cpu.inst 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45036.490101 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45036.490101 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40206.712752 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40206.712752 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 158490258 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158490258 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100802653750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 100802653750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013926 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013926 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 2238244 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238244 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 350933 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 350933 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75882571250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75882571250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887311 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887311 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 609516444 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 609516444 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29257.308743 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29257.308743 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26065.632890 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26065.632890 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 599988575 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 599988575 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 278759805000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 278759805000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.015632 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015632 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 9527869 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9527869 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 401732 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 401732 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237878536750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 237878536750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014973 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014973 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9126137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126137 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 609516444 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 609516444 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29257.308743 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29257.308743 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26065.632890 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26065.632890 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 599988575 # number of overall hits -system.cpu.dcache.overall_hits::total 599988575 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 278759805000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 278759805000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.015632 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015632 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 9527869 # number of overall misses -system.cpu.dcache.overall_misses::total 9527869 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 401732 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 401732 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237878536750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 237878536750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014973 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014973 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9126137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126137 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1591 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2338 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 65.743981 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 1228159025 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.562725 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.996231 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996231 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 9122041 # number of replacements -system.cpu.dcache.tags.sampled_refs 9126137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 1228159025 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4080.562725 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 599988575 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16716397000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 3700613 # number of writebacks -system.cpu.dcache.writebacks::total 3700613 # number of writebacks -system.cpu.discardedOps 50078248 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dtb.data_accesses 620722700 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 614030991 # DTB hits -system.cpu.dtb.data_misses 6691709 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 457660877 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 452677890 # DTB read hits -system.cpu.dtb.read_misses 4982987 # DTB read misses -system.cpu.dtb.write_accesses 163061823 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 161353101 # DTB write hits -system.cpu.dtb.write_misses 1708722 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 592077907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 592077907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74367.693111 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74367.693111 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71956.941545 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71956.941545 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 592076949 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 592076949 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 71244250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 71244250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68934750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 68934750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 592077907 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 592077907 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74367.693111 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74367.693111 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71956.941545 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71956.941545 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 592076949 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 592076949 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 71244250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 71244250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68934750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 68934750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 592077907 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 592077907 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74367.693111 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74367.693111 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71956.941545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71956.941545 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 592076949 # number of overall hits -system.cpu.icache.overall_hits::total 592076949 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 71244250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 71244250 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses -system.cpu.icache.overall_misses::total 958 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68934750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 68934750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 618034.393528 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 1184156772 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 750.687488 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.366547 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.366547 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 1184156772 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 750.687488 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 592076949 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 321001841 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.771737 # IPC: instructions per cycle -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 592077926 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 592077907 # ITB hits -system.cpu.itb.fetch_misses 19 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1887311 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1887311 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80641.484731 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80641.484731 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68018.096944 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68018.096944 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1107870 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107870 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 62855279500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 62855279500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.412990 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.412990 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 779441 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 779441 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53016093500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53016093500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412990 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412990 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779441 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 779441 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7239784 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7239784 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79744.744851 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79744.744851 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67168.011379 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67168.011379 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 6058181 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6058181 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 94226629750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 94226629750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.163210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 1181603 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1181603 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79365923750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79365923750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181603 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1181603 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 3700613 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3700613 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 3700613 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3700613 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 9127095 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9127095 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80101.165119 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80101.165119 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67505.888318 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67505.888318 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 7166051 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7166051 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 157081909250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 157081909250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.214860 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214860 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 1961044 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1961044 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132382017250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 132382017250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214860 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961044 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1961044 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 9127095 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9127095 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80101.165119 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80101.165119 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67505.888318 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67505.888318 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 7166051 # number of overall hits -system.cpu.l2cache.overall_hits::total 7166051 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 157081909250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 157081909250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214860 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214860 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 1961044 # number of overall misses -system.cpu.l2cache.overall_misses::total 1961044 # number of overall misses -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132382017250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 132382017250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214860 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961044 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1961044 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1231 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12870 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15515 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 4.586945 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 106467088 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 14930.905733 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15810.667479 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.455655 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482503 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.938158 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29804 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 1928309 # number of replacements -system.cpu.l2cache.tags.sampled_refs 1958113 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 106467088 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 30741.573213 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8981756 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 88668325250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 1018252 # number of writebacks -system.cpu.l2cache.writebacks::total 1018252 # number of writebacks -system.cpu.numCycles 2366582369 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 2045580528 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 820973312 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952887 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954803 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10114467000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1633750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14012915250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 693804976 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820912000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 820973312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 7239784 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239784 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887311 # Transaction distribution -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 190674944 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940340 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940340 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 11933306500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18491731750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.6 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 161139495 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190674944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190674944 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 1181603 # Transaction distribution -system.membus.trans_dist::ReadResp 1181603 # Transaction distribution -system.membus.trans_dist::Writeback 1018252 # Transaction distribution -system.membus.trans_dist::ReadExReq 779441 # Transaction distribution -system.membus.trans_dist::ReadExResp 779441 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 397171.37 # Average gap between requests -system.physmem.avgMemAccLat 37373.81 # Average memory access latency per DRAM burst -system.physmem.avgQLat 18623.81 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 106.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 106.07 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrBW 55.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 55.07 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 25.40 # Average write queue length when enqueuing -system.physmem.busUtil 1.26 # Data bus utilization in percentage -system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.43 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 51815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 106065876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 106065876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 55073619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106065876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 161139495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 55073619 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 55073619 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 1832587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 104.000528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.206567 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.424181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1451916 79.23% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 263842 14.40% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49021 2.67% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20912 1.14% 97.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12920 0.71% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7284 0.40% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5395 0.29% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4101 0.22% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 17196 0.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1832587 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 125427328 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 125506816 # Total read bytes from the system interface side -system.physmem.bytesReadWrQ 79488 # Total number of bytes read from write queue -system.physmem.bytesWritten 65166528 # Total number of bytes written to DRAM -system.physmem.bytesWrittenSys 65168128 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 125506816 # Number of bytes read from this memory -system.physmem.bytes_read::total 125506816 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 65168128 # Number of bytes written to this memory -system.physmem.bytes_written::total 65168128 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 388135850750 # Time in different power states -system.physmem.memoryStateTime::REF 39512460000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 755636161750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.bytes_read::cpu.inst 125507328 # Number of bytes read from this memory +system.physmem.bytes_read::total 125507328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65168512 # Number of bytes written to this memory +system.physmem.bytes_written::total 65168512 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1961052 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961052 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018258 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018258 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 106197622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 106197622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 51825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 51825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 55142127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 55142127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 55142127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106197622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 161339749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961052 # Number of read requests accepted +system.physmem.writeReqs 1018258 # Number of write requests accepted +system.physmem.readBursts 1961052 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018258 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125425344 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81984 # Total number of bytes read from write queue +system.physmem.bytesWritten 65166912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125507328 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65168512 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1281 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 1961044 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961044 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018252 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018252 # Number of write requests responded to by this memory -system.physmem.pageHitRate 38.46 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 118755 # Per bank write bursts +system.physmem.perBankRdBursts::0 118745 # Per bank write bursts system.physmem.perBankRdBursts::1 114099 # Per bank write bursts -system.physmem.perBankRdBursts::2 116230 # Per bank write bursts -system.physmem.perBankRdBursts::3 117769 # Per bank write bursts -system.physmem.perBankRdBursts::4 117839 # Per bank write bursts -system.physmem.perBankRdBursts::5 117521 # Per bank write bursts -system.physmem.perBankRdBursts::6 119889 # Per bank write bursts -system.physmem.perBankRdBursts::7 124535 # Per bank write bursts -system.physmem.perBankRdBursts::8 126979 # Per bank write bursts -system.physmem.perBankRdBursts::9 130093 # Per bank write bursts -system.physmem.perBankRdBursts::10 128642 # Per bank write bursts +system.physmem.perBankRdBursts::2 116228 # Per bank write bursts +system.physmem.perBankRdBursts::3 117773 # Per bank write bursts +system.physmem.perBankRdBursts::4 117823 # Per bank write bursts +system.physmem.perBankRdBursts::5 117515 # Per bank write bursts +system.physmem.perBankRdBursts::6 119886 # Per bank write bursts +system.physmem.perBankRdBursts::7 124512 # Per bank write bursts +system.physmem.perBankRdBursts::8 126980 # Per bank write bursts +system.physmem.perBankRdBursts::9 130096 # Per bank write bursts +system.physmem.perBankRdBursts::10 128651 # Per bank write bursts system.physmem.perBankRdBursts::11 130358 # Per bank write bursts -system.physmem.perBankRdBursts::12 126048 # Per bank write bursts -system.physmem.perBankRdBursts::13 125260 # Per bank write bursts -system.physmem.perBankRdBursts::14 122592 # Per bank write bursts -system.physmem.perBankRdBursts::15 123193 # Per bank write bursts -system.physmem.perBankWrBursts::0 61221 # Per bank write bursts -system.physmem.perBankWrBursts::1 61486 # Per bank write bursts -system.physmem.perBankWrBursts::2 60571 # Per bank write bursts -system.physmem.perBankWrBursts::3 61239 # Per bank write bursts +system.physmem.perBankRdBursts::12 126070 # Per bank write bursts +system.physmem.perBankRdBursts::13 125261 # Per bank write bursts +system.physmem.perBankRdBursts::14 122591 # Per bank write bursts +system.physmem.perBankRdBursts::15 123183 # Per bank write bursts +system.physmem.perBankWrBursts::0 61220 # Per bank write bursts +system.physmem.perBankWrBursts::1 61482 # Per bank write bursts +system.physmem.perBankWrBursts::2 60570 # Per bank write bursts +system.physmem.perBankWrBursts::3 61238 # Per bank write bursts system.physmem.perBankWrBursts::4 61663 # Per bank write bursts -system.physmem.perBankWrBursts::5 63103 # Per bank write bursts -system.physmem.perBankWrBursts::6 64150 # Per bank write bursts -system.physmem.perBankWrBursts::7 65615 # Per bank write bursts -system.physmem.perBankWrBursts::8 65333 # Per bank write bursts -system.physmem.perBankWrBursts::9 65778 # Per bank write bursts -system.physmem.perBankWrBursts::10 65294 # Per bank write bursts -system.physmem.perBankWrBursts::11 65644 # Per bank write bursts -system.physmem.perBankWrBursts::12 64163 # Per bank write bursts -system.physmem.perBankWrBursts::13 64209 # Per bank write bursts -system.physmem.perBankWrBursts::14 64571 # Per bank write bursts -system.physmem.perBankWrBursts::15 64187 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 59249 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.075495 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 165.201868 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59213 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 8 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59249 # Reads before turning the bus around for writes -system.physmem.rdQLenPdf::0 1833824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 125960 # What read queue length does an incoming req see +system.physmem.perBankWrBursts::5 63102 # Per bank write bursts +system.physmem.perBankWrBursts::6 64153 # Per bank write bursts +system.physmem.perBankWrBursts::7 65613 # Per bank write bursts +system.physmem.perBankWrBursts::8 65334 # Per bank write bursts +system.physmem.perBankWrBursts::9 65779 # Per bank write bursts +system.physmem.perBankWrBursts::10 65298 # Per bank write bursts +system.physmem.perBankWrBursts::11 65646 # Per bank write bursts +system.physmem.perBankWrBursts::12 64168 # Per bank write bursts +system.physmem.perBankWrBursts::13 64213 # Per bank write bursts +system.physmem.perBankWrBursts::14 64569 # Per bank write bursts +system.physmem.perBankWrBursts::15 64185 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1181827934500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1961052 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1018258 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1833401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126352 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -558,37 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 1961044 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961044 # Read request sizes (log2) -system.physmem.readReqs 1961044 # Number of read requests accepted -system.physmem.readRowHitRate 37.25 # Row buffer hit rate for reads -system.physmem.readRowHits 729960 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 1242 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 9799010000 # Total ticks spent in databus transfers -system.physmem.totGap 1183291074500 # Total gap between requests -system.physmem.totMemAccLat 73245258000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 36498970500 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 59249 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.185556 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.149947 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.108422 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 25999 43.88% 43.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1383 2.33% 46.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 27359 46.18% 92.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4006 6.76% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 414 0.70% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 70 0.12% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59249 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -604,31 +140,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 59784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 59755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 59766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59740 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 59781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 59768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 59810 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 59797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 59826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 59953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 59814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 59934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 95 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -653,17 +189,482 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 1018252 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018252 # Write request sizes (log2) -system.physmem.writeReqs 1018252 # Number of write requests accepted -system.physmem.writeRowHitRate 40.80 # Row buffer hit rate for writes -system.physmem.writeRowHits 415473 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.bytesPerActivate::samples 1832736 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.991479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.204587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.379474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1452314 79.24% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 263429 14.37% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49355 2.69% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20877 1.14% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12925 0.71% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7130 0.39% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5386 0.29% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4144 0.23% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17176 0.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1832736 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59244 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.077763 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 162.502392 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59205 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 59244 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59244 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.187108 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.151334 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.111623 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 26003 43.89% 43.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1351 2.28% 46.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 27334 46.14% 92.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4039 6.82% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 439 0.74% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 54 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 18 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 3 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59244 # Writes before turning the bus around for reads +system.physmem.totQLat 36544904000 # Total ticks spent queuing +system.physmem.totMemAccLat 73290610250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798855000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18647.54 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 37397.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 106.13 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 55.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 106.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 55.14 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 1.26 # Data bus utilization in percentage +system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.43 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing +system.physmem.readRowHits 730029 # Number of row buffer hits during reads +system.physmem.writeRowHits 415229 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.78 # Row buffer hit rate for writes +system.physmem.avgGap 396678.40 # Average gap between requests +system.physmem.pageHitRate 38.46 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 386610550250 # Time in different power states +system.physmem.memoryStateTime::REF 39463580000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 755746527250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 161339749 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1181614 # Transaction distribution +system.membus.trans_dist::ReadResp 1181614 # Transaction distribution +system.membus.trans_dist::Writeback 1018258 # Transaction distribution +system.membus.trans_dist::ReadExReq 779438 # Transaction distribution +system.membus.trans_dist::ReadExResp 779438 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940362 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940362 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190675840 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 190675840 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190675840 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11933572000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 18494807500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 244429252 # Number of BP lookups +system.cpu.branchPred.condPredicted 184894637 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15662499 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 166226175 # Number of BTB lookups +system.cpu.branchPred.BTBHits 163968290 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.641679 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18313425 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 99980 # Number of incorrect RAS predictions. +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 452571491 # DTB read hits +system.cpu.dtb.read_misses 4982965 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 457554456 # DTB read accesses +system.cpu.dtb.write_hits 161354418 # DTB write hits +system.cpu.dtb.write_misses 1708765 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 163063183 # DTB write accesses +system.cpu.dtb.data_hits 613925909 # DTB hits +system.cpu.dtb.data_misses 6691730 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 620617639 # DTB accesses +system.cpu.itb.fetch_hits 591482700 # ITB hits +system.cpu.itb.fetch_misses 19 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 591482719 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.numCycles 2363656089 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1826378509 # Number of instructions committed +system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed +system.cpu.discardedOps 49661954 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.294176 # CPI: cycles per instruction +system.cpu.ipc 0.772692 # IPC: instructions per cycle +system.cpu.tickCycles 2043068356 # Number of cycles that the object actually ticked +system.cpu.idleCycles 320587733 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 3 # number of replacements +system.cpu.icache.tags.tagsinuse 750.459785 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 591481743 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 957 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 618058.247649 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 750.459785 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.366435 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.366435 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 873 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1182966357 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1182966357 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 591481743 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 591481743 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 591481743 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 591481743 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 591481743 # number of overall hits +system.cpu.icache.overall_hits::total 591481743 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses +system.cpu.icache.overall_misses::total 957 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 70550250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 70550250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 70550250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 70550250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 70550250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 70550250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 591482700 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 591482700 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 591482700 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 591482700 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 591482700 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 591482700 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73720.219436 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73720.219436 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73720.219436 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73720.219436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73720.219436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73720.219436 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 957 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 957 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 957 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 957 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68248750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 68248750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68248750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 68248750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68248750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 68248750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71315.308255 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71315.308255 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71315.308255 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71315.308255 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71315.308255 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71315.308255 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 694662629 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7239687 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239687 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700672 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887325 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952782 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954696 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820910528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 820971776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 820971776 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10114514000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1629250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14012964250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 1928316 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30739.409036 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8981710 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1958121 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.586902 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 88667368250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14930.422883 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 15808.986154 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455640 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482452 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.938092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29805 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1232 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12869 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15516 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 106466918 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106466918 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 6058073 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6058073 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3700672 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700672 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1107887 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1107887 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7165960 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7165960 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7165960 # number of overall hits +system.cpu.l2cache.overall_hits::total 7165960 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1181614 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1181614 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 779438 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 779438 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1961052 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1961052 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1961052 # number of overall misses +system.cpu.l2cache.overall_misses::total 1961052 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 94264990000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94264990000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 62866370000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 62866370000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 157131360000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 157131360000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 157131360000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 157131360000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7239687 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7239687 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3700672 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3700672 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1887325 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1887325 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 9127012 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9127012 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9127012 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9127012 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.163213 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163213 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.412986 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.412986 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.214862 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214862 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214862 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214862 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79776.466765 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79776.466765 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.023956 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.023956 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80126.054791 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80126.054791 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80126.054791 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80126.054791 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 1018258 # number of writebacks +system.cpu.l2cache.writebacks::total 1018258 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181614 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1181614 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779438 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 779438 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961052 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961052 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961052 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1961052 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79403793000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79403793000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53024408000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53024408000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132428201000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 132428201000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132428201000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 132428201000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163213 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163213 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412986 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412986 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214862 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214862 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214862 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214862 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67199.434841 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67199.434841 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68029.026042 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68029.026042 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67529.163429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67529.163429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67529.163429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67529.163429 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 9121959 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.549274 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 599881153 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126055 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.732801 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16715078000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.549274 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.996228 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996228 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1621 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2308 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 64 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1227943655 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1227943655 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 441390753 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 441390753 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 158490400 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158490400 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 599881153 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 599881153 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 599881153 # number of overall hits +system.cpu.dcache.overall_hits::total 599881153 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7289545 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289545 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2238102 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2238102 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9527647 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9527647 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9527647 # number of overall misses +system.cpu.dcache.overall_misses::total 9527647 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 177999429500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177999429500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100859304250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 100859304250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 278858733750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 278858733750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 278858733750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 278858733750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 448680298 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 448680298 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 609408800 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 609408800 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 609408800 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 609408800 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016247 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016247 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013925 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013925 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.015634 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015634 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.015634 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015634 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24418.455404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24418.455404 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45064.659363 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45064.659363 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29268.373792 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29268.373792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29268.373792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29268.373792 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3700672 # number of writebacks +system.cpu.dcache.writebacks::total 3700672 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50815 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50815 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 350777 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 350777 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 401592 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 401592 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 401592 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 401592 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238730 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238730 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887325 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887325 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9126055 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126055 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9126055 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126055 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162033829750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 162033829750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75893768500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 75893768500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237927598250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 237927598250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237927598250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 237927598250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016133 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016133 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014975 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014975 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014975 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014975 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22384.289751 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22384.289751 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40212.347370 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40212.347370 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26071.243078 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26071.243078 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26071.243078 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26071.243078 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |