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authorNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
commit9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch)
tree64b85031cb791a21af6059778384d358d992b817 /tests/long/se/60.bzip2
parentdbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff)
downloadgem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/long/se/60.bzip2')
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini57
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt27
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini57
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt27
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini21
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini68
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout12
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt210
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini37
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout10
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt27
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini34
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini87
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout10
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt226
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini10
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout4
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini27
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout4
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt210
27 files changed, 629 insertions, 598 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
index 8009459e0..65c82eda1 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,18 +31,13 @@ system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
@@ -57,17 +53,9 @@ dtb=system.cpu.dtb
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -76,11 +64,11 @@ memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
@@ -88,6 +76,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -95,21 +101,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -126,21 +127,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -163,21 +159,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -204,7 +195,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
index 43339a0ee..de1a8f5c6 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 12:40:49
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:29:25
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index 7470c11aa..2c8c2e903 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.985090 # Nu
sim_ticks 985089830500 # Number of ticks simulated
final_tick 985089830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109003 # Simulator instruction rate (inst/s)
-host_op_rate 109003 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59005665 # Simulator tick rate (ticks/s)
-host_mem_usage 485696 # Number of bytes of host memory used
-host_seconds 16694.83 # Real time elapsed on the host
+host_inst_rate 87940 # Simulator instruction rate (inst/s)
+host_op_rate 87940 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47603973 # Simulator tick rate (ticks/s)
+host_mem_usage 516412 # Number of bytes of host memory used
+host_seconds 20693.44 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
@@ -192,6 +192,15 @@ system.physmem.writeRowHits 194113 # Nu
system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes
system.physmem.avgGap 330817.71 # Average gap between requests
+system.cpu.branchPred.lookups 326556831 # Number of BP lookups
+system.cpu.branchPred.condPredicted 252596788 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 138232865 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 218937552 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 135479530 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 61.880444 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -228,14 +237,6 @@ system.cpu.workload.num_syscalls 29 # Nu
system.cpu.numCycles 1970179662 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 326556831 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 252596788 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 138232865 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 218937552 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 135479530 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 61.880444 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 172296521 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 154260310 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 1667620352 # Number of Reads from Int. Register File
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index fb395fc71..6fb7253a6 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -56,7 +53,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -116,6 +103,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -125,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -132,21 +138,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -426,21 +427,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -463,21 +459,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -504,7 +495,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 78436c89b..0d9d55e31 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 12:41:35
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:57:42
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index c867780d0..c63a4e0f8 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.655920 # Nu
sim_ticks 655919824500 # Number of ticks simulated
final_tick 655919824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 137989 # Simulator instruction rate (inst/s)
-host_op_rate 137989 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 52135439 # Simulator tick rate (ticks/s)
-host_mem_usage 496344 # Number of bytes of host memory used
-host_seconds 12581.07 # Real time elapsed on the host
+host_inst_rate 111017 # Simulator instruction rate (inst/s)
+host_op_rate 111017 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41944886 # Simulator tick rate (ticks/s)
+host_mem_usage 517560 # Number of bytes of host memory used
+host_seconds 15637.66 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory
@@ -192,6 +192,15 @@ system.physmem.writeRowHits 193886 # Nu
system.physmem.readRowHitRate 42.77 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 19.01 # Row buffer hit rate for writes
system.physmem.avgGap 219646.04 # Average gap between requests
+system.cpu.branchPred.lookups 381024003 # Number of BP lookups
+system.cpu.branchPred.condPredicted 296029232 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 16079219 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 261934224 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 259237388 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 98.970415 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 24703724 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3041 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -228,14 +237,6 @@ system.cpu.workload.num_syscalls 29 # Nu
system.cpu.numCycles 1311839650 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 381024003 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 296029232 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 16079219 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 261934224 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 259237388 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 24703724 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 3041 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 402148068 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 3157560086 # Number of instructions fetch has processed
system.cpu.fetch.Branches 381024003 # Number of branches that fetch encountered
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index 16083f416..fd8132952 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,17 +44,18 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -82,7 +88,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
@@ -99,14 +105,15 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
index 88b1b065e..0658af7d4 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 14:21:33
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:47:45
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index cdd816836..4f12f01d2 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu
sim_ticks 913189263000 # Number of ticks simulated
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3414010 # Simulator instruction rate (inst/s)
-host_op_rate 3414010 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1713194291 # Simulator tick rate (ticks/s)
-host_mem_usage 206032 # Number of bytes of host memory used
-host_seconds 533.03 # Real time elapsed on the host
+host_inst_rate 2288605 # Simulator instruction rate (inst/s)
+host_op_rate 2288605 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1148451794 # Simulator tick rate (ticks/s)
+host_mem_usage 263992 # Number of bytes of host memory used
+host_seconds 795.15 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index c5fc5fd4c..ea6dff7f2 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -41,15 +43,16 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,21 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -90,21 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -113,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -120,23 +120,20 @@ size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -145,10 +142,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -158,12 +155,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
@@ -181,13 +178,14 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 2743afc35..167c61e46 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 10:19:14
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:15:18
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@@ -23,4 +25,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2642007987000 because target called exit()
+Exiting @ tick 2623386226000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 3a71ce0c3..56da2f7b0 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu
sim_ticks 2623386226000 # Number of ticks simulated
final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1789114 # Simulator instruction rate (inst/s)
-host_op_rate 1789114 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2579177735 # Simulator tick rate (ticks/s)
-host_mem_usage 217052 # Number of bytes of host memory used
-host_seconds 1017.14 # Real time elapsed on the host
+host_inst_rate 1056521 # Simulator instruction rate (inst/s)
+host_op_rate 1056521 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1523075909 # Simulator tick rate (ticks/s)
+host_mem_usage 272444 # Number of bytes of host memory used
+host_seconds 1722.43 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
@@ -167,106 +167,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 9107638 # number of replacements
-system.cpu.dcache.tagsinuse 4079.262869 # Cycle average of tags in use
-system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.995914 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits
-system.cpu.dcache.overall_hits::total 596212431 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
-system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143374726000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143374726000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377180000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 57377180000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200751906000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200751906000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200751906000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200751906000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19851.358009 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19851.358009 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30369.222789 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30369.222789 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22032.239528 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22032.239528 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks
-system.cpu.dcache.writebacks::total 3693497 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128929898000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 128929898000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53598540000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 53598540000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182528438000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 182528438000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182528438000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 182528438000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17851.358009 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17851.358009 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28369.222789 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28369.222789 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1926937 # number of replacements
system.cpu.l2cache.tagsinuse 30535.257456 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8959453 # Total number of references to valid blocks.
@@ -402,5 +302,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9107638 # number of replacements
+system.cpu.dcache.tagsinuse 4079.262869 # Cycle average of tags in use
+system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.995914 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits
+system.cpu.dcache.overall_hits::total 596212431 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
+system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 143374726000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 143374726000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377180000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 57377180000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 200751906000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 200751906000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 200751906000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 200751906000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19851.358009 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19851.358009 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30369.222789 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30369.222789 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22032.239528 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22032.239528 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks
+system.cpu.dcache.writebacks::total 3693497 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128929898000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 128929898000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53598540000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 53598540000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182528438000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 182528438000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182528438000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 182528438000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17851.358009 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17851.358009 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28369.222789 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28369.222789 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 9dd6f437e..b3f283cca 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -522,7 +527,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index 0fb886b0f..fa5d435db 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 5 2013 00:51:58
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:12:52
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -24,4 +26,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 506577346000 because target called exit()
+Exiting @ tick 506353996500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index dd9ca10a0..fe1996e1b 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.506354 # Nu
sim_ticks 506353996500 # Number of ticks simulated
final_tick 506353996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 136322 # Simulator instruction rate (inst/s)
-host_op_rate 152077 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44690362 # Simulator tick rate (ticks/s)
-host_mem_usage 507940 # Number of bytes of host memory used
-host_seconds 11330.27 # Real time elapsed on the host
+host_inst_rate 105319 # Simulator instruction rate (inst/s)
+host_op_rate 117491 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 34526611 # Simulator tick rate (ticks/s)
+host_mem_usage 552892 # Number of bytes of host memory used
+host_seconds 14665.62 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1723073835 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory
@@ -192,6 +192,15 @@ system.physmem.writeRowHits 189005 # Nu
system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 17.17 # Row buffer hit rate for writes
system.physmem.avgGap 151240.81 # Average gap between requests
+system.cpu.branchPred.lookups 301930111 # Number of BP lookups
+system.cpu.branchPred.condPredicted 248173247 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 15201095 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 171785530 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 160276899 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 93.300582 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 17551988 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -238,14 +247,6 @@ system.cpu.workload.num_syscalls 46 # Nu
system.cpu.numCycles 1012707994 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 301930111 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 248173247 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 15201095 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 171785530 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 160276899 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 17551988 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 296178013 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2176838116 # Number of instructions fetch has processed
system.cpu.fetch.Branches 301930111 # Number of branches that fetch encountered
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index b82b134f8..c0c32553c 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -68,7 +71,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@@ -76,6 +79,23 @@ port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -84,7 +104,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@@ -100,7 +120,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
@@ -124,7 +144,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
index 06746d191..ad5616590 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:26:56
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:13:46
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index 3e4545cce..bf810ed1c 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu
sim_ticks 861538200000 # Number of ticks simulated
final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2426875 # Simulator instruction rate (inst/s)
-host_op_rate 2707358 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1353681051 # Simulator tick rate (ticks/s)
-host_mem_usage 219056 # Number of bytes of host memory used
-host_seconds 636.44 # Real time elapsed on the host
+host_inst_rate 1602478 # Simulator instruction rate (inst/s)
+host_op_rate 1787682 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 893842215 # Simulator tick rate (ticks/s)
+host_mem_usage 278712 # Number of bytes of host memory used
+host_seconds 963.86 # Real time elapsed on the host
sim_insts 1544563041 # Number of instructions simulated
sim_ops 1723073853 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index a32ea8ea4..15930e421 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,23 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -91,7 +89,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -101,23 +99,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -126,6 +119,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -134,7 +144,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -142,25 +152,20 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -169,10 +174,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -187,7 +192,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
@@ -211,7 +216,7 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
index 92d2da7b2..f67b33f3c 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:53:48
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:25:52
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -24,4 +26,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2409361491000 because target called exit()
+Exiting @ tick 2391205115000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 6ff1664e3..8d9905464 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu
sim_ticks 2391205115000 # Number of ticks simulated
final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1213159 # Simulator instruction rate (inst/s)
-host_op_rate 1353897 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1885227488 # Simulator tick rate (ticks/s)
-host_mem_usage 231376 # Number of bytes of host memory used
-host_seconds 1268.39 # Real time elapsed on the host
+host_inst_rate 809589 # Simulator instruction rate (inst/s)
+host_op_rate 903509 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1258086461 # Simulator tick rate (ticks/s)
+host_mem_usage 287292 # Number of bytes of host memory used
+host_seconds 1900.67 # Real time elapsed on the host
sim_insts 1538759601 # Number of instructions simulated
sim_ops 1717270334 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
@@ -177,114 +177,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 9111140 # number of replacements
-system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use
-system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits
-system.cpu.dcache.overall_hits::total 645854937 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
-system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks
-system.cpu.dcache.writebacks::total 3697418 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1926075 # number of replacements
system.cpu.l2cache.tagsinuse 30987.094489 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8967572 # Total number of references to valid blocks.
@@ -423,5 +315,113 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9111140 # number of replacements
+system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use
+system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits
+system.cpu.dcache.overall_hits::total 645854937 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
+system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks
+system.cpu.dcache.writebacks::total 3697418 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 3e10b88db..e5390bdb7 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -15,6 +15,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -83,6 +86,9 @@ int_master=system.membus.slave[5]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
index f8f83dcd3..2b9587722 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atom
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:35:30
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 17:13:04
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 15cf58882..b864f8ff9 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu
sim_ticks 2846007227000 # Number of ticks simulated
final_tick 2846007227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1003542 # Simulator instruction rate (inst/s)
-host_op_rate 1563610 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 949472024 # Simulator tick rate (ticks/s)
-host_mem_usage 267592 # Number of bytes of host memory used
-host_seconds 2997.46 # Real time elapsed on the host
+host_inst_rate 1019064 # Simulator instruction rate (inst/s)
+host_op_rate 1587794 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 964157561 # Simulator tick rate (ticks/s)
+host_mem_usage 283172 # Number of bytes of host memory used
+host_seconds 2951.81 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index 514c208bd..55b9fc1a9 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -63,21 +66,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -102,21 +100,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -133,6 +126,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
@@ -152,21 +148,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index e7934dc80..b6532688b 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:38:11
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:35:45
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index 8918bba84..790f1ac3e 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu
sim_ticks 5882580525000 # Number of ticks simulated
final_tick 5882580525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 506721 # Simulator instruction rate (inst/s)
-host_op_rate 789517 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 990939541 # Simulator tick rate (ticks/s)
-host_mem_usage 276172 # Number of bytes of host memory used
-host_seconds 5936.37 # Real time elapsed on the host
+host_inst_rate 639726 # Simulator instruction rate (inst/s)
+host_op_rate 996751 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1251043124 # Simulator tick rate (ticks/s)
+host_mem_usage 291744 # Number of bytes of host memory used
+host_seconds 4702.14 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
@@ -135,106 +135,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 9108581 # number of replacements
-system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1668600406 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 58853921000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1668600406 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1668600406 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1668600406 # number of overall hits
-system.cpu.dcache.overall_hits::total 1668600406 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
-system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1677713083 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1677713083 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1677713083 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1677713083 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency
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-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1926197 # number of replacements
system.cpu.l2cache.tagsinuse 31136.249384 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks.
@@ -370,5 +270,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------