diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/60.bzip2 | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/60.bzip2')
8 files changed, 3017 insertions, 2990 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index fd5fa200e..8e313893e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.181828 # Number of seconds simulated -sim_ticks 1181828044500 # Number of ticks simulated -final_tick 1181828044500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.181972 # Number of seconds simulated +sim_ticks 1181971516500 # Number of ticks simulated +final_tick 1181971516500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 296156 # Simulator instruction rate (inst/s) -host_op_rate 296156 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 191639126 # Simulator tick rate (ticks/s) -host_mem_usage 241048 # Number of bytes of host memory used -host_seconds 6166.95 # Real time elapsed on the host +host_inst_rate 316302 # Simulator instruction rate (inst/s) +host_op_rate 316302 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 204699977 # Simulator tick rate (ticks/s) +host_mem_usage 267460 # Number of bytes of host memory used +host_seconds 5774.17 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 125507328 # Number of bytes read from this memory -system.physmem.bytes_read::total 125507328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65168512 # Number of bytes written to this memory -system.physmem.bytes_written::total 65168512 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1961052 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961052 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018258 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018258 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106197622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 106197622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 51825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 55142127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 55142127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 55142127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106197622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 161339749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961052 # Number of read requests accepted -system.physmem.writeReqs 1018258 # Number of write requests accepted -system.physmem.readBursts 1961052 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1018258 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125425344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 81984 # Total number of bytes read from write queue -system.physmem.bytesWritten 65166912 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125507328 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65168512 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1281 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 125504768 # Number of bytes read from this memory +system.physmem.bytes_read::total 125504768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65167040 # Number of bytes written to this memory +system.physmem.bytes_written::total 65167040 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1961012 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961012 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018235 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018235 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 106182566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 106182566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 51873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 51873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 55134188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 55134188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 55134188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106182566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 161316754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961012 # Number of read requests accepted +system.physmem.writeReqs 1018235 # Number of write requests accepted +system.physmem.readBursts 1961012 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018235 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125424512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 80256 # Total number of bytes read from write queue +system.physmem.bytesWritten 65165696 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125504768 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65167040 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1254 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118745 # Per bank write bursts -system.physmem.perBankRdBursts::1 114099 # Per bank write bursts -system.physmem.perBankRdBursts::2 116228 # Per bank write bursts -system.physmem.perBankRdBursts::3 117773 # Per bank write bursts -system.physmem.perBankRdBursts::4 117823 # Per bank write bursts -system.physmem.perBankRdBursts::5 117515 # Per bank write bursts +system.physmem.perBankRdBursts::0 118750 # Per bank write bursts +system.physmem.perBankRdBursts::1 114103 # Per bank write bursts +system.physmem.perBankRdBursts::2 116233 # Per bank write bursts +system.physmem.perBankRdBursts::3 117780 # Per bank write bursts +system.physmem.perBankRdBursts::4 117833 # Per bank write bursts +system.physmem.perBankRdBursts::5 117521 # Per bank write bursts system.physmem.perBankRdBursts::6 119886 # Per bank write bursts -system.physmem.perBankRdBursts::7 124512 # Per bank write bursts -system.physmem.perBankRdBursts::8 126980 # Per bank write bursts -system.physmem.perBankRdBursts::9 130096 # Per bank write bursts -system.physmem.perBankRdBursts::10 128651 # Per bank write bursts -system.physmem.perBankRdBursts::11 130358 # Per bank write bursts -system.physmem.perBankRdBursts::12 126070 # Per bank write bursts -system.physmem.perBankRdBursts::13 125261 # Per bank write bursts -system.physmem.perBankRdBursts::14 122591 # Per bank write bursts -system.physmem.perBankRdBursts::15 123183 # Per bank write bursts -system.physmem.perBankWrBursts::0 61220 # Per bank write bursts -system.physmem.perBankWrBursts::1 61482 # Per bank write bursts -system.physmem.perBankWrBursts::2 60570 # Per bank write bursts -system.physmem.perBankWrBursts::3 61238 # Per bank write bursts -system.physmem.perBankWrBursts::4 61663 # Per bank write bursts -system.physmem.perBankWrBursts::5 63102 # Per bank write bursts -system.physmem.perBankWrBursts::6 64153 # Per bank write bursts -system.physmem.perBankWrBursts::7 65613 # Per bank write bursts -system.physmem.perBankWrBursts::8 65334 # Per bank write bursts -system.physmem.perBankWrBursts::9 65779 # Per bank write bursts -system.physmem.perBankWrBursts::10 65298 # Per bank write bursts -system.physmem.perBankWrBursts::11 65646 # Per bank write bursts -system.physmem.perBankWrBursts::12 64168 # Per bank write bursts -system.physmem.perBankWrBursts::13 64213 # Per bank write bursts -system.physmem.perBankWrBursts::14 64569 # Per bank write bursts -system.physmem.perBankWrBursts::15 64185 # Per bank write bursts +system.physmem.perBankRdBursts::7 124520 # Per bank write bursts +system.physmem.perBankRdBursts::8 126974 # Per bank write bursts +system.physmem.perBankRdBursts::9 130087 # Per bank write bursts +system.physmem.perBankRdBursts::10 128649 # Per bank write bursts +system.physmem.perBankRdBursts::11 130350 # Per bank write bursts +system.physmem.perBankRdBursts::12 126060 # Per bank write bursts +system.physmem.perBankRdBursts::13 125237 # Per bank write bursts +system.physmem.perBankRdBursts::14 122580 # Per bank write bursts +system.physmem.perBankRdBursts::15 123195 # Per bank write bursts +system.physmem.perBankWrBursts::0 61223 # Per bank write bursts +system.physmem.perBankWrBursts::1 61486 # Per bank write bursts +system.physmem.perBankWrBursts::2 60566 # Per bank write bursts +system.physmem.perBankWrBursts::3 61239 # Per bank write bursts +system.physmem.perBankWrBursts::4 61662 # Per bank write bursts +system.physmem.perBankWrBursts::5 63100 # Per bank write bursts +system.physmem.perBankWrBursts::6 64151 # Per bank write bursts +system.physmem.perBankWrBursts::7 65612 # Per bank write bursts +system.physmem.perBankWrBursts::8 65333 # Per bank write bursts +system.physmem.perBankWrBursts::9 65776 # Per bank write bursts +system.physmem.perBankWrBursts::10 65296 # Per bank write bursts +system.physmem.perBankWrBursts::11 65642 # Per bank write bursts +system.physmem.perBankWrBursts::12 64167 # Per bank write bursts +system.physmem.perBankWrBursts::13 64207 # Per bank write bursts +system.physmem.perBankWrBursts::14 64568 # Per bank write bursts +system.physmem.perBankWrBursts::15 64186 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1181827934500 # Total gap between requests +system.physmem.totGap 1181971406500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961052 # Read request sizes (log2) +system.physmem.readPktSize::6 1961012 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018258 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1833401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126352 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1018235 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1833489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126251 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,28 +140,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 59766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 59740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 59810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 59797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 59814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 59934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 59765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 59783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 59794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 59834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 59898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -189,27 +189,27 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1832736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.991479 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.204587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.379474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1452314 79.24% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 263429 14.37% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49355 2.69% 96.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20877 1.14% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12925 0.71% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7130 0.39% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5386 0.29% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4144 0.23% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 17176 0.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1832736 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.077763 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 162.502392 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59205 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1832879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.982912 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.202772 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.375131 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1452262 79.23% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 263657 14.38% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49315 2.69% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20815 1.14% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12975 0.71% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7226 0.39% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5262 0.29% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4170 0.23% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17197 0.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1832879 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59235 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.083110 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 163.258366 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59198 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 10 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes @@ -217,96 +217,94 @@ system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # R system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59244 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59244 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.187108 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.151334 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.111623 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 26003 43.89% 43.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1351 2.28% 46.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 27334 46.14% 92.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4039 6.82% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 439 0.74% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 54 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 59235 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59235 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.189398 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.153834 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.107502 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 25894 43.71% 43.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1328 2.24% 45.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 27547 46.50% 92.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3948 6.66% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 431 0.73% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 64 0.11% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 18 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59244 # Writes before turning the bus around for reads -system.physmem.totQLat 36544904000 # Total ticks spent queuing -system.physmem.totMemAccLat 73290610250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18647.54 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::23 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59235 # Writes before turning the bus around for reads +system.physmem.totQLat 36544529000 # Total ticks spent queuing +system.physmem.totMemAccLat 73289991500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798790000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18647.47 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37397.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 106.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 55.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 106.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 55.14 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37397.47 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 106.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 55.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 106.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 55.13 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.26 # Data bus utilization in percentage system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.43 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing -system.physmem.readRowHits 730029 # Number of row buffer hits during reads -system.physmem.writeRowHits 415229 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.78 # Average write queue length when enqueuing +system.physmem.readRowHits 729927 # Number of row buffer hits during reads +system.physmem.writeRowHits 415160 # Number of row buffer hits during writes system.physmem.readRowHitRate 37.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.78 # Row buffer hit rate for writes -system.physmem.avgGap 396678.40 # Average gap between requests -system.physmem.pageHitRate 38.46 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 386610550250 # Time in different power states -system.physmem.memoryStateTime::REF 39463580000 # Time in different power states +system.physmem.writeRowHitRate 40.77 # Row buffer hit rate for writes +system.physmem.avgGap 396734.95 # Average gap between requests +system.physmem.pageHitRate 38.45 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 385912942500 # Time in different power states +system.physmem.memoryStateTime::REF 39468520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 755746527250 # Time in different power states +system.physmem.memoryStateTime::ACT 756587133750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 161339749 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1181614 # Transaction distribution -system.membus.trans_dist::ReadResp 1181614 # Transaction distribution -system.membus.trans_dist::Writeback 1018258 # Transaction distribution -system.membus.trans_dist::ReadExReq 779438 # Transaction distribution -system.membus.trans_dist::ReadExResp 779438 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940362 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940362 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190675840 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190675840 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190675840 # Total data (bytes) +system.membus.throughput 161316754 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1181581 # Transaction distribution +system.membus.trans_dist::ReadResp 1181581 # Transaction distribution +system.membus.trans_dist::Writeback 1018235 # Transaction distribution +system.membus.trans_dist::ReadExReq 779431 # Transaction distribution +system.membus.trans_dist::ReadExResp 779431 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940259 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940259 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190671808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 190671808 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190671808 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11933572000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11933364500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18494807500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18494109500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 244429252 # Number of BP lookups -system.cpu.branchPred.condPredicted 184894637 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15662499 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 166226175 # Number of BTB lookups -system.cpu.branchPred.BTBHits 163968290 # Number of BTB hits +system.cpu.branchPred.lookups 244428250 # Number of BP lookups +system.cpu.branchPred.condPredicted 184893435 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15662948 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 166307436 # Number of BTB lookups +system.cpu.branchPred.BTBHits 163975175 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.641679 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18313425 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 99980 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.597621 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18313183 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 99860 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452571491 # DTB read hits -system.cpu.dtb.read_misses 4982965 # DTB read misses +system.cpu.dtb.read_hits 452570396 # DTB read hits +system.cpu.dtb.read_misses 4982513 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457554456 # DTB read accesses -system.cpu.dtb.write_hits 161354418 # DTB write hits -system.cpu.dtb.write_misses 1708765 # DTB write misses +system.cpu.dtb.read_accesses 457552909 # DTB read accesses +system.cpu.dtb.write_hits 161353452 # DTB write hits +system.cpu.dtb.write_misses 1708793 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163063183 # DTB write accesses -system.cpu.dtb.data_hits 613925909 # DTB hits -system.cpu.dtb.data_misses 6691730 # DTB misses +system.cpu.dtb.write_accesses 163062245 # DTB write accesses +system.cpu.dtb.data_hits 613923848 # DTB hits +system.cpu.dtb.data_misses 6691306 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620617639 # DTB accesses -system.cpu.itb.fetch_hits 591482700 # ITB hits +system.cpu.dtb.data_accesses 620615154 # DTB accesses +system.cpu.itb.fetch_hits 591487986 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 591482719 # ITB accesses +system.cpu.itb.fetch_accesses 591488005 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -320,68 +318,68 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2363656089 # number of cpu cycles simulated +system.cpu.numCycles 2363943033 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 49661954 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 49642925 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.294176 # CPI: cycles per instruction -system.cpu.ipc 0.772692 # IPC: instructions per cycle -system.cpu.tickCycles 2043068356 # Number of cycles that the object actually ticked -system.cpu.idleCycles 320587733 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.294334 # CPI: cycles per instruction +system.cpu.ipc 0.772598 # IPC: instructions per cycle +system.cpu.tickCycles 2043545366 # Number of cycles that the object actually ticked +system.cpu.idleCycles 320397667 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 750.459785 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 591481743 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 957 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 618058.247649 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 750.580892 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 591487028 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 617418.609603 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 750.459785 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.366435 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.366435 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 750.580892 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.366495 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.366495 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 873 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1182966357 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1182966357 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 591481743 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 591481743 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 591481743 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 591481743 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 591481743 # number of overall hits -system.cpu.icache.overall_hits::total 591481743 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses -system.cpu.icache.overall_misses::total 957 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 70550250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 70550250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 70550250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 70550250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 70550250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 70550250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 591482700 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 591482700 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 591482700 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 591482700 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 591482700 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 591482700 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1182976930 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1182976930 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 591487028 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 591487028 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 591487028 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 591487028 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 591487028 # number of overall hits +system.cpu.icache.overall_hits::total 591487028 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses +system.cpu.icache.overall_misses::total 958 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 69768750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 69768750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 69768750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69768750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 69768750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69768750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 591487986 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 591487986 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 591487986 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 591487986 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 591487986 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 591487986 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73720.219436 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73720.219436 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73720.219436 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73720.219436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73720.219436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73720.219436 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72827.505219 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72827.505219 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72827.505219 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72827.505219 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72827.505219 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72827.505219 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,62 +388,62 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 957 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 957 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 957 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 957 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68248750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 68248750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68248750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 68248750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68248750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 68248750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67467250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 67467250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67467250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 67467250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67467250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 67467250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71315.308255 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71315.308255 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71315.308255 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71315.308255 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71315.308255 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71315.308255 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70425.104384 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70425.104384 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70425.104384 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70425.104384 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70425.104384 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70425.104384 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 694662629 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7239687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700672 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887325 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952782 # 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Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887316 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952725 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954641 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820906816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 820968128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 820968128 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # 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Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1928276 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30739.606267 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8981702 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1958081 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.586992 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 88667368250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14930.422883 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15808.986154 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.455640 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482452 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.938092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14931.057799 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 15808.548467 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455660 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482439 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.938098 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29805 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -453,60 +451,60 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1232 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12869 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15516 # 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miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79776.466765 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79776.466765 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.023956 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.023956 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80126.054791 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80126.054791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80126.054791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80126.054791 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 106466413 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106466413 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 6058117 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163209 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412984 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412984 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214858 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214858 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214858 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214858 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67195.924147 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67195.924147 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68035.351109 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68035.351109 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67529.565857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67529.565857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67529.565857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67529.565857 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9121959 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.549274 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 599881153 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126055 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.732801 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 9121960 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.551150 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 599880175 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126056 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.732686 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 16715078000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.549274 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.551150 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.996228 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.996228 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1621 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2308 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1617 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2312 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 64 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1227943655 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1227943655 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 441390753 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 441390753 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 158490400 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158490400 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 599881153 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 599881153 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 599881153 # number of overall hits -system.cpu.dcache.overall_hits::total 599881153 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7289545 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289545 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2238102 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238102 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9527647 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9527647 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9527647 # number of overall misses -system.cpu.dcache.overall_misses::total 9527647 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 177999429500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177999429500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100859304250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 100859304250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 278858733750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 278858733750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 278858733750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 278858733750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 448680298 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 448680298 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1227941810 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1227941810 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 441389836 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 441389836 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 158490339 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158490339 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 599880175 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 599880175 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 599880175 # number of overall hits +system.cpu.dcache.overall_hits::total 599880175 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7289539 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289539 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2238163 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2238163 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9527702 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9527702 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9527702 # number of overall misses +system.cpu.dcache.overall_misses::total 9527702 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 177992802750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177992802750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100871241750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 100871241750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 278864044500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 278864044500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 278864044500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 278864044500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 448679375 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 448679375 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 609408800 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 609408800 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 609408800 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 609408800 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 609407877 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 609407877 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 609407877 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 609407877 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016247 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016247 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013925 # miss rate for WriteReq accesses @@ -607,14 +605,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.015634 system.cpu.dcache.demand_miss_rate::total 0.015634 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.015634 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015634 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24418.455404 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24418.455404 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45064.659363 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45064.659363 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29268.373792 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29268.373792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29268.373792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29268.373792 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24417.566426 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24417.566426 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45068.764764 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45068.764764 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29268.762237 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29268.762237 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29268.762237 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29268.762237 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -623,32 +621,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700672 # number of writebacks -system.cpu.dcache.writebacks::total 3700672 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50815 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50815 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 350777 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 350777 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 401592 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 401592 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 401592 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 401592 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238730 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238730 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887325 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887325 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9126055 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126055 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9126055 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126055 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162033829750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 162033829750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75893768500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75893768500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237927598250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 237927598250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237927598250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 237927598250 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3700613 # number of writebacks +system.cpu.dcache.writebacks::total 3700613 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50799 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50799 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 350847 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 350847 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 401646 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 401646 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 401646 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 401646 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238740 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238740 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887316 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887316 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9126056 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126056 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9126056 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126056 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162027926000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 162027926000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75898088250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 75898088250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237926014250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 237926014250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237926014250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 237926014250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016133 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016133 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses @@ -657,14 +655,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014975 system.cpu.dcache.demand_mshr_miss_rate::total 0.014975 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014975 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014975 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22384.289751 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22384.289751 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40212.347370 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40212.347370 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26071.243078 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26071.243078 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26071.243078 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26071.243078 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22383.443251 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22383.443251 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40214.827962 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40214.827962 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26071.066652 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26071.066652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26071.066652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26071.066652 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index a090e3fd8..87bb9f534 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.679350 # Number of seconds simulated -sim_ticks 679349778000 # Number of ticks simulated -final_tick 679349778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.661836 # Number of seconds simulated +sim_ticks 661835607000 # Number of ticks simulated +final_tick 661835607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176355 # Simulator instruction rate (inst/s) -host_op_rate 176355 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69011357 # Simulator tick rate (ticks/s) -host_mem_usage 223060 # Number of bytes of host memory used -host_seconds 9844.03 # Real time elapsed on the host +host_inst_rate 129941 # Simulator instruction rate (inst/s) +host_op_rate 129941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49537566 # Simulator tick rate (ticks/s) +host_mem_usage 237180 # Number of bytes of host memory used +host_seconds 13360.28 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125814720 # Number of bytes read from this memory -system.physmem.bytes_read::total 125876544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65265856 # Number of bytes written to this memory -system.physmem.bytes_written::total 65265856 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965855 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966821 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019779 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019779 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 91005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 185198736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 185289740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 91005 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91005 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96071064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96071064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96071064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 91005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 185198736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 281360804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966821 # Number of read requests accepted -system.physmem.writeReqs 1019779 # Number of write requests accepted -system.physmem.readBursts 1966821 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1019779 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125795136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 81408 # Total number of bytes read from write queue -system.physmem.bytesWritten 65264000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125876544 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65265856 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1272 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125980800 # Number of bytes read from this memory +system.physmem.bytes_read::total 126042752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65306880 # Number of bytes written to this memory +system.physmem.bytes_written::total 65306880 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1968450 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1969418 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1020420 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1020420 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93606 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 190350593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 190444199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93606 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93606 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98675380 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98675380 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98675380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 190350593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 289119579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1969418 # Number of read requests accepted +system.physmem.writeReqs 1020420 # Number of write requests accepted +system.physmem.readBursts 1969418 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1020420 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125960256 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 82496 # Total number of bytes read from write queue +system.physmem.bytesWritten 65304896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126042752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65306880 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1289 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118990 # Per bank write bursts -system.physmem.perBankRdBursts::1 114401 # Per bank write bursts -system.physmem.perBankRdBursts::2 116526 # Per bank write bursts -system.physmem.perBankRdBursts::3 118038 # Per bank write bursts -system.physmem.perBankRdBursts::4 118100 # Per bank write bursts -system.physmem.perBankRdBursts::5 117781 # Per bank write bursts -system.physmem.perBankRdBursts::6 120191 # Per bank write bursts -system.physmem.perBankRdBursts::7 124916 # Per bank write bursts -system.physmem.perBankRdBursts::8 127523 # Per bank write bursts -system.physmem.perBankRdBursts::9 130444 # Per bank write bursts -system.physmem.perBankRdBursts::10 129055 # Per bank write bursts -system.physmem.perBankRdBursts::11 130769 # Per bank write bursts -system.physmem.perBankRdBursts::12 126629 # Per bank write bursts -system.physmem.perBankRdBursts::13 125625 # Per bank write bursts -system.physmem.perBankRdBursts::14 122929 # Per bank write bursts -system.physmem.perBankRdBursts::15 123632 # Per bank write bursts -system.physmem.perBankWrBursts::0 61276 # Per bank write bursts -system.physmem.perBankWrBursts::1 61573 # Per bank write bursts -system.physmem.perBankWrBursts::2 60655 # Per bank write bursts -system.physmem.perBankWrBursts::3 61329 # Per bank write bursts -system.physmem.perBankWrBursts::4 61751 # Per bank write bursts -system.physmem.perBankWrBursts::5 63183 # Per bank write bursts -system.physmem.perBankWrBursts::6 64216 # Per bank write bursts -system.physmem.perBankWrBursts::7 65714 # Per bank write bursts -system.physmem.perBankWrBursts::8 65484 # Per bank write bursts -system.physmem.perBankWrBursts::9 65866 # Per bank write bursts -system.physmem.perBankWrBursts::10 65407 # Per bank write bursts -system.physmem.perBankWrBursts::11 65735 # Per bank write bursts -system.physmem.perBankWrBursts::12 64310 # Per bank write bursts -system.physmem.perBankWrBursts::13 64307 # Per bank write bursts -system.physmem.perBankWrBursts::14 64646 # Per bank write bursts -system.physmem.perBankWrBursts::15 64298 # Per bank write bursts +system.physmem.perBankRdBursts::0 119133 # Per bank write bursts +system.physmem.perBankRdBursts::1 114512 # Per bank write bursts +system.physmem.perBankRdBursts::2 116620 # Per bank write bursts +system.physmem.perBankRdBursts::3 118156 # Per bank write bursts +system.physmem.perBankRdBursts::4 118267 # Per bank write bursts +system.physmem.perBankRdBursts::5 117901 # Per bank write bursts +system.physmem.perBankRdBursts::6 120342 # Per bank write bursts +system.physmem.perBankRdBursts::7 125056 # Per bank write bursts +system.physmem.perBankRdBursts::8 127675 # Per bank write bursts +system.physmem.perBankRdBursts::9 130585 # Per bank write bursts +system.physmem.perBankRdBursts::10 129305 # Per bank write bursts +system.physmem.perBankRdBursts::11 130922 # Per bank write bursts +system.physmem.perBankRdBursts::12 126863 # Per bank write bursts +system.physmem.perBankRdBursts::13 125867 # Per bank write bursts +system.physmem.perBankRdBursts::14 123079 # Per bank write bursts +system.physmem.perBankRdBursts::15 123846 # Per bank write bursts +system.physmem.perBankWrBursts::0 61299 # Per bank write bursts +system.physmem.perBankWrBursts::1 61588 # Per bank write bursts +system.physmem.perBankWrBursts::2 60677 # Per bank write bursts +system.physmem.perBankWrBursts::3 61353 # Per bank write bursts +system.physmem.perBankWrBursts::4 61807 # Per bank write bursts +system.physmem.perBankWrBursts::5 63207 # Per bank write bursts +system.physmem.perBankWrBursts::6 64256 # Per bank write bursts +system.physmem.perBankWrBursts::7 65745 # Per bank write bursts +system.physmem.perBankWrBursts::8 65527 # Per bank write bursts +system.physmem.perBankWrBursts::9 65905 # Per bank write bursts +system.physmem.perBankWrBursts::10 65467 # Per bank write bursts +system.physmem.perBankWrBursts::11 65774 # Per bank write bursts +system.physmem.perBankWrBursts::12 64405 # Per bank write bursts +system.physmem.perBankWrBursts::13 64356 # Per bank write bursts +system.physmem.perBankWrBursts::14 64678 # Per bank write bursts +system.physmem.perBankWrBursts::15 64345 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 679349688500 # Total gap between requests +system.physmem.totGap 661835517500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1966821 # Read request sizes (log2) +system.physmem.readPktSize::6 1969418 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1019779 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1643770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 225726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 72200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1020420 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1619695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 248396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 75753 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,39 +144,39 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 29643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 50000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 63137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 63948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 60448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 27847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 29428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 63276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 64246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 60589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see @@ -193,125 +193,132 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1771721 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.836103 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.953832 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 137.029832 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1375665 77.65% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 272762 15.40% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53440 3.02% 96.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21316 1.20% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12827 0.72% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6576 0.37% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5044 0.28% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3861 0.22% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20230 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1771721 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59588 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.942421 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 164.012858 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59550 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 13 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1772142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.926701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.988600 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 137.225720 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1375537 77.62% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 272696 15.39% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53852 3.04% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21473 1.21% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12850 0.73% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6581 0.37% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4855 0.27% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3761 0.21% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20537 1.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1772142 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59644 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.954195 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 163.722438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59607 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 6 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59588 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59588 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.113345 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.071670 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.230173 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 30977 51.99% 51.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 27509 46.17% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 1030 1.73% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 43 0.07% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 11 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-77 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59588 # Writes before turning the bus around for reads -system.physmem.totQLat 40014194750 # Total ticks spent queuing -system.physmem.totMemAccLat 76868238500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9827745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20357.77 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59644 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59644 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.107991 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.066184 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.220335 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29768 49.91% 49.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1416 2.37% 52.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 22411 37.57% 89.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4939 8.28% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 872 1.46% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 162 0.27% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 31 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 10 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 3 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59644 # Writes before turning the bus around for reads +system.physmem.totQLat 40394853000 # Total ticks spent queuing +system.physmem.totMemAccLat 77297271750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9840645000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20524.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39107.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 185.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 96.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 185.29 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 96.07 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39274.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 190.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 98.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 190.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 98.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.20 # Data bus utilization in percentage -system.physmem.busUtilRead 1.45 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.15 # Average write queue length when enqueuing -system.physmem.readRowHits 795833 # Number of row buffer hits during reads -system.physmem.writeRowHits 417735 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.49 # Row buffer hit rate for reads +system.physmem.busUtil 2.26 # Data bus utilization in percentage +system.physmem.busUtilRead 1.49 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.77 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.96 # Average write queue length when enqueuing +system.physmem.readRowHits 798370 # Number of row buffer hits during reads +system.physmem.writeRowHits 417997 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.56 # Row buffer hit rate for reads system.physmem.writeRowHitRate 40.96 # Row buffer hit rate for writes -system.physmem.avgGap 227465.91 # Average gap between requests -system.physmem.pageHitRate 40.65 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 134374460000 # Time in different power states -system.physmem.memoryStateTime::REF 22684740000 # Time in different power states +system.physmem.avgGap 221361.66 # Average gap between requests +system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 126237669000 # Time in different power states +system.physmem.memoryStateTime::REF 22100000000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 522286376500 # Time in different power states +system.physmem.memoryStateTime::ACT 513493900500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 281360804 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191893 # Transaction distribution -system.membus.trans_dist::ReadResp 1191893 # Transaction distribution -system.membus.trans_dist::Writeback 1019779 # Transaction distribution -system.membus.trans_dist::ReadExReq 774928 # Transaction distribution -system.membus.trans_dist::ReadExResp 774928 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4953421 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4953421 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191142400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191142400 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191142400 # Total data (bytes) +system.membus.throughput 289119579 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1198182 # Transaction distribution +system.membus.trans_dist::ReadResp 1198182 # Transaction distribution +system.membus.trans_dist::Writeback 1020420 # Transaction distribution +system.membus.trans_dist::ReadExReq 771236 # Transaction distribution +system.membus.trans_dist::ReadExResp 771236 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4959256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4959256 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191349632 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 191349632 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191349632 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11809306000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18437139750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 11823202500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 18425039000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 390516660 # Number of BP lookups -system.cpu.branchPred.condPredicted 303583970 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16113462 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 268537122 # Number of BTB lookups -system.cpu.branchPred.BTBHits 266026822 # Number of BTB hits +system.cpu.branchPred.lookups 410520712 # Number of BP lookups +system.cpu.branchPred.condPredicted 318849760 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16265290 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 282927738 # Number of BTB lookups +system.cpu.branchPred.BTBHits 279343276 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.065194 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25282995 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3069 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.733082 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26370791 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 621222786 # DTB read hits -system.cpu.dtb.read_misses 11503040 # DTB read misses +system.cpu.dtb.read_hits 646139057 # DTB read hits +system.cpu.dtb.read_misses 12159875 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 632725826 # DTB read accesses -system.cpu.dtb.write_hits 213831979 # DTB write hits -system.cpu.dtb.write_misses 7254265 # DTB write misses +system.cpu.dtb.read_accesses 658298932 # DTB read accesses +system.cpu.dtb.write_hits 218185834 # DTB write hits +system.cpu.dtb.write_misses 7515423 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 221086244 # DTB write accesses -system.cpu.dtb.data_hits 835054765 # DTB hits -system.cpu.dtb.data_misses 18757305 # DTB misses +system.cpu.dtb.write_accesses 225701257 # DTB write accesses +system.cpu.dtb.data_hits 864324891 # DTB hits +system.cpu.dtb.data_misses 19675298 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 853812070 # DTB accesses -system.cpu.itb.fetch_hits 400046189 # ITB hits +system.cpu.dtb.data_accesses 884000189 # DTB accesses +system.cpu.itb.fetch_hits 422443679 # ITB hits system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 400046233 # ITB accesses +system.cpu.itb.fetch_accesses 422443723 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -325,239 +332,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1358699557 # number of cpu cycles simulated +system.cpu.numCycles 1323671215 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 410929991 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3243314345 # Number of instructions fetch has processed -system.cpu.fetch.Branches 390516660 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 291309817 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 589336372 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 147340013 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133548447 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 141 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1456 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 400046189 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9025513 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1257254668 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.579680 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.173136 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 433730630 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3419498139 # Number of instructions fetch has processed +system.cpu.fetch.Branches 410520712 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 305714067 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 866879802 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45990094 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 88 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1786 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 422443679 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8426079 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1323607404 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.583469 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.158025 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 667918296 53.13% 53.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 44267394 3.52% 56.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22207289 1.77% 58.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40636739 3.23% 61.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 131869370 10.49% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 62966774 5.01% 77.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40227274 3.20% 80.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28245094 2.25% 82.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 218916438 17.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 696600974 52.63% 52.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48023746 3.63% 56.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24394821 1.84% 58.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45250405 3.42% 61.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142990505 10.80% 72.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 66206181 5.00% 77.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43787822 3.31% 80.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29609921 2.24% 82.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226743029 17.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1257254668 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.287419 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.387072 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 430550615 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 129659255 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 568815009 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4792365 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 123437424 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 59500767 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 1323607404 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310138 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.583344 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 355560821 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 384357689 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 525784970 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34909729 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22994195 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62281773 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 917 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3153748807 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2128 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 123437424 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 446386402 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61779163 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6860 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 557518816 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 68126003 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3069486898 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1505727 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6123879 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 54202488 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 8466199 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2295837862 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3983545178 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3983398130 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 147047 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 3264096854 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2212 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22994195 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 373922324 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 204910686 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7734 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 538718918 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 183053547 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3181111000 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1787853 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18972686 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 140245391 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27858899 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2377395421 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4126748897 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4126578364 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 170532 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 919634899 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 203 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 202 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 44876150 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 692163471 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 260495859 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 73383628 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 38808502 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2780183806 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 184 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2536585762 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4364880 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1034533664 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 460650584 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 155 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1257254668 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.017559 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.009997 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1001192458 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 212 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99259627 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 719210617 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272896274 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90779805 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 59022559 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2889836484 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 194 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2624050349 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1575226 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1139401909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 505657216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 165 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1323607404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.982499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.151238 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 428157011 34.05% 34.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 188380197 14.98% 49.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 177998596 14.16% 63.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153960413 12.25% 75.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 135215337 10.75% 86.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80818226 6.43% 92.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 69593138 5.54% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17238172 1.37% 99.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5893578 0.47% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 519394281 39.24% 39.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169344121 12.79% 52.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158328435 11.96% 64.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149155945 11.27% 75.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126186051 9.53% 84.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84451720 6.38% 91.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68205907 5.15% 96.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33984275 2.57% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14556669 1.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1257254668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1323607404 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2760636 13.79% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12853797 64.19% 77.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4410220 22.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13175247 35.70% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19116655 51.79% 87.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4618094 12.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1663143410 65.57% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 259 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 21 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 647516942 25.53% 91.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 225924828 8.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1719340504 65.52% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 109 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896937 0.03% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 170 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 672950109 25.65% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230862442 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2536585762 # Type of FU issued -system.cpu.iq.rate 1.866922 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20024653 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007894 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6352883505 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3813585390 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2440929650 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1932220 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1252073 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 864209 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2555655812 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 954603 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64558247 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2624050349 # Type of FU issued +system.cpu.iq.rate 1.982403 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36909996 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014066 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6608212970 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4028086926 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2521962769 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1980354 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1298007 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 893087 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2659977012 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 983333 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69535121 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 247567808 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 343004 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 121628 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 99767357 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 274614954 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 379465 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 148696 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 112167772 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1607198 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 269 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6022963 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 123437424 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22713536 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 8297734 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2923674181 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8955846 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 692163471 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 260495859 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 184 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 449856 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8304684 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 121628 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10428435 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8597760 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19026195 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2492121408 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 632726353 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 44464354 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22994195 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 147722049 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18412868 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3041056525 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6683505 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 719210617 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272896274 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 194 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 821771 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17859213 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 148696 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10896298 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8844115 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19740413 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2578377980 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 658298938 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45672369 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 143490191 # number of nop insts executed -system.cpu.iew.exec_refs 853812632 # number of memory reference insts executed -system.cpu.iew.exec_branches 304222027 # Number of branches executed -system.cpu.iew.exec_stores 221086279 # Number of stores executed -system.cpu.iew.exec_rate 1.834196 # Inst execution rate -system.cpu.iew.wb_sent 2470047897 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2441793859 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1422096892 # num instructions producing a value -system.cpu.iew.wb_consumers 1830175974 # num instructions consuming a value +system.cpu.iew.exec_nop 151219847 # number of nop insts executed +system.cpu.iew.exec_refs 884000267 # number of memory reference insts executed +system.cpu.iew.exec_branches 315975248 # Number of branches executed +system.cpu.iew.exec_stores 225701329 # Number of stores executed +system.cpu.iew.exec_rate 1.947899 # Inst execution rate +system.cpu.iew.wb_sent 2552852780 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2522855856 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1489309006 # num instructions producing a value +system.cpu.iew.wb_consumers 1920624303 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.797155 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.777027 # average fanout of values written-back +system.cpu.iew.wb_rate 1.905954 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775430 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 873443731 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1005196168 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16112643 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1133817244 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.605003 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.541695 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16264438 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1184721059 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.536041 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.558766 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 625261340 55.15% 55.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 171314027 15.11% 70.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86268180 7.61% 77.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54871559 4.84% 82.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 31288205 2.76% 85.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20767631 1.83% 87.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 23576751 2.08% 89.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22892827 2.02% 91.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 97576724 8.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 695617998 58.72% 58.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159800446 13.49% 72.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79745623 6.73% 78.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52150996 4.40% 83.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28466079 2.40% 85.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19402088 1.64% 87.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20010452 1.69% 89.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23121038 1.95% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106406339 8.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1133817244 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1184721059 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,10 +575,10 @@ system.cpu.commit.fp_insts 805525 # Nu system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1130719227 62.13% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 75 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 166 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction @@ -603,224 +609,225 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 97576724 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106406339 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3643685177 # The number of ROB reads -system.cpu.rob.rob_writes 5509997541 # The number of ROB writes -system.cpu.timesIdled 1119552 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 101444889 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3817511814 # The number of ROB reads +system.cpu.rob.rob_writes 5788973646 # The number of ROB writes +system.cpu.timesIdled 715 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 63811 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.782641 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.782641 # CPI: Total CPI of All Threads -system.cpu.ipc 1.277725 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.277725 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3354502670 # number of integer regfile reads -system.cpu.int_regfile_writes 1955490145 # number of integer regfile writes -system.cpu.fp_regfile_reads 31250 # number of floating regfile reads -system.cpu.fp_regfile_writes 519 # number of floating regfile writes +system.cpu.cpi 0.762464 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.762464 # CPI: Total CPI of All Threads +system.cpu.ipc 1.311537 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.311537 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3467668910 # number of integer regfile reads +system.cpu.int_regfile_writes 2022324472 # number of integer regfile writes +system.cpu.fp_regfile_reads 45289 # number of floating regfile reads +system.cpu.fp_regfile_writes 607 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1216162152 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7299986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7299986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3725797 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1883584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1883584 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1932 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22091005 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22092937 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826137664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 826199488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 826199488 # Total data (bytes) +system.cpu.toL2Bus.throughput 1252958492 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7335196 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7335196 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3742782 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879093 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879093 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22169424 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22171360 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829190592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 829252544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 829252544 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10180553427 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10221470348 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1609000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1613250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14076007750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14118250749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 775.530288 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 400044658 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 966 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 414124.904762 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 769.518205 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 422442162 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 968 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 436407.192149 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 775.530288 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.378677 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.378677 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 769.518205 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.375741 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.375741 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 967 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 912 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 800093342 # Number of tag accesses -system.cpu.icache.tags.data_accesses 800093342 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 400044658 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 400044658 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 400044658 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 400044658 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 400044658 # number of overall hits -system.cpu.icache.overall_hits::total 400044658 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1530 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1530 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1530 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1530 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1530 # number of overall misses -system.cpu.icache.overall_misses::total 1530 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 107584749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 107584749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 107584749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 107584749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 107584749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 107584749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 400046188 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 400046188 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 400046188 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 400046188 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 400046188 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 400046188 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 900 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.472168 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 844888324 # Number of tag accesses +system.cpu.icache.tags.data_accesses 844888324 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 422442162 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 422442162 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 422442162 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 422442162 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 422442162 # number of overall hits +system.cpu.icache.overall_hits::total 422442162 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1516 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1516 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1516 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1516 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1516 # number of overall misses +system.cpu.icache.overall_misses::total 1516 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 105797750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 105797750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 105797750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 105797750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 105797750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 105797750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 422443678 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 422443678 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 422443678 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 422443678 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 422443678 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 422443678 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70316.829412 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70316.829412 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70316.829412 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70316.829412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70316.829412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70316.829412 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 293 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69787.434037 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69787.434037 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69787.434037 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69787.434037 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69787.434037 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69787.434037 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 455 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48.833333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 564 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 564 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 564 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 564 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 564 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 564 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73366499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 73366499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73366499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 73366499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73366499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 73366499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 548 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59385750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137754062750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 137813448500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163163 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163273 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163237 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163347 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410430 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410430 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214085 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214167 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213653 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.213735 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214085 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214167 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62353.519669 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69647.107463 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69641.196190 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69998.648259 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69998.648259 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62353.519669 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69785.682692 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69782.032401 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62353.519669 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69785.682692 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69782.032401 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213653 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.213735 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61348.915289 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69978.951758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69971.979632 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69984.131965 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69984.131965 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61348.915289 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69980.981356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69976.738559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61348.915289 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69980.981356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69976.738559 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9178508 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.552800 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 699314315 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9182604 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 76.156427 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5143328250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.552800 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997938 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997938 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9209225 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.405523 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 713868953 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9213321 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.482262 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5101114000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.405523 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997902 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997902 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 755 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2929 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 735 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2949 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1441348176 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1441348176 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 543788004 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 543788004 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155526308 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155526308 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 699314312 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 699314312 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 699314312 # number of overall hits -system.cpu.dcache.overall_hits::total 699314312 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11566276 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11566276 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5202194 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5202194 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 1472872785 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1472872785 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 558354793 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 558354793 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155514155 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155514155 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 713868948 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 713868948 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 713868948 # number of overall hits +system.cpu.dcache.overall_hits::total 713868948 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12746431 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12746431 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5214347 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5214347 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16768470 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16768470 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16768470 # number of overall misses -system.cpu.dcache.overall_misses::total 16768470 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 334833749250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 334833749250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 287624135124 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 287624135124 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 69500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 69500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 622457884374 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 622457884374 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 622457884374 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 622457884374 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 555354280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 555354280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17960778 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17960778 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17960778 # number of overall misses +system.cpu.dcache.overall_misses::total 17960778 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 384137632000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 384137632000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 288800427104 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 288800427104 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 70500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 70500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 672938059104 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 672938059104 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 672938059104 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 672938059104 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 571101224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 571101224 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 716082782 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 716082782 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 716082782 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 716082782 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020827 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020827 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032366 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032366 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023417 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023417 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023417 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023417 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28949.140523 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28949.140523 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55289.005970 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55289.005970 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37120.732206 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37120.732206 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37120.732206 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37120.732206 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11998793 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8384809 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 779484 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65137 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.393251 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 128.725747 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 731829726 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731829726 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731829726 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731829726 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032442 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032442 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024542 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024542 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024542 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024542 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30136.877688 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30136.877688 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55385.732308 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55385.732308 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37467.088514 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37467.088514 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37467.088514 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37467.088514 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14080620 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8619116 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1054999 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67267 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.346572 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 128.132903 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725797 # number of writebacks -system.cpu.dcache.writebacks::total 3725797 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4267247 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4267247 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3318620 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3318620 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7585867 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7585867 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7585867 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7585867 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7299029 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7299029 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883574 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883574 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3742782 # number of writebacks +system.cpu.dcache.writebacks::total 3742782 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5412183 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5412183 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3335275 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3335275 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8747458 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8747458 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8747458 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8747458 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334248 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7334248 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879072 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879072 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9182603 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9182603 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9182603 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9182603 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 167129067750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 167129067750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77336919371 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77336919371 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 67500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 67500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244465987121 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 244465987121 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244465987121 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 244465987121 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013143 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013143 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012823 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012823 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012823 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012823 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22897.438515 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22897.438515 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41058.604213 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41058.604213 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 67500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26622.732914 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26622.732914 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26622.732914 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26622.732914 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 9213320 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9213320 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9213320 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9213320 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168546702500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168546702500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77098541067 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77098541067 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 68500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 68500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245645243567 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245645243567 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245645243567 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245645243567 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22980.774921 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22980.774921 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41030.115433 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41030.115433 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 68500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 68500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26661.968060 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26661.968060 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26661.968060 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26661.968060 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index f3e627477..f3667e9fd 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2693565 # Simulator instruction rate (inst/s) -host_op_rate 2693565 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1351665756 # Simulator tick rate (ticks/s) -host_mem_usage 256712 # Number of bytes of host memory used -host_seconds 675.60 # Real time elapsed on the host +host_inst_rate 3321406 # Simulator instruction rate (inst/s) +host_op_rate 3321406 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1666724755 # Simulator tick rate (ticks/s) +host_mem_usage 255644 # Number of bytes of host memory used +host_seconds 547.89 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -96,10 +96,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction -system.cpu.op_class::IntAlu 1130719228 61.91% 66.50% # Class of executed instruction -system.cpu.op_class::IntMult 75 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatAdd 166 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction +system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction +system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 2ba96be4b..07eca3cb9 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu sim_ticks 2623386226000 # Number of ticks simulated final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1099630 # Simulator instruction rate (inst/s) -host_op_rate 1099630 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1585220760 # Simulator tick rate (ticks/s) -host_mem_usage 265440 # Number of bytes of host memory used -host_seconds 1654.90 # Real time elapsed on the host +host_inst_rate 1619868 # Simulator instruction rate (inst/s) +host_op_rate 1619868 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2335193556 # Simulator tick rate (ticks/s) +host_mem_usage 265412 # Number of bytes of host memory used +host_seconds 1123.41 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -110,10 +110,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction -system.cpu.op_class::IntAlu 1130719228 61.91% 66.50% # Class of executed instruction -system.cpu.op_class::IntMult 75 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatAdd 166 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction +system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction +system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 7b16ef532..d103f16e9 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,599 +1,101 @@ ---------- Begin Simulation Statistics ---------- -final_tick 1134079016500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 227824 # Simulator instruction rate (inst/s) -host_mem_usage 293824 # Number of bytes of host memory used -host_op_rate 254155 # Simulator op (including micro ops) rate (op/s) -host_seconds 6779.62 # Real time elapsed on the host -host_tick_rate 167277674 # Simulator tick rate (ticks/s) +sim_seconds 1.095875 # Number of seconds simulated +sim_ticks 1095875470500 # Number of ticks simulated +final_tick 1095875470500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 232088 # Simulator instruction rate (inst/s) +host_op_rate 250040 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 164667871 # Simulator tick rate (ticks/s) +host_mem_usage 318056 # Number of bytes of host memory used +host_seconds 6655.07 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated -sim_ops 1723073900 # Number of ops (including micro ops) simulated -sim_seconds 1.134079 # Number of seconds simulated -sim_ticks 1134079016500 # Number of ticks simulated +sim_ops 1664032480 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.938151 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 122192107 # Number of BTB hits -system.cpu.branchPred.BTBLookups 138952327 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 14597136 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 197361074 # Number of conditional branches predicted -system.cpu.branchPred.lookups 250285818 # Number of BP lookups -system.cpu.branchPred.usedRAS 13226889 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 1544563087 # Number of instructions committed -system.cpu.committedOps 1723073900 # Number of ops (including micro ops) committed -system.cpu.cpi 1.468479 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 485955700 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 485955700 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24973.063686 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24973.063686 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22917.493937 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22917.493937 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 478618690 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 478618690 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183227617996 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183227617996 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015098 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015098 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 7337010 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7337010 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 222 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168140794504 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168140794504 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015098 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015098 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7336788 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7336788 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45215.138055 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45215.138055 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40855.687627 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40855.687627 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 170348428 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170348428 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101174252000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 101174252000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012965 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012965 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 2237619 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2237619 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 346681 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 346681 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77255572250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77255572250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890938 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890938 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 658541747 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 658541747 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29703.696091 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29703.696091 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26593.373790 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26593.373790 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 648967118 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 648967118 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 284401869996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 284401869996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.014539 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014539 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 9574629 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9574629 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 346903 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 346903 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245396366754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245396366754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014012 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014012 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9227726 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9227726 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 658541747 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 658541747 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29703.696091 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29703.696091 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26593.373790 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26593.373790 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 648967118 # number of overall hits -system.cpu.dcache.overall_hits::total 648967118 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 284401869996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 284401869996 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.014539 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014539 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 9574629 # number of overall misses -system.cpu.dcache.overall_misses::total 9574629 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 346903 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 346903 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245396366754 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245396366754 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9227726 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9227726 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1280 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2489 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 70.327970 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 1326311464 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.294010 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997386 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997386 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 9223630 # number of replacements -system.cpu.dcache.tags.sampled_refs 9227726 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 1326311464 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4085.294010 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 648967240 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 10338720250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 3700800 # number of writebacks -system.cpu.dcache.writebacks::total 3700800 # number of writebacks -system.cpu.discardedOps 51251418 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 468616075 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 468616075 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71218.824455 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71218.824455 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68823.548426 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68823.548426 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 468615249 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 468615249 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58826749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58826749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 826 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 826 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56848251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 56848251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 826 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 826 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 468616075 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 468616075 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71218.824455 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71218.824455 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68823.548426 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68823.548426 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 468615249 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 468615249 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 58826749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58826749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 826 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 826 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56848251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 56848251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 826 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 826 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 468616075 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 468616075 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71218.824455 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71218.824455 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68823.548426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68823.548426 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 468615249 # number of overall hits -system.cpu.icache.overall_hits::total 468615249 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 58826749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58826749 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 826 # number of overall misses -system.cpu.icache.overall_misses::total 826 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56848251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 56848251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 826 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 826 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 760 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 567330.809927 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 937232976 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 667.306532 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.325833 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.325833 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.sampled_refs 826 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 937232976 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 667.306532 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 468615249 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 378561103 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.680977 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890938 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1890938 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80530.523230 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80530.523230 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67904.363586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67904.363586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090908 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1090908 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64426834500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 64426834500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423086 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.423086 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 800030 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 800030 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54325528000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54325528000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423086 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423086 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800030 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 800030 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7337614 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7337614 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79650.729800 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79650.729800 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67079.515524 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67079.515524 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 6081653 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6081653 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100038210250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 100038210250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171167 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.171167 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 1255961 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1255961 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84248920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84248920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171167 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171167 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255956 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1255956 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 3700800 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3700800 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 3700800 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3700800 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 9228552 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9228552 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79993.076210 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79993.076210 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67400.482299 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67400.482299 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 7172561 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7172561 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 164465044750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 164465044750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222786 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.222786 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 2055991 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2055991 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138574448000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138574448000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222785 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.222785 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055986 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2055986 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 9228552 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9228552 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79993.076210 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79993.076210 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67400.482299 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67400.482299 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 7172561 # number of overall hits -system.cpu.l2cache.overall_hits::total 7172561 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 164465044750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 164465044750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222786 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.222786 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 2055991 # number of overall misses -system.cpu.l2cache.overall_misses::total 2055991 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138574448000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138574448000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222785 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.222785 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055986 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2055986 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1208 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12891 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15554 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 4.376215 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 107378812 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 14921.737919 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 16303.939645 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.455375 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.497557 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.952932 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 2023282 # number of replacements -system.cpu.l2cache.tags.sampled_refs 2053058 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 107378812 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 31225.677564 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8984623 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 62285743250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 1046478 # number of writebacks -system.cpu.l2cache.writebacks::total 1046478 # number of writebacks -system.cpu.numCycles 2268158033 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 1889596930 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 827478528 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22157904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10165476000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1402249 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14183973746 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 729648037 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827425664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 827478528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 7337614 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7337614 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890938 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890938 # Transaction distribution -system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 198557696 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158450 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5158450 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 12256366000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 19378736500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.7 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 175082770 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198557696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 198557696 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 1255956 # Transaction distribution -system.membus.trans_dist::ReadResp 1255956 # Transaction distribution -system.membus.trans_dist::Writeback 1046478 # Transaction distribution -system.membus.trans_dist::ReadExReq 800030 # Transaction distribution -system.membus.trans_dist::ReadExResp 800030 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 365541.37 # Average gap between requests -system.physmem.avgMemAccLat 37274.24 # Average memory access latency per DRAM burst -system.physmem.avgQLat 18524.24 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 115.95 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.03 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrBW 59.05 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 59.06 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing -system.physmem.busUtil 1.37 # Data bus utilization in percentage -system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 44808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 44808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 116026399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116026399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 59056372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 116026399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 175082770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 59056372 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 59056372 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 1917061 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.528140 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.739842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.452866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1492586 77.86% 77.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305285 15.92% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52052 2.72% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21496 1.12% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13307 0.69% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7031 0.37% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5522 0.29% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4121 0.21% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15661 0.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1917061 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 131498944 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 131583104 # Total read bytes from the system interface side -system.physmem.bytesReadWrQ 84160 # Total number of bytes read from write queue -system.physmem.bytesWritten 66972672 # Total number of bytes written to DRAM -system.physmem.bytesWrittenSys 66974592 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 50816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50816 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 131583104 # Number of bytes read from this memory -system.physmem.bytes_read::total 131583104 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 66974592 # Number of bytes written to this memory -system.physmem.bytes_written::total 66974592 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 321867794250 # Time in different power states -system.physmem.memoryStateTime::REF 37869260000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 774338779750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.bytes_read::cpu.inst 131539072 # Number of bytes read from this memory +system.physmem.bytes_read::total 131539072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66963456 # Number of bytes written to this memory +system.physmem.bytes_written::total 66963456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2055298 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2055298 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046304 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 120031040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 120031040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 46020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 46020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 61104987 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 61104987 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 61104987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 120031040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 181136026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2055298 # Number of read requests accepted +system.physmem.writeReqs 1046304 # Number of write requests accepted +system.physmem.readBursts 2055298 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046304 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131453056 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue +system.physmem.bytesWritten 66961856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131539072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66963456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 127944 # Per bank write bursts +system.physmem.perBankRdBursts::1 125151 # Per bank write bursts +system.physmem.perBankRdBursts::2 122313 # Per bank write bursts +system.physmem.perBankRdBursts::3 124176 # Per bank write bursts +system.physmem.perBankRdBursts::4 123203 # Per bank write bursts +system.physmem.perBankRdBursts::5 123365 # Per bank write bursts +system.physmem.perBankRdBursts::6 123797 # Per bank write bursts +system.physmem.perBankRdBursts::7 124247 # Per bank write bursts +system.physmem.perBankRdBursts::8 131879 # Per bank write bursts +system.physmem.perBankRdBursts::9 134089 # Per bank write bursts +system.physmem.perBankRdBursts::10 132451 # Per bank write bursts +system.physmem.perBankRdBursts::11 133680 # Per bank write bursts +system.physmem.perBankRdBursts::12 133764 # Per bank write bursts +system.physmem.perBankRdBursts::13 133810 # Per bank write bursts +system.physmem.perBankRdBursts::14 129795 # Per bank write bursts +system.physmem.perBankRdBursts::15 130290 # Per bank write bursts +system.physmem.perBankWrBursts::0 65788 # Per bank write bursts +system.physmem.perBankWrBursts::1 64108 # Per bank write bursts +system.physmem.perBankWrBursts::2 62418 # Per bank write bursts +system.physmem.perBankWrBursts::3 62855 # Per bank write bursts +system.physmem.perBankWrBursts::4 62808 # Per bank write bursts +system.physmem.perBankWrBursts::5 62982 # Per bank write bursts +system.physmem.perBankWrBursts::6 64271 # Per bank write bursts +system.physmem.perBankWrBursts::7 65268 # Per bank write bursts +system.physmem.perBankWrBursts::8 67081 # Per bank write bursts +system.physmem.perBankWrBursts::9 67609 # Per bank write bursts +system.physmem.perBankWrBursts::10 67274 # Per bank write bursts +system.physmem.perBankWrBursts::11 67626 # Per bank write bursts +system.physmem.perBankWrBursts::12 67000 # Per bank write bursts +system.physmem.perBankWrBursts::13 67431 # Per bank write bursts +system.physmem.perBankWrBursts::14 66125 # Per bank write bursts +system.physmem.perBankWrBursts::15 65635 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 2055986 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2055986 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046478 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046478 # Number of write requests responded to by this memory -system.physmem.pageHitRate 38.18 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 127958 # Per bank write bursts -system.physmem.perBankRdBursts::1 125105 # Per bank write bursts -system.physmem.perBankRdBursts::2 122165 # Per bank write bursts -system.physmem.perBankRdBursts::3 124186 # Per bank write bursts -system.physmem.perBankRdBursts::4 123280 # Per bank write bursts -system.physmem.perBankRdBursts::5 123449 # Per bank write bursts -system.physmem.perBankRdBursts::6 123880 # Per bank write bursts -system.physmem.perBankRdBursts::7 124388 # Per bank write bursts -system.physmem.perBankRdBursts::8 131994 # Per bank write bursts -system.physmem.perBankRdBursts::9 133987 # Per bank write bursts -system.physmem.perBankRdBursts::10 132463 # Per bank write bursts -system.physmem.perBankRdBursts::11 133769 # Per bank write bursts -system.physmem.perBankRdBursts::12 133910 # Per bank write bursts -system.physmem.perBankRdBursts::13 133839 # Per bank write bursts -system.physmem.perBankRdBursts::14 129945 # Per bank write bursts -system.physmem.perBankRdBursts::15 130353 # Per bank write bursts -system.physmem.perBankWrBursts::0 65810 # Per bank write bursts -system.physmem.perBankWrBursts::1 64091 # Per bank write bursts -system.physmem.perBankWrBursts::2 62337 # Per bank write bursts -system.physmem.perBankWrBursts::3 62824 # Per bank write bursts -system.physmem.perBankWrBursts::4 62831 # Per bank write bursts -system.physmem.perBankWrBursts::5 62991 # Per bank write bursts -system.physmem.perBankWrBursts::6 64303 # Per bank write bursts -system.physmem.perBankWrBursts::7 65302 # Per bank write bursts -system.physmem.perBankWrBursts::8 67082 # Per bank write bursts -system.physmem.perBankWrBursts::9 67591 # Per bank write bursts -system.physmem.perBankWrBursts::10 67285 # Per bank write bursts -system.physmem.perBankWrBursts::11 67661 # Per bank write bursts -system.physmem.perBankWrBursts::12 67090 # Per bank write bursts -system.physmem.perBankWrBursts::13 67416 # Per bank write bursts -system.physmem.perBankWrBursts::14 66182 # Per bank write bursts -system.physmem.perBankWrBursts::15 65652 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 60782 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.755668 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.633297 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60741 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60782 # Reads before turning the bus around for writes -system.physmem.rdQLenPdf::0 1924013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 130641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.totGap 1095875382500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 2055298 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1046304 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1922424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -623,36 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 2055986 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2055986 # Read request sizes (log2) -system.physmem.readReqs 2055986 # Number of read requests accepted -system.physmem.readRowHitRate 37.77 # Row buffer hit rate for reads -system.physmem.readRowHits 776076 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 1315 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 10273355000 # Total ticks spent in databus transfers -system.physmem.totGap 1134078928500 # Total gap between requests -system.physmem.totMemAccLat 76586290250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 38061209000 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 60782 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.216413 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.182090 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.086488 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 25426 41.83% 41.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1488 2.45% 44.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 29643 48.77% 93.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3806 6.26% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 363 0.60% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 50 0.08% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60782 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -668,30 +140,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 33627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 60930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 33528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 60945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -717,17 +189,544 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 1046478 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046478 # Write request sizes (log2) -system.physmem.writeReqs 1046478 # Number of write requests accepted -system.physmem.writeRowHitRate 38.99 # Row buffer hit rate for writes -system.physmem.writeRowHits 407972 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.bytesPerActivate::samples 1911965 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.774418 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.877172 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.825249 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1485376 77.69% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 306998 16.06% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52789 2.76% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21060 1.10% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13283 0.69% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6873 0.36% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5659 0.30% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4134 0.22% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15793 0.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1911965 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60795 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.737117 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.571664 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60754 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60795 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60795 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.209951 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.175292 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.091996 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 25805 42.45% 42.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1192 1.96% 44.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29551 48.61% 93.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3811 6.27% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 363 0.60% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 60 0.10% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 11 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60795 # Writes before turning the bus around for reads +system.physmem.totQLat 38124649000 # Total ticks spent queuing +system.physmem.totMemAccLat 76636286500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10269770000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18561.59 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 37311.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 119.95 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 61.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 120.03 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 61.10 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 1.41 # Data bus utilization in percentage +system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.69 # Average write queue length when enqueuing +system.physmem.readRowHits 779774 # Number of row buffer hits during reads +system.physmem.writeRowHits 408484 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.04 # Row buffer hit rate for writes +system.physmem.avgGap 353325.60 # Average gap between requests +system.physmem.pageHitRate 38.33 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 306310282500 # Time in different power states +system.physmem.memoryStateTime::REF 36593440000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 752968660500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 181136026 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1255348 # Transaction distribution +system.membus.trans_dist::ReadResp 1255348 # Transaction distribution +system.membus.trans_dist::Writeback 1046304 # Transaction distribution +system.membus.trans_dist::ReadExReq 799950 # Transaction distribution +system.membus.trans_dist::ReadExResp 799950 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5156900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5156900 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198502528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 198502528 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 198502528 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12227667000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 19360882250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.8 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 239641872 # Number of BP lookups +system.cpu.branchPred.condPredicted 186303374 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14594643 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 130836287 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121989290 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 93.238117 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15653729 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.numCycles 2191750941 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1544563087 # Number of instructions committed +system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed +system.cpu.discardedOps 42066132 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.419010 # CPI: cycles per instruction +system.cpu.ipc 0.704717 # IPC: instructions per cycle +system.cpu.tickCycles 1808188284 # Number of cycles that the object actually ticked +system.cpu.idleCycles 383562657 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 29 # number of replacements +system.cpu.icache.tags.tagsinuse 661.141376 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 464847257 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 566886.898780 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 661.141376 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322823 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322823 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 929696974 # Number of tag accesses +system.cpu.icache.tags.data_accesses 929696974 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 464847257 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 464847257 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 464847257 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 464847257 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 464847257 # number of overall hits +system.cpu.icache.overall_hits::total 464847257 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses +system.cpu.icache.overall_misses::total 820 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58324499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58324499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58324499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58324499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58324499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58324499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 464848077 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 464848077 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 464848077 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 464848077 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 464848077 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 464848077 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71127.437805 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71127.437805 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71127.437805 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71127.437805 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 820 # 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Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 755014954 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7336391 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7336391 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890876 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890876 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22153789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22155429 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827349888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 827402368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 827402368 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10164976000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1391999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14185372245 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 2022594 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31252.258926 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8984184 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2052369 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.377470 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 58953869250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14968.183746 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 16284.075180 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.456793 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496951 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.953743 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 107368541 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 107368541 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 6081037 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6081037 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3700895 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700895 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090926 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1090926 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7171963 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7171963 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7171963 # number of overall hits +system.cpu.l2cache.overall_hits::total 7171963 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1255354 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1255354 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 799950 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 799950 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2055304 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2055304 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2055304 # number of overall misses +system.cpu.l2cache.overall_misses::total 2055304 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100122250500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 100122250500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64358555750 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 9227267 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9227267 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9227267 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9227267 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171113 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.171113 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423058 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.423058 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222742 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222742 # 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number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 1046304 # number of writebacks +system.cpu.l2cache.writebacks::total 1046304 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255348 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1255348 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 799950 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 799950 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055298 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2055298 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055298 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2055298 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84333554000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84333554000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54273221250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54273221250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138606775250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 138606775250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138606775250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 138606775250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171112 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171112 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423058 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423058 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222742 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222742 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67179.422758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67179.422758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67845.766923 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67845.766923 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 9222351 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.559894 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624001258 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9226447 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.631804 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9703664000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.559894 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.997451 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997451 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 283 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1314 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1276381727 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276381727 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 453655688 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453655688 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 170345448 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170345448 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 624001136 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624001136 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 624001136 # number of overall hits +system.cpu.dcache.overall_hits::total 624001136 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7335783 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7335783 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2240599 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2240599 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9576382 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9576382 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9576382 # number of overall misses +system.cpu.dcache.overall_misses::total 9576382 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183307188995 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 183307188995 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101248592250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 101248592250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 284555781245 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 284555781245 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 284555781245 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 284555781245 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 460991471 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 460991471 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 633577518 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633577518 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 633577518 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633577518 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012983 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012983 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.015115 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015115 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.015115 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015115 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24988.087706 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24988.087706 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45188.180594 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45188.180594 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29714.330657 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29714.330657 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3700895 # number of writebacks +system.cpu.dcache.writebacks::total 3700895 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 212 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 212 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349723 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 349723 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 349935 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 349935 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 349935 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 349935 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335571 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7335571 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890876 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890876 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9226447 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9226447 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9226447 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9226447 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168217924005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168217924005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77187221250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77187221250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245405145255 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245405145255 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245405145255 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245405145255 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22931.810490 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22931.810490 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40820.879450 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40820.879450 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 80d2ee221..a0b5e888a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.523064 # Number of seconds simulated -sim_ticks 523063504500 # Number of ticks simulated -final_tick 523063504500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.506591 # Number of seconds simulated +sim_ticks 506591420000 # Number of ticks simulated +final_tick 506591420000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149016 # Simulator instruction rate (inst/s) -host_op_rate 166238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50463882 # Simulator tick rate (ticks/s) -host_mem_usage 261252 # Number of bytes of host memory used -host_seconds 10365.11 # Real time elapsed on the host +host_inst_rate 188296 # Simulator instruction rate (inst/s) +host_op_rate 202861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61758141 # Simulator tick rate (ticks/s) +host_mem_usage 254008 # Number of bytes of host memory used +host_seconds 8202.83 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated -sim_ops 1723073835 # Number of ops (including micro ops) simulated +sim_ops 1664032415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143764288 # Number of bytes read from this memory -system.physmem.bytes_read::total 143812352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70447616 # Number of bytes written to this memory -system.physmem.bytes_written::total 70447616 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2246317 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2247068 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100744 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100744 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 91889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 274850543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 274942432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 91889 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91889 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 134682721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 134682721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 134682721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 91889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 274850543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 409625153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2247068 # Number of read requests accepted -system.physmem.writeReqs 1100744 # Number of write requests accepted -system.physmem.readBursts 2247068 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1100744 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 143722368 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 89984 # Total number of bytes read from write queue -system.physmem.bytesWritten 70445760 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 143812352 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70447616 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1406 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 46336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143772736 # Number of bytes read from this memory +system.physmem.bytes_read::total 143819072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 46336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 46336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70460288 # Number of bytes written to this memory +system.physmem.bytes_written::total 70460288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 724 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2246449 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2247173 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100942 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100942 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 91466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 283804128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 283895594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 139087014 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 139087014 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 139087014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 283804128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 422982608 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2247174 # Number of read requests accepted +system.physmem.writeReqs 1100942 # Number of write requests accepted +system.physmem.readBursts 2247174 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1100942 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 143725504 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 93632 # Total number of bytes read from write queue +system.physmem.bytesWritten 70458432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 143819136 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70460288 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1463 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 139750 # Per bank write bursts -system.physmem.perBankRdBursts::1 136144 # Per bank write bursts -system.physmem.perBankRdBursts::2 133842 # Per bank write bursts -system.physmem.perBankRdBursts::3 136111 # Per bank write bursts -system.physmem.perBankRdBursts::4 134906 # Per bank write bursts -system.physmem.perBankRdBursts::5 135203 # Per bank write bursts -system.physmem.perBankRdBursts::6 136131 # Per bank write bursts -system.physmem.perBankRdBursts::7 136315 # Per bank write bursts -system.physmem.perBankRdBursts::8 143809 # Per bank write bursts -system.physmem.perBankRdBursts::9 146590 # Per bank write bursts -system.physmem.perBankRdBursts::10 144423 # Per bank write bursts -system.physmem.perBankRdBursts::11 146169 # Per bank write bursts -system.physmem.perBankRdBursts::12 145711 # Per bank write bursts -system.physmem.perBankRdBursts::13 146127 # Per bank write bursts -system.physmem.perBankRdBursts::14 142010 # Per bank write bursts -system.physmem.perBankRdBursts::15 142421 # Per bank write bursts -system.physmem.perBankWrBursts::0 69157 # Per bank write bursts -system.physmem.perBankWrBursts::1 67395 # Per bank write bursts -system.physmem.perBankWrBursts::2 65690 # Per bank write bursts -system.physmem.perBankWrBursts::3 66283 # Per bank write bursts -system.physmem.perBankWrBursts::4 66211 # Per bank write bursts -system.physmem.perBankWrBursts::5 66391 # Per bank write bursts -system.physmem.perBankWrBursts::6 67933 # Per bank write bursts -system.physmem.perBankWrBursts::7 68845 # Per bank write bursts -system.physmem.perBankWrBursts::8 70389 # Per bank write bursts -system.physmem.perBankWrBursts::9 71029 # Per bank write bursts -system.physmem.perBankWrBursts::10 70577 # Per bank write bursts -system.physmem.perBankWrBursts::11 70974 # Per bank write bursts -system.physmem.perBankWrBursts::12 70326 # Per bank write bursts -system.physmem.perBankWrBursts::13 70796 # Per bank write bursts -system.physmem.perBankWrBursts::14 69605 # Per bank write bursts -system.physmem.perBankWrBursts::15 69114 # Per bank write bursts +system.physmem.perBankRdBursts::0 139870 # Per bank write bursts +system.physmem.perBankRdBursts::1 136313 # Per bank write bursts +system.physmem.perBankRdBursts::2 133717 # Per bank write bursts +system.physmem.perBankRdBursts::3 136218 # Per bank write bursts +system.physmem.perBankRdBursts::4 134833 # Per bank write bursts +system.physmem.perBankRdBursts::5 135331 # Per bank write bursts +system.physmem.perBankRdBursts::6 136159 # Per bank write bursts +system.physmem.perBankRdBursts::7 136113 # Per bank write bursts +system.physmem.perBankRdBursts::8 143820 # Per bank write bursts +system.physmem.perBankRdBursts::9 146459 # Per bank write bursts +system.physmem.perBankRdBursts::10 144333 # Per bank write bursts +system.physmem.perBankRdBursts::11 146068 # Per bank write bursts +system.physmem.perBankRdBursts::12 145787 # Per bank write bursts +system.physmem.perBankRdBursts::13 145950 # Per bank write bursts +system.physmem.perBankRdBursts::14 142167 # Per bank write bursts +system.physmem.perBankRdBursts::15 142573 # Per bank write bursts +system.physmem.perBankWrBursts::0 69256 # Per bank write bursts +system.physmem.perBankWrBursts::1 67490 # Per bank write bursts +system.physmem.perBankWrBursts::2 65701 # Per bank write bursts +system.physmem.perBankWrBursts::3 66292 # Per bank write bursts +system.physmem.perBankWrBursts::4 66182 # Per bank write bursts +system.physmem.perBankWrBursts::5 66456 # Per bank write bursts +system.physmem.perBankWrBursts::6 67905 # Per bank write bursts +system.physmem.perBankWrBursts::7 68814 # Per bank write bursts +system.physmem.perBankWrBursts::8 70409 # Per bank write bursts +system.physmem.perBankWrBursts::9 70980 # Per bank write bursts +system.physmem.perBankWrBursts::10 70565 # Per bank write bursts +system.physmem.perBankWrBursts::11 70894 # Per bank write bursts +system.physmem.perBankWrBursts::12 70329 # Per bank write bursts +system.physmem.perBankWrBursts::13 70807 # Per bank write bursts +system.physmem.perBankWrBursts::14 69706 # Per bank write bursts +system.physmem.perBankWrBursts::15 69127 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 523063435500 # Total gap between requests +system.physmem.totGap 506591366500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2247068 # Read request sizes (log2) +system.physmem.readPktSize::6 2247174 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1100744 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1615066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 449330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 137330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100942 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1574104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 476401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 148213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,160 +144,152 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 65129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 66570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 66892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 67087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 67169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 67424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 67533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 67827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 68851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 70296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 67618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 68033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 66306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 65326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 22580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 65003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 66811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 67460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 67663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 67777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 68170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 69182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 70669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 67984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 68233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 66514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 65455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2025915 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 105.713545 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.619710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.565498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1567130 77.35% 77.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 318929 15.74% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 67085 3.31% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23530 1.16% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13977 0.69% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6837 0.34% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5148 0.25% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3637 0.18% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19642 0.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2025915 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 65189 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 34.403642 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 148.850371 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 65147 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 15 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 2025013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 105.768407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.613194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 129.925028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1567130 77.39% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 318117 15.71% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 66732 3.30% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23886 1.18% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14001 0.69% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6496 0.32% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4833 0.24% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3896 0.19% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19922 0.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2025013 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65320 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 34.335441 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 154.678788 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 65282 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 65189 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 65189 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.884981 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.844479 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.202215 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 39520 60.62% 60.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1483 2.27% 62.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18196 27.91% 90.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4786 7.34% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 898 1.38% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 207 0.32% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 54 0.08% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 10 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 65189 # Writes before turning the bus around for reads -system.physmem.totQLat 50228413500 # Total ticks spent queuing -system.physmem.totMemAccLat 92334576000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 11228310000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22366.86 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 65320 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65320 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.854149 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.813582 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.224401 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 41990 64.28% 64.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 22168 33.94% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 1073 1.64% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 57 0.09% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 14 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-85 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 65320 # Writes before turning the bus around for reads +system.physmem.totQLat 50678676000 # Total ticks spent queuing +system.physmem.totMemAccLat 92785757250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 11228555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22566.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41116.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 274.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 134.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 274.94 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 134.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41316.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 283.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 139.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 283.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 139.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.20 # Data bus utilization in percentage -system.physmem.busUtilRead 2.15 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing -system.physmem.readRowHits 905849 # Number of row buffer hits during reads -system.physmem.writeRowHits 414601 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.67 # Row buffer hit rate for writes -system.physmem.avgGap 156240.38 # Average gap between requests -system.physmem.pageHitRate 39.46 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 94741058000 # Time in different power states -system.physmem.memoryStateTime::REF 17466020000 # Time in different power states +system.physmem.busUtil 3.30 # Data bus utilization in percentage +system.physmem.busUtilRead 2.22 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.09 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing +system.physmem.readRowHits 906473 # Number of row buffer hits during reads +system.physmem.writeRowHits 415128 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 37.71 # Row buffer hit rate for writes +system.physmem.avgGap 151306.40 # Average gap between requests +system.physmem.pageHitRate 39.49 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 89126966500 # Time in different power states +system.physmem.memoryStateTime::REF 16916120000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 410854630500 # Time in different power states +system.physmem.memoryStateTime::ACT 400546526000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 409625031 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1419612 # Transaction distribution -system.membus.trans_dist::ReadResp 1419611 # Transaction distribution -system.membus.trans_dist::Writeback 1100744 # Transaction distribution -system.membus.trans_dist::ReadExReq 827456 # Transaction distribution -system.membus.trans_dist::ReadExResp 827456 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5594879 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5594879 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214259904 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214259904 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214259904 # Total data (bytes) +system.membus.throughput 422982608 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1419539 # Transaction distribution +system.membus.trans_dist::ReadResp 1419538 # Transaction distribution +system.membus.trans_dist::Writeback 1100942 # Transaction distribution +system.membus.trans_dist::ReadExReq 827635 # Transaction distribution +system.membus.trans_dist::ReadExResp 827635 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5595289 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5595289 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214279360 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214279360 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214279360 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12872956000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12858312000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 21034966500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 21011522750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 310041872 # Number of BP lookups -system.cpu.branchPred.condPredicted 254951905 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15242132 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 177250182 # Number of BTB lookups -system.cpu.branchPred.BTBHits 164623168 # Number of BTB hits +system.cpu.branchPred.lookups 322479068 # Number of BP lookups +system.cpu.branchPred.condPredicted 251697336 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15342173 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 182789015 # Number of BTB lookups +system.cpu.branchPred.BTBHits 169211218 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.876163 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17905906 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.571875 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19180311 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 62 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -383,380 +375,377 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1046127010 # number of cpu cycles simulated +system.cpu.numCycles 1013182841 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 304406506 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2237155990 # Number of instructions fetch has processed -system.cpu.fetch.Branches 310041872 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 182529074 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 444747763 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 93800973 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 104367517 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 295060555 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6266924 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 929205544 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.663579 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.245143 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 309137299 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2319640214 # Number of instructions fetch has processed +system.cpu.fetch.Branches 322479068 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 188391529 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 688452374 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31084694 # Number of cycles fetch has spent squashing +system.cpu.fetch.CacheLines 300792002 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5498702 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1013132020 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.455758 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.154346 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 484458019 52.14% 52.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25667204 2.76% 54.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39962445 4.30% 59.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 49351933 5.31% 64.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 44527866 4.79% 69.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 47023403 5.06% 74.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39036338 4.20% 78.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19508250 2.10% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 179670086 19.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 555222202 54.80% 54.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 28050197 2.77% 57.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43308558 4.27% 61.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 56959165 5.62% 67.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 42292761 4.17% 71.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 51207543 5.05% 76.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41019007 4.05% 80.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29441196 2.91% 83.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 165631391 16.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 929205544 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.296371 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.138513 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 323230837 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95973570 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 424273226 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10044892 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 75683019 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46957126 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 712 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2419092576 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2470 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 75683019 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 338590369 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36235131 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20070 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 418478079 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 60198876 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2357219159 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 486871 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 10439342 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 39865193 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 9487400 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 108 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2332621614 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10887738442 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9980989966 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 478 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 626301684 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1665 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1662 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62763220 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 637377073 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 224726985 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 97022139 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 86012676 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2244793752 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1629 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2031991177 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 6410093 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 517307509 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1273036014 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1459 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 929205544 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.186805 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.944442 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1013132020 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.318283 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.289459 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 248682792 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 345622952 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 359459924 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 43824601 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15541751 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 49856372 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 610 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2395697302 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2189 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15541751 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 269479595 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 192381996 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17471 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 380094168 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 155617039 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2338847400 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 939227 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 43524152 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 85831703 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 28336004 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2341659219 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10827293229 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2896191361 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 924 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 666760274 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 297 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 295 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 177584133 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 623787680 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 234474986 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 103326529 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 119861826 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2235979798 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2042453270 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1123672 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 568282292 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1410742018 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 109 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1013132020 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.015979 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.060962 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 266904218 28.72% 28.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 128322549 13.81% 42.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158977129 17.11% 59.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 117185502 12.61% 72.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 128428514 13.82% 86.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 72785870 7.83% 93.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42669642 4.59% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10960354 1.18% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2971766 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 369509753 36.47% 36.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 122144381 12.06% 48.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 148105848 14.62% 63.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 116397380 11.49% 74.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 120158766 11.86% 86.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 67734855 6.69% 93.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38716090 3.82% 97.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19620402 1.94% 98.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10744545 1.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 929205544 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1013132020 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1285844 5.85% 5.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5675 0.03% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18368199 83.62% 89.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2306433 10.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3650692 18.70% 18.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 890 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15434151 79.07% 97.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 434530 2.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1245462856 61.29% 61.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 947392 0.05% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 51 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 9 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 592199391 29.14% 90.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193381454 9.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1227555044 60.10% 60.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 999501 0.05% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 75 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 36 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 18 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 618802083 30.30% 90.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 195096510 9.55% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2031991177 # Type of FU issued -system.cpu.iq.rate 1.942394 # Inst issue rate -system.cpu.iq.fu_busy_cnt 21966151 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010810 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5021563817 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2762296727 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1969035141 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 325 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 660 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 139 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2053957167 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 66315008 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2042453270 # Type of FU issued +system.cpu.iq.rate 2.015878 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19520263 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009557 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5118681932 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2804481694 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1937195401 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 563 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 772 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 222 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2061973250 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 283 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 29620868 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 151450304 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 182572 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 197144 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 49879940 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 165481346 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 152761 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 223174 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 59627941 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4648682 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 27365932 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 20554693 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 75683019 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13889446 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17402817 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2244795480 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7970371 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 637377073 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 224726985 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1567 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 551835 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16641279 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 197144 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8164855 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9718586 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17883441 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2000301565 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 577561658 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 31689612 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15541751 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 99594513 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 79709192 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2235980127 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3715851 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 623787680 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 234474986 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 217 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 887425 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 78519079 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 223174 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8257753 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10408115 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18665868 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2014561503 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 604829298 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27891767 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 99 # number of nop insts executed -system.cpu.iew.exec_refs 768256899 # number of memory reference insts executed -system.cpu.iew.exec_branches 239583236 # Number of branches executed -system.cpu.iew.exec_stores 190695241 # Number of stores executed -system.cpu.iew.exec_rate 1.912102 # Inst execution rate -system.cpu.iew.wb_sent 1977910575 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1969035280 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1321133911 # num instructions producing a value -system.cpu.iew.wb_consumers 2129107129 # num instructions consuming a value +system.cpu.iew.exec_nop 50 # number of nop insts executed +system.cpu.iew.exec_refs 796810326 # number of memory reference insts executed +system.cpu.iew.exec_branches 245407289 # Number of branches executed +system.cpu.iew.exec_stores 191981028 # Number of stores executed +system.cpu.iew.exec_rate 1.988349 # Inst execution rate +system.cpu.iew.wb_sent 1947397166 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1937195623 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1312629106 # num instructions producing a value +system.cpu.iew.wb_consumers 2061058840 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.882214 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.620511 # average fanout of values written-back +system.cpu.iew.wb_rate 1.911990 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.636871 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 522107871 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 572342091 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15241473 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 853522525 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.018780 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.777115 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15341577 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 933174586 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.783195 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.675212 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 375117315 43.95% 43.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 185477330 21.73% 65.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 70116011 8.21% 73.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 33059312 3.87% 77.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18836055 2.21% 79.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30683416 3.59% 83.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20461939 2.40% 85.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11515545 1.35% 87.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 108255602 12.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 468896979 50.25% 50.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 178641910 19.14% 69.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 68227019 7.31% 76.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 32102473 3.44% 80.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24397966 2.61% 82.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27603302 2.96% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17322198 1.86% 87.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 14774408 1.58% 89.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101208331 10.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 853522525 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 933174586 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed -system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773814 # Number of memory references committed -system.cpu.commit.loads 485926769 # Number of loads committed +system.cpu.commit.refs 633153379 # Number of memory references committed +system.cpu.commit.loads 458306334 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed system.cpu.commit.branches 213462426 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. +system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1061599714 61.61% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 485926769 28.20% 89.85% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 174847045 10.15% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1030178729 61.91% 61.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1723073853 # Class of committed instruction -system.cpu.commit.bw_lim_events 108255602 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction +system.cpu.commit.bw_lim_events 101208331 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2990448048 # The number of ROB reads -system.cpu.rob.rob_writes 4566229463 # The number of ROB writes -system.cpu.timesIdled 1335234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 116921466 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3068340180 # The number of ROB reads +system.cpu.rob.rob_writes 4552875899 # The number of ROB writes +system.cpu.timesIdled 556 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50821 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated -system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.677296 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.677296 # CPI: Total CPI of All Threads -system.cpu.ipc 1.476458 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.476458 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10016037678 # number of integer regfile reads -system.cpu.int_regfile_writes 1949973157 # number of integer regfile writes -system.cpu.fp_regfile_reads 144 # number of floating regfile reads -system.cpu.fp_regfile_writes 144 # number of floating regfile writes -system.cpu.misc_regfile_reads 741547581 # number of misc regfile reads +system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.655967 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.655967 # CPI: Total CPI of All Threads +system.cpu.ipc 1.524466 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.524466 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2376547647 # number of integer regfile reads +system.cpu.int_regfile_writes 1366493054 # number of integer regfile writes +system.cpu.fp_regfile_reads 209 # number of floating regfile reads +system.cpu.fp_regfile_writes 233 # number of floating regfile writes +system.cpu.cc_regfile_reads 7643535318 # number of cc regfile reads +system.cpu.cc_regfile_writes 583887345 # number of cc regfile writes +system.cpu.misc_regfile_reads 725285725 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1637500473 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7708273 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7708272 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3780671 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1894131 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1894131 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22983914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22985478 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856466688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 856516736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856516736 # Total data (bytes) +system.cpu.toL2Bus.throughput 1691907313 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7714547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7714546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3783532 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1894199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1894199 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1502 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22999521 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23001023 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 48064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 857057664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 857105728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 857105728 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10472370339 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1301749 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10479902270 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1252249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14750464244 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 21 # number of replacements -system.cpu.icache.tags.tagsinuse 633.135504 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 295059337 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 377313.730179 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 14758141993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.9 # Layer utilization (%) +system.cpu.icache.tags.replacements 15 # number of replacements +system.cpu.icache.tags.tagsinuse 614.894819 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 300790815 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 751 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 400520.392810 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 633.135504 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.309148 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.309148 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 761 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 732 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.371582 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 590121892 # Number of tag accesses -system.cpu.icache.tags.data_accesses 590121892 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 295059337 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 295059337 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 295059337 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 295059337 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 295059337 # number of overall hits -system.cpu.icache.overall_hits::total 295059337 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1218 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1218 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1218 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1218 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1218 # number of overall misses -system.cpu.icache.overall_misses::total 1218 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82722999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82722999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82722999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82722999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82722999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82722999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 295060555 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 295060555 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 295060555 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 295060555 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 295060555 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 295060555 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 614.894819 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.300242 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.300242 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 736 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 709 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.359375 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 601584755 # Number of tag accesses +system.cpu.icache.tags.data_accesses 601584755 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 300790815 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 300790815 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 300790815 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 300790815 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 300790815 # number of overall hits +system.cpu.icache.overall_hits::total 300790815 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1187 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1187 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1187 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1187 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1187 # number of overall misses +system.cpu.icache.overall_misses::total 1187 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 83295499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 83295499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 83295499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 83295499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 83295499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 83295499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 300792002 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 300792002 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 300792002 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 300792002 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 300792002 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 300792002 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67917.076355 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67917.076355 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67917.076355 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67917.076355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67917.076355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67917.076355 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 292 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70173.124684 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70173.124684 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70173.124684 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70173.124684 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -766,123 +755,123 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 436 system.cpu.icache.demand_mshr_hits::total 436 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 436 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 436 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 782 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 782 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 782 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55396751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 55396751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55396751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 55396751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55396751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 55396751 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # 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number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1418861 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1419612 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 827456 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 827456 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2246317 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2247068 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2246317 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2247068 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44796750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 101386052500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 101430849250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60631607750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60631607750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44796750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162017660250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 162062457000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44796750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162017660250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 162062457000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184089 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184167 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436853 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436853 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.234011 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233952 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.234011 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59649.467377 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71455.944240 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71449.698404 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73274.721254 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73274.721254 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59649.467377 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72125.911102 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72121.741309 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59649.467377 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72125.911102 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72121.741309 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 724 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1418815 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1419539 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 827635 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 827635 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 724 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2246450 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2247174 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 724 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2246450 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2247174 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44565250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 101708549750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 101753115000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60858432750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60858432750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44565250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162566982500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 162611547750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44565250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162566982500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 162611547750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964048 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.183932 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184008 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436931 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436931 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964048 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233810 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233868 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964048 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233810 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233868 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61554.212707 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71685.561366 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71680.394128 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73532.937527 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73532.937527 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61554.212707 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72366.169957 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72362.686534 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61554.212707 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72366.169957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72362.686534 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9597525 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.935639 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 657806876 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9601621 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 68.509981 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3523864250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.935639 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998031 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9603898 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.677378 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 678741158 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9607994 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 70.643379 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3511642250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.677378 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997968 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 660 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 657 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2421 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1359744661 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1359744661 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 490891096 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 490891096 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166915657 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166915657 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 1403558154 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1403558154 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 511838800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 511838800 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166902232 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166902232 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 657806753 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 657806753 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 657806753 # number of overall hits -system.cpu.dcache.overall_hits::total 657806753 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11594251 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11594251 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5670390 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5670390 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 678741032 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 678741032 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 678741034 # number of overall hits +system.cpu.dcache.overall_hits::total 678741034 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12550102 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12550102 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5683815 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5683815 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17264641 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17264641 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17264641 # number of overall misses -system.cpu.dcache.overall_misses::total 17264641 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 353287122740 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 353287122740 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 298200381062 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 298200381062 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 243250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 243250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 651487503802 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 651487503802 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 651487503802 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 651487503802 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 502485347 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 502485347 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 18233917 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 18233917 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 18233919 # number of overall misses +system.cpu.dcache.overall_misses::total 18233919 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 378927155489 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 378927155489 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 307221007401 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 307221007401 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 686148162890 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 686148162890 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 686148162890 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 686148162890 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 524388902 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 524388902 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 4 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 4 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 66 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 66 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 675071394 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 675071394 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 675071394 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 675071394 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023074 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023074 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032855 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032855 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025575 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025575 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025575 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025575 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30470.887920 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30470.887920 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52589.042564 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52589.042564 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 81083.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 81083.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37735.363498 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37735.363498 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37735.363498 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37735.363498 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22798709 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4000734 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1307566 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.435991 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.425957 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 696974949 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 696974949 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 696974953 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 696974953 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023933 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032933 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032933 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.500000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.500000 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045455 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045455 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026162 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026162 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026162 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026162 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30193.153449 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30193.153449 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54051.901302 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54051.901302 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37630.321718 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37630.321718 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37630.317591 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37630.317591 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28822616 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4626055 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1847693 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65151 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.599245 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 71.005127 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3780671 # number of writebacks -system.cpu.dcache.writebacks::total 3780671 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3886759 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3886759 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3776260 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3776260 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3783532 # number of writebacks +system.cpu.dcache.writebacks::total 3783532 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4836306 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4836306 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3789617 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3789617 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7663019 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7663019 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7663019 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7663019 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707492 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7707492 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894130 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1894130 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601622 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601622 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601622 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601622 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 191674058756 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 191674058756 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84036609462 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84036609462 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 275710668218 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 275710668218 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 275710668218 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 275710668218 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015339 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015339 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 8625923 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8625923 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8625923 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8625923 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7713796 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7713796 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894198 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1894198 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9607994 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9607994 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9607995 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9607995 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 192253948507 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 192253948507 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84881076130 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84881076130 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 277135024637 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 277135024637 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 277135094137 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 277135094137 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014710 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014710 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014223 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24868.538139 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24868.538139 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44366.864715 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44366.864715 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28715.009633 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28715.009633 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28715.009633 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28715.009633 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.013785 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.013785 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24923.390314 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24923.390314 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44811.089511 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44811.089511 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28844.212917 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28844.212917 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28844.217148 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28844.217148 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 38623e444..4decc9d3b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.861538 # Number of seconds simulated -sim_ticks 861538200000 # Number of ticks simulated -final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.832017 # Number of seconds simulated +sim_ticks 832017490000 # Number of ticks simulated +final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1785934 # Simulator instruction rate (inst/s) -host_op_rate 1992340 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 996171702 # Simulator tick rate (ticks/s) -host_mem_usage 301680 # Number of bytes of host memory used -host_seconds 864.85 # Real time elapsed on the host +host_inst_rate 1782051 # Simulator instruction rate (inst/s) +host_op_rate 1919890 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 959946236 # Simulator tick rate (ticks/s) +host_mem_usage 306272 # Number of bytes of host memory used +host_seconds 866.73 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated -sim_ops 1723073853 # Number of ops (including micro ops) simulated +sim_ops 1664032433 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory @@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 6178262356 # Nu system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1544565589 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 482384187 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2026949776 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1999474786 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7171199554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1835539818 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9006739373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7171199554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7171199554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 724469782 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 724469782 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7171199554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2560009600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9731209155 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9731209155 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1900666380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9326306382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10076480987 # Throughput (bytes/s) system.membus.data_through_bus 8383808419 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1723076401 # number of cpu cycles simulated +system.cpu.numCycles 1664034981 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563041 # Number of instructions committed -system.cpu.committedOps 1723073853 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses +system.cpu.committedOps 1664032433 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330256 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls -system.cpu.num_int_insts 1536941842 # number of integer instructions +system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls +system.cpu.num_int_insts 1477900422 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 7861285293 # number of times the integer registers were read -system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written +system.cpu.num_int_register_reads 2605402942 # number of times the integer registers were read +system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 660773815 # number of memory refs -system.cpu.num_load_insts 485926769 # Number of load instructions +system.cpu.num_cc_register_reads 4992096236 # number of times the CC registers were read +system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written +system.cpu.num_mem_refs 633153380 # number of memory refs +system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1723076401 # Number of busy cycles +system.cpu.num_busy_cycles 1664034981 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 213462426 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1061599760 61.61% 61.61% # Class of executed instruction -system.cpu.op_class::IntMult 700322 0.04% 61.65% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::MemRead 485926769 28.20% 89.85% # Class of executed instruction -system.cpu.op_class::MemWrite 174847046 10.15% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction +system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction +system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1723073900 # Class of executed instruction +system.cpu.op_class::total 1664032480 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index de9b22f80..8e22dfda9 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.391205 # Number of seconds simulated -sim_ticks 2391205115000 # Number of ticks simulated -final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.363671 # Number of seconds simulated +sim_ticks 2363670998000 # Number of ticks simulated +final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 867002 # Simulator instruction rate (inst/s) -host_op_rate 967582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1347305237 # Simulator tick rate (ticks/s) -host_mem_usage 310408 # Number of bytes of host memory used -host_seconds 1774.81 # Real time elapsed on the host +host_inst_rate 1066052 # Simulator instruction rate (inst/s) +host_op_rate 1148821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1637550718 # Simulator tick rate (ticks/s) +host_mem_usage 316024 # Number of bytes of host memory used +host_seconds 1443.42 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated -sim_ops 1717270334 # Number of ops (including micro ops) simulated +sim_ops 1658228914 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory @@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data 1958158 # Nu system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52409604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52426091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16487 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16487 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27225047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27225047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27225047 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 79651138 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 80578984 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1177898 # Transaction distribution system.membus.trans_dist::ReadResp 1177898 # Transaction distribution system.membus.trans_dist::Writeback 1017198 # Transaction distribution @@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1 system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 190462208 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -138,73 +138,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4782410230 # number of cpu cycles simulated +system.cpu.numCycles 4727341996 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759601 # Number of instructions committed -system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses +system.cpu.committedOps 1658228914 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330256 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls -system.cpu.num_int_insts 1536941842 # number of integer instructions +system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls +system.cpu.num_int_insts 1477900422 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 9304895467 # number of times the integer registers were read -system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written +system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read +system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 660773815 # number of memory refs -system.cpu.num_load_insts 485926769 # Number of load instructions +system.cpu.num_cc_register_reads 6356387675 # number of times the CC registers were read +system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written +system.cpu.num_mem_refs 633153380 # number of memory refs +system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4782410230 # Number of busy cycles +system.cpu.num_busy_cycles 4727341996 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 213462426 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1061599760 61.61% 61.61% # Class of executed instruction -system.cpu.op_class::IntMult 700322 0.04% 61.65% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::MemRead 485926769 28.20% 89.85% # Class of executed instruction -system.cpu.op_class::MemWrite 174847046 10.15% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction +system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction +system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1723073900 # Class of executed instruction +system.cpu.op_class::total 1664032480 # Class of executed instruction system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id @@ -224,12 +226,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34233000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34233000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34233000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34233000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34233000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34233000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses @@ -242,12 +244,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53656.739812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53656.739812 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -262,44 +264,44 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32957000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32957000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32957000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32957000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32957000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32957000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1926075 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.946305 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26880 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1732 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26841 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses @@ -327,17 +329,17 @@ system.cpu.l2cache.demand_misses::total 1958774 # nu system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32099000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61225555000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 61257654000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608829000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 40608829000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32099000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101834384000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 101866483000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32099000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101834384000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 101866483000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) @@ -362,17 +364,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.214875 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52108.766234 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.907133 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.196569 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.196569 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52005.225207 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52005.225207 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,17 +396,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1958774 system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24707000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098171000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122878000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24707000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336488000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78361195000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24707000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336488000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78361195000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses @@ -416,92 +418,98 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1214 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1319055826 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1319055826 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits -system.cpu.dcache.overall_hits::total 645854937 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits +system.cpu.dcache.overall_hits::total 618379947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -512,40 +520,48 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks system.cpu.dcache.writebacks::total 3697418 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 346939438 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution |