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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
commit | 4646369afd408b486fd3515c35d6c6bbe8960839 (patch) | |
tree | 0649a2372083956dc573d4b0d56d60c1c15a344c /tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini | |
parent | 4920f0d7e5a4c29ada074bf3a73f36510e138016 (diff) | |
download | gem5-4646369afd408b486fd3515c35d6c6bbe8960839.tar.xz |
regressions: update due to cache latency fix
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini')
-rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 8d2d15293..9b4ab11e5 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -179,6 +179,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -211,6 +212,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -218,25 +220,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false |