diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
| commit | 8fe556338db4cc50a3f1ba20306bc5e464941f2b (patch) | |
| tree | d95b1933c18d142f9c533f32ac7b84bd1f2d0da5 /tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | |
| parent | 66e331c7bb7d503c35808325e1bfaa9f18f4bdb9 (diff) | |
| download | gem5-8fe556338db4cc50a3f1ba20306bc5e464941f2b.tar.xz | |
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 638 |
1 files changed, 398 insertions, 240 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index feb13ce30..a6fa2a523 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.042001 # Number of seconds simulated -sim_ticks 42001440000 # Number of ticks simulated -final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041975 # Number of seconds simulated +sim_ticks 41974805000 # Number of ticks simulated +final_tick 41974805000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134131 # Simulator instruction rate (inst/s) -host_op_rate 134131 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61300636 # Simulator tick rate (ticks/s) -host_mem_usage 216520 # Number of bytes of host memory used -host_seconds 685.17 # Real time elapsed on the host +host_inst_rate 82989 # Simulator instruction rate (inst/s) +host_op_rate 82989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37903288 # Simulator tick rate (ticks/s) +host_mem_usage 220440 # Number of bytes of host memory used +host_seconds 1107.42 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,172 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4257378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3266936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7524313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4257378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4257378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4257378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3266936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7524313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4260079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3269009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7529088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4260079 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4260079 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4260079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3269009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7529088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4938 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 316032 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 316032 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 349 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 352 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 383 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 306 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 356 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 332 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 41974753000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 4938 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 3879 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 15273921 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 109715921 # Sum of mem lat for all requests +system.physmem.totBusLat 19752000 # Total cycles spent in databus access +system.physmem.totBankLat 74690000 # Total cycles spent in bank access +system.physmem.avgQLat 3093.14 # Average queueing delay per request +system.physmem.avgBankLat 15125.56 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 22218.70 # Average memory access latency +system.physmem.avgRdBW 7.53 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 7.53 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 4458 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 8500355.00 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -43,10 +201,10 @@ system.cpu.dtb.data_hits 26498122 # DT system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 26498155 # DTB accesses -system.cpu.itb.fetch_hits 10035828 # ITB hits +system.cpu.itb.fetch_hits 10035744 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 10035877 # ITB accesses +system.cpu.itb.fetch_accesses 10035793 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 84002881 # number of cpu cycles simulated +system.cpu.numCycles 83949611 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 13564877 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9782208 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4497797 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 7992443 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 3850454 # Number of BTB hits +system.cpu.branch_predictor.lookups 13564912 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9782242 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4497823 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 7992579 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3850502 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 48.176183 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 5999677 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7565200 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73745294 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 48.175964 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5999728 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7565184 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73745301 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136320766 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 136320773 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38528678 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26769096 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3520460 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 976479 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4496939 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5743763 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.912410 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57470351 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 38528717 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26769089 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3520477 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 976488 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4496965 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5743737 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 43.912663 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57470360 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83639631 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83639616 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 11378 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7720370 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76282511 # Number of cycles cpu stages are processed. -system.cpu.activity 90.809399 # Percentage of cycles cpu is active +system.cpu.timesIdled 11375 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7667023 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76282588 # Number of cycles cpu stages are processed. +system.cpu.activity 90.867113 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -107,144 +265,144 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.914038 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.913458 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.914038 # CPI: Total CPI of All Threads -system.cpu.ipc 1.094046 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.913458 # CPI: Total CPI of All Threads +system.cpu.ipc 1.094741 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.094046 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27781439 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56221442 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.927993 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34555420 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49447461 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.864006 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34024816 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.094741 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27728071 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56221540 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.970578 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34502106 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49447505 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.901411 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33971546 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.495656 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65973303 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029578 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.463047 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 30058791 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53944090 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.216952 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.utilization 59.533409 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65920043 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029568 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.476655 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30005535 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53944076 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.257684 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 8127 # number of replacements -system.cpu.icache.tagsinuse 1492.293343 # Cycle average of tags in use -system.cpu.icache.total_refs 10024070 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1492.468291 # Cycle average of tags in use +system.cpu.icache.total_refs 10023999 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1001.205553 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1001.198462 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.293343 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728659 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728659 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10024070 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10024070 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10024070 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10024070 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10024070 # number of overall hits -system.cpu.icache.overall_hits::total 10024070 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11754 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11754 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11754 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11754 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11754 # number of overall misses -system.cpu.icache.overall_misses::total 11754 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 284626500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 284626500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 284626500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 284626500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 284626500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 284626500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 10035824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 10035824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 10035824 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 10035824 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 10035824 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 10035824 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24215.288412 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24215.288412 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24215.288412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1492.468291 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728744 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728744 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10023999 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10023999 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10023999 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10023999 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10023999 # number of overall hits +system.cpu.icache.overall_hits::total 10023999 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11743 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11743 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11743 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11743 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11743 # number of overall misses +system.cpu.icache.overall_misses::total 11743 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 259067500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 259067500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 259067500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 259067500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 259067500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 259067500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 10035742 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 10035742 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 10035742 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 10035742 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 10035742 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 10035742 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001170 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001170 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001170 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001170 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001170 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001170 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22061.440858 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22061.440858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22061.440858 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22061.440858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22061.440858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22061.440858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 184 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 67 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 16.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1742 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1742 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1742 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1742 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1742 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1731 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1731 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1731 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1731 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1731 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1731 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231904000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 231904000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231904000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 231904000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231904000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 231904000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210374500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 210374500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210374500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 210374500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210374500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 210374500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23162.604874 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23162.604874 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21012.235318 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21012.235318 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21012.235318 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21012.235318 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21012.235318 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21012.235318 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.465399 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491189 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.629591 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491183 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.864148 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11916.861448 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.465399 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351920 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351920 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995639 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995639 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6495550 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6495550 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26491189 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26491189 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26491189 # number of overall hits -system.cpu.dcache.overall_hits::total 26491189 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 559 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 559 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5553 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5553 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6112 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6112 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6112 # number of overall misses -system.cpu.dcache.overall_misses::total 6112 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28955000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28955000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 305088500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 305088500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 334043500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 334043500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 334043500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 334043500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 1441.629591 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351960 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351960 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995637 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995637 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6495546 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6495546 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26491183 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491183 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491183 # number of overall hits +system.cpu.dcache.overall_hits::total 26491183 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 561 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 561 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5557 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5557 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6118 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6118 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6118 # number of overall misses +system.cpu.dcache.overall_misses::total 6118 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28389500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28389500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 249397000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 249397000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 277786500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 277786500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 277786500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 277786500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -255,38 +413,38 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000854 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000854 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000855 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000855 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000231 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51797.853309 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51797.853309 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54941.202953 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54941.202953 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54653.714005 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50605.169340 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50605.169340 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44879.791254 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44879.791254 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45404.789147 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45404.789147 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45404.789147 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45404.789147 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 82457 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 63919 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 99.706167 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 77.290206 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3805 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3805 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3889 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3889 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3889 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3889 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 86 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3809 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3809 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3895 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3895 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3895 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3895 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -295,14 +453,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24156000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24156000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96637000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 96637000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 120793000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 120793000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 120793000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 120793000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23282500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23282500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80468500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 80468500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 103751000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 103751000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 103751000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 103751000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -311,28 +469,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50854.736842 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50854.736842 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55284.324943 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55284.324943 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49015.789474 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49015.789474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46034.610984 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46034.610984 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46671.614935 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 46671.614935 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46671.614935 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 46671.614935 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.683531 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2189.948520 # Cycle average of tags in use system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.845444 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1820.840268 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 350.997820 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.843388 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1821.063413 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.041719 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066824 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055574 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066832 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits @@ -357,17 +515,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149399500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23132500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 172532000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 94615000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 94615000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 149399500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 117747500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 267147000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 149399500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 117747500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 267147000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127870000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22259000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 150129000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78446500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 78446500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 127870000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 100705500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 228575500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 127870000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 100705500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 228575500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses) @@ -392,17 +550,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.403596 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53471.546170 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54816.350711 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53648.009950 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54944.831591 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54944.831591 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54100.243013 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54100.243013 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45765.926986 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52746.445498 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 46681.902985 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45555.458769 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45555.458769 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45765.926986 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46970.848881 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46289.084650 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45765.926986 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46970.848881 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46289.084650 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,17 +580,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115312500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17984000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133296500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73481500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73481500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115312500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91465500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 206778000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115312500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91465500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 206778000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 92500808 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16940683 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109441491 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 57047489 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 57047489 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92500808 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73988172 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 166488980 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92500808 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73988172 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 166488980 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses @@ -444,17 +602,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41271.474588 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42616.113744 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41447.916667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42672.183508 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42672.183508 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33106.946314 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40143.798578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34030.314366 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33128.623113 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33128.623113 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33106.946314 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34509.408582 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33715.872823 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33106.946314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34509.408582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33715.872823 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |