stats: Cumulative stats update

This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.

1 files changed, 47 insertions, 46 deletions

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index 9ab9303b1..5350fe782 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.041672                       # Nu
 sim_ticks                                 41671895000                       # Number of ticks simulated
 final_tick                                41671895000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  84546                       # Simulator instruction rate (inst/s)
-host_op_rate                                    84546                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               38336000                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228812                       # Number of bytes of host memory used
-host_seconds                                  1087.02                       # Real time elapsed on the host
+host_inst_rate                                 101828                       # Simulator instruction rate (inst/s)
+host_op_rate                                   101828                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               46172411                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228672                       # Number of bytes of host memory used
+host_seconds                                   902.53                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            178816                       # Number of bytes read from this memory
@@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total            4291046                       # In
 system.physmem.bw_total::cpu.inst             4291046                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data             3292771                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                7583816                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          4938                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                           4938                       # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs                          4938                       # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs                            0                       # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts                        4938                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts                          0                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
 system.physmem.bytesRead                       316032                       # Total number of bytes read from memory
 system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
 system.physmem.bytesConsumedRd                 316032                       # bytesRead derated as per pkt->getSize()
 system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by write Q
 system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
 system.physmem.perBankRdReqs::0                   443                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::1                   270                       # Track reads on a per bank basis
@@ -239,10 +240,10 @@ system.membus.trans_dist::ReadReq                3216                       # Tr
 system.membus.trans_dist::ReadResp               3216                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1722                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1722                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side         9876                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                          9876                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side       316032                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                     316032                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         9876                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   9876                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       316032                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              316032                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 316032                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy             5784500                       # Layer occupancy (ticks)
@@ -351,15 +352,15 @@ system.cpu.stage3.utilization               21.629101                       # Pe
 system.cpu.stage4.idleCycles                 29484037                       # Number of cycles 0 instructions are processed.
 system.cpu.stage4.runCycles                  53859754                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage4.utilization               64.623595                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.tags.replacements                   7635                       # number of replacements
-system.cpu.icache.tags.tagsinuse               1492.268238                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                  9945551                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                   9520                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                1044.700735                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst    1492.268238                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.728647                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.728647                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements              7635                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1492.268238                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             9945551                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              9520                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1044.700735                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1492.268238                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.728647                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.728647                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst      9945551                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total         9945551                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst       9945551                       # number of demand (read+write) hits
@@ -441,12 +442,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp          9995                       # Tr
 system.cpu.toL2Bus.trans_dist::Writeback          107                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1748                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1748                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side        19040                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side         4553                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                    23593                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side       609280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side       149120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size                758400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        19040                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4553                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             23593                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       609280                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       149120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         758400                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.data_through_bus            758400                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy        6032000                       # Layer occupancy (ticks)
@@ -455,19 +456,19 @@ system.cpu.toL2Bus.respLayer0.occupancy      14868500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       3600000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse              2189.714615                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                    6793                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                  3282                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  2.069775                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse         2189.714615                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               6793                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3282                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.069775                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks    17.843770                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   1820.865070                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    351.005775                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1820.865070                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   351.005775                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000545                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.055568                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.010712                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.066825                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.066825                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst         6726                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           53                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           6779                       # number of ReadReq hits
@@ -591,15 +592,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52663.027917
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55345.382463                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53827.663021                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                    157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse               1441.455272                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 26488508                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                   2223                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs               11915.658120                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    1441.455272                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.351918                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.351918                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements               157                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1441.455272                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26488508                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2223                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          11915.658120                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  1441.455272                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.351918                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.351918                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     19995622                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        19995622                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      6492886                       # number of WriteReq hits