diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/se/70.twolf/ref/alpha/tru64/minor-timing | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/minor-timing')
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt | 538 |
1 files changed, 271 insertions, 267 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 78502d1ca..d3e370d8a 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.053345 # Number of seconds simulated -sim_ticks 53344764500 # Number of ticks simulated -final_tick 53344764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.053349 # Number of seconds simulated +sim_ticks 53349450500 # Number of ticks simulated +final_tick 53349450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260335 # Simulator instruction rate (inst/s) -host_op_rate 260335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 151110624 # Simulator tick rate (ticks/s) -host_mem_usage 253412 # Number of bytes of host memory used -host_seconds 353.02 # Real time elapsed on the host +host_inst_rate 273465 # Simulator instruction rate (inst/s) +host_op_rate 273465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158745564 # Simulator tick rate (ticks/s) +host_mem_usage 258296 # Number of bytes of host memory used +host_seconds 336.07 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory system.physmem.bytes_read::total 340608 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 202880 # Nu system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3803185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2581847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6385031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3803185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3803185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3803185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2581847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6385031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3802851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2581620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6384471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3802851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3802851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3802851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2581620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6384471 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5322 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 53344677500 # Total gap between requests +system.physmem.totGap 53349362500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -92,8 +92,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 4932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,29 +187,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.749242 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 211.692592 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.528362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 314 31.75% 31.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 216 21.84% 53.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88 8.90% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 117 11.83% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 52 5.26% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 40 4.04% 83.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 2.93% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 2.12% 88.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 112 11.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 989 # Bytes accessed per row activation -system.physmem.totQLat 40222250 # Total ticks spent queuing -system.physmem.totMemAccLat 140009750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.743381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 213.338865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.606559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 303 30.86% 30.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 220 22.40% 53.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94 9.57% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 105 10.69% 73.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 62 6.31% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 3.67% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 29 2.95% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 22 2.24% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 111 11.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation +system.physmem.totQLat 40016750 # Total ticks spent queuing +system.physmem.totMemAccLat 139804250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7557.73 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7519.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26307.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26269.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.39 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -217,49 +217,49 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4331 # Number of row buffer hits during reads +system.physmem.readRowHits 4333 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10023426.81 # Average gap between requests -system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3538080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1930500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 20022600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 10024307.12 # Average gap between requests +system.physmem.pageHitRate 81.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3462480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1889250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19843200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1791514845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30434811000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 35735961585 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.917071 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 50627942250 # Time in different power states +system.physmem_0.actBackEnergy 1795262310 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30431523750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 35736125550 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.920144 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 50622338000 # Time in different power states system.physmem_0.memoryStateTime::REF 1781260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 934855250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 940274500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3938760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2149125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21411000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3923640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2140875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21247200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1835182260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 30396506250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 35743331955 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.055238 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 50563679500 # Time in different power states +system.physmem_1.actBackEnergy 1822659075 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 30407483250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 35741598600 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.022916 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 50582866250 # Time in different power states system.physmem_1.memoryStateTime::REF 1781260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 998933000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 980601250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 11450644 # Number of BP lookups -system.cpu.branchPred.condPredicted 8210940 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 11450641 # Number of BP lookups +system.cpu.branchPred.condPredicted 8210938 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765018 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6085193 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5320740 # Number of BTB hits +system.cpu.branchPred.BTBLookups 6085190 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5320739 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.437490 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176675 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.437516 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1176674 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits. @@ -270,22 +270,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20415220 # DTB read hits +system.cpu.dtb.read_hits 20415218 # DTB read hits system.cpu.dtb.read_misses 43383 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20458603 # DTB read accesses +system.cpu.dtb.read_accesses 20458601 # DTB read accesses system.cpu.dtb.write_hits 6579912 # DTB write hits system.cpu.dtb.write_misses 276 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 6580188 # DTB write accesses -system.cpu.dtb.data_hits 26995132 # DTB hits +system.cpu.dtb.data_hits 26995130 # DTB hits system.cpu.dtb.data_misses 43659 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27038791 # DTB accesses -system.cpu.itb.fetch_hits 22968620 # ITB hits +system.cpu.dtb.data_accesses 27038789 # DTB accesses +system.cpu.itb.fetch_hits 22968614 # ITB hits system.cpu.itb.fetch_misses 90 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22968710 # ITB accesses +system.cpu.itb.fetch_accesses 22968704 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 106689529 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 106698901 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2191325 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2191321 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.160892 # CPI: cycles per instruction -system.cpu.ipc 0.861407 # IPC: instructions per cycle +system.cpu.cpi 1.160994 # CPI: cycles per instruction +system.cpu.ipc 0.861331 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction @@ -344,16 +344,16 @@ system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91903089 # Class of committed instruction -system.cpu.tickCycles 103791732 # Number of cycles that the object actually ticked -system.cpu.idleCycles 2897797 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 103791781 # Number of cycles that the object actually ticked +system.cpu.idleCycles 2907120 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.584436 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26572205 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1447.584590 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26572201 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11910.445988 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11910.444195 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.584436 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.584590 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.353414 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353414 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id @@ -363,41 +363,41 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 228 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53153443 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53153443 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20074007 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20074007 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498198 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498198 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26572205 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26572205 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26572205 # number of overall hits -system.cpu.dcache.overall_hits::total 26572205 # number of overall hits +system.cpu.dcache.tags.tag_accesses 53153439 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53153439 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20074005 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20074005 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498196 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498196 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26572201 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26572201 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26572201 # number of overall hits +system.cpu.dcache.overall_hits::total 26572201 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2905 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2905 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3401 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3401 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3401 # number of overall misses -system.cpu.dcache.overall_misses::total 3401 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37448500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37448500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 219755500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 219755500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 257204000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 257204000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 257204000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 257204000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20074503 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20074503 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 2907 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2907 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3403 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3403 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3403 # number of overall misses +system.cpu.dcache.overall_misses::total 3403 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37687000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37687000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 223750000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 223750000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 261437000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 261437000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 261437000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 261437000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20074501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20074501 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26575606 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26575606 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26575606 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26575606 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26575604 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26575604 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26575604 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26575604 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses @@ -406,14 +406,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 system.cpu.dcache.demand_miss_rate::total 0.000128 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75501.008065 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75501.008065 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75647.332186 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75647.332186 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75625.992355 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75625.992355 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75625.992355 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75625.992355 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75981.854839 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75981.854839 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76969.384245 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76969.384245 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76825.448134 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76825.448134 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +424,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1162 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1162 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1170 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1170 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1170 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1170 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1164 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1164 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1172 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1172 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1172 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1172 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses @@ -438,14 +438,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2231 system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36544000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36544000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 137282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 137282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 173826000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 173826000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 173826000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 173826000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36777500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36777500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 140150000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 140150000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 176927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176927500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 176927500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -454,24 +454,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74885.245902 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74885.245902 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78761.904762 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78761.904762 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77913.939937 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77913.939937 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77913.939937 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77913.939937 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75363.729508 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75363.729508 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80407.343660 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80407.343660 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13865 # number of replacements -system.cpu.icache.tags.tagsinuse 1642.714068 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22952789 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1642.701416 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22952783 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15830 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1449.955085 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1449.954706 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1642.714068 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.802106 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.802106 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1642.701416 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.802100 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.802100 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -479,45 +479,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 670 system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45953070 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45953070 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22952789 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22952789 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22952789 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22952789 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22952789 # number of overall hits -system.cpu.icache.overall_hits::total 22952789 # number of overall hits +system.cpu.icache.tags.tag_accesses 45953058 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45953058 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22952783 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22952783 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22952783 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22952783 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22952783 # number of overall hits +system.cpu.icache.overall_hits::total 22952783 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15831 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15831 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15831 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15831 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15831 # number of overall misses system.cpu.icache.overall_misses::total 15831 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 409090000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 409090000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 409090000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 409090000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 409090000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 409090000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22968620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22968620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22968620 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22968620 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22968620 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22968620 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 411111000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 411111000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 411111000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 411111000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 411111000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 411111000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22968614 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22968614 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22968614 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22968614 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22968614 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22968614 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25841.071316 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25841.071316 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25841.071316 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25841.071316 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25841.071316 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25841.071316 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25968.732234 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25968.732234 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25968.732234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25968.732234 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,48 +532,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15831 system.cpu.icache.demand_mshr_misses::total 15831 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15831 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393260000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 393260000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393260000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 393260000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393260000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 393260000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 395281000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 395281000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 395281000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 395281000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 395281000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 395281000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24841.134483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24841.134483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24841.134483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24841.134483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24841.134483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24841.134483 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24968.795401 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24968.795401 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2482.282304 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 26642 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3671 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.257423 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3575.444447 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 26761 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5322 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 5.028373 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.761061 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.458659 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 362.062585 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000542 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.450993 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.993454 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064162 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011049 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.075753 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3671 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 771 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 183 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2509 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.112030 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 262078 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 262078 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_percent::cpu.data 0.044952 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.109114 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5322 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 569 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3605 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.162415 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 261986 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 261986 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 13865 # number of WritebackClean hits @@ -602,18 +600,18 @@ system.cpu.l2cache.demand_misses::total 5322 # nu system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2152 # number of overall misses system.cpu.l2cache.overall_misses::total 5322 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 134394000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 134394000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236583500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 236583500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35249500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 35249500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 236583500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 169643500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 406227000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 236583500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 169643500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 406227000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 137262000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 137262000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 238604500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 238604500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35483000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 35483000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 238604500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 172745000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 411349500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 238604500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 172745000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 411349500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 13865 # number of WritebackClean accesses(hits+misses) @@ -642,18 +640,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.294668 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200253 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964590 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294668 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78272.568433 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78272.568433 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74632.018927 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74632.018927 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81033.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81033.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74632.018927 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78830.622677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76329.763247 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74632.018927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78830.622677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76329.763247 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79942.923704 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79942.923704 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75269.558360 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75269.558360 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81570.114943 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81570.114943 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77292.277339 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77292.277339 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -672,18 +670,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5322 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2152 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5322 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 117224000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 117224000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204883500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204883500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30899500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30899500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204883500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148123500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 353007000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204883500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148123500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 353007000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120092000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120092000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 206904500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 206904500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31133000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31133000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 206904500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151225000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 358129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 206904500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151225000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 358129500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for ReadCleanReq accesses @@ -696,25 +694,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294668 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294668 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68272.568433 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68272.568433 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64632.018927 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64632.018927 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71033.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71033.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64632.018927 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68830.622677 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66329.763247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64632.018927 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68830.622677 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66329.763247 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69942.923704 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69942.923704 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65269.558360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65269.558360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71570.114943 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71570.114943 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution @@ -748,7 +746,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 23745000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3346500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 5322 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3605 # Transaction distribution system.membus.trans_dist::ReadExReq 1717 # Transaction distribution system.membus.trans_dist::ReadExResp 1717 # Transaction distribution @@ -769,9 +773,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5322 # Request fanout histogram -system.membus.reqLayer0.occupancy 6419500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6421000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28179750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28180500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |