diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
| commit | 0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (patch) | |
| tree | 45d559d0511bdca749a08a2f42eeafdcf25739cf /tests/long/se/70.twolf/ref/alpha/tru64/minor-timing | |
| parent | 3de9def6c1ad38d6a5068b07512cbefffafcb758 (diff) | |
| download | gem5-0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e.tar.xz | |
stats: updates due to recent changesets including d0934b57735a
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/minor-timing')
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini | 6 | ||||
| -rwxr-xr-x | tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr | 1 | ||||
| -rwxr-xr-x[-rw-r--r--] | tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout | 13 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt | 742 |
4 files changed, 381 insertions, 381 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini index 459f492af..5ec95ce79 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini @@ -125,7 +125,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -548,7 +548,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -597,7 +597,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr index de77515a1..f0a9a7c93 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr @@ -1,3 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout index 4d57fab87..606ce3744 100644..100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:41:53 -gem5 started May 7 2014 15:05:33 -gem5 executing on cz3212c2d7 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2 +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 20:55:41 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -25,4 +24,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 51810251500 because target called exit() +122 123 124 Exiting @ tick 51910606500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index f4338fb5a..5fb393485 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.052057 # Number of seconds simulated -sim_ticks 52057006500 # Number of ticks simulated -final_tick 52057006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.051911 # Number of seconds simulated +sim_ticks 51910606500 # Number of ticks simulated +final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 338250 # Simulator instruction rate (inst/s) -host_op_rate 338250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 191596351 # Simulator tick rate (ticks/s) -host_mem_usage 300296 # Number of bytes of host memory used -host_seconds 271.70 # Real time elapsed on the host +host_inst_rate 229005 # Simulator instruction rate (inst/s) +host_op_rate 229005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 129351336 # Simulator tick rate (ticks/s) +host_mem_usage 295204 # Number of bytes of host memory used +host_seconds 401.31 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 202752 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory -system.physmem.bytes_read::total 340480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 340416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202752 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5320 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3896037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2644486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6540522 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3896037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3896037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3896037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2644486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6540522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5320 # Number of read requests accepted +system.physmem.num_reads::total 5319 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3905791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2651944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6557735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3905791 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3905791 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3905791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2651944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6557735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5319 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5320 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5319 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 340480 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 340416 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 340480 # Total read bytes from the system interface side +system.physmem.bytesReadSys 340416 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 469 # Per bank write bursts system.physmem.perBankRdBursts::1 295 # Per bank write bursts -system.physmem.perBankRdBursts::2 307 # Per bank write bursts +system.physmem.perBankRdBursts::2 308 # Per bank write bursts system.physmem.perBankRdBursts::3 524 # Per bank write bursts system.physmem.perBankRdBursts::4 224 # Per bank write bursts system.physmem.perBankRdBursts::5 238 # Per bank write bursts system.physmem.perBankRdBursts::6 222 # Per bank write bursts system.physmem.perBankRdBursts::7 289 # Per bank write bursts -system.physmem.perBankRdBursts::8 252 # Per bank write bursts +system.physmem.perBankRdBursts::8 251 # Per bank write bursts system.physmem.perBankRdBursts::9 282 # Per bank write bursts -system.physmem.perBankRdBursts::10 255 # Per bank write bursts +system.physmem.perBankRdBursts::10 254 # Per bank write bursts system.physmem.perBankRdBursts::11 261 # Per bank write bursts system.physmem.perBankRdBursts::12 410 # Per bank write bursts system.physmem.perBankRdBursts::13 344 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 52056919000 # Total gap between requests +system.physmem.totGap 51910519000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5320 # Read request sizes (log2) +system.physmem.readPktSize::6 5319 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 973 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.809866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.712248 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.458818 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 301 30.94% 30.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 209 21.48% 52.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 98 10.07% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 92 9.46% 71.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 72 7.40% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 45 4.62% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 2.47% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 1.95% 88.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 113 11.61% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 973 # Bytes accessed per row activation -system.physmem.totQLat 31528250 # Total ticks spent queuing -system.physmem.totMemAccLat 131278250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26600000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5926.36 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 979 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 346.541369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 213.036393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.369108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 309 31.56% 31.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 207 21.14% 52.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 105 10.73% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 89 9.09% 72.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 7.25% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 31 3.17% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 27 2.76% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 27 2.76% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 113 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 979 # Bytes accessed per row activation +system.physmem.totQLat 35331250 # Total ticks spent queuing +system.physmem.totMemAccLat 135062500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6642.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24676.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25392.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.54 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4340 # Number of row buffer hits during reads +system.physmem.readRowHits 4332 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.58 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9785135.15 # Average gap between requests -system.physmem.pageHitRate 81.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3492720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1905750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19843200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9759450.84 # Average gap between requests +system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3507840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1914000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19835400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3399723600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1761174315 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29685915000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34872054585 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.954967 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49382007750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1738100000 # Time in different power states +system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1735578180 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29619604500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34770500880 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.907929 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49271576750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 931384250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 898679500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21231600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3848040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2099625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3399723600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1805818995 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29646744750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34879431555 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.096868 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49317281000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1738100000 # Time in different power states +system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1825261695 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29540934750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34783421070 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.156857 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49142723000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 996955000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1030068000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 11466165 # Number of BP lookups -system.cpu.branchPred.condPredicted 8229222 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 788767 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6698071 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5372970 # Number of BTB hits +system.cpu.branchPred.lookups 11441088 # Number of BP lookups +system.cpu.branchPred.condPredicted 8207826 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765853 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6077536 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5340604 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.216677 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1174312 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.874494 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1173808 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20431374 # DTB read hits -system.cpu.dtb.read_misses 46957 # DTB read misses +system.cpu.dtb.read_hits 20417089 # DTB read hits +system.cpu.dtb.read_misses 43350 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20478331 # DTB read accesses -system.cpu.dtb.write_hits 6580300 # DTB write hits -system.cpu.dtb.write_misses 270 # DTB write misses +system.cpu.dtb.read_accesses 20460439 # DTB read accesses +system.cpu.dtb.write_hits 6579898 # DTB write hits +system.cpu.dtb.write_misses 278 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6580570 # DTB write accesses -system.cpu.dtb.data_hits 27011674 # DTB hits -system.cpu.dtb.data_misses 47227 # DTB misses +system.cpu.dtb.write_accesses 6580176 # DTB write accesses +system.cpu.dtb.data_hits 26996987 # DTB hits +system.cpu.dtb.data_misses 43628 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27058901 # DTB accesses -system.cpu.itb.fetch_hits 23067346 # ITB hits -system.cpu.itb.fetch_misses 89 # ITB misses +system.cpu.dtb.data_accesses 27040615 # DTB accesses +system.cpu.itb.fetch_hits 22953519 # ITB hits +system.cpu.itb.fetch_misses 90 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 23067435 # ITB accesses +system.cpu.itb.fetch_accesses 22953609 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,67 +293,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 104114013 # number of cpu cycles simulated +system.cpu.numCycles 103821213 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2234090 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2183676 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.132867 # CPI: cycles per instruction -system.cpu.ipc 0.882716 # IPC: instructions per cycle -system.cpu.tickCycles 102384742 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1729271 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.129681 # CPI: cycles per instruction +system.cpu.ipc 0.885205 # IPC: instructions per cycle +system.cpu.tickCycles 102104321 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1716892 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.483845 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26587292 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1447.424804 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26573200 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11922.552466 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11916.233184 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1448.483845 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353634 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353634 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424804 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353375 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353375 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53183674 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53183674 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20089099 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20089099 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 53155492 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53155492 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20075007 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20075007 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6498193 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6498193 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26587292 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26587292 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26587292 # number of overall hits -system.cpu.dcache.overall_hits::total 26587292 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 520 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 520 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 26573200 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26573200 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26573200 # number of overall hits +system.cpu.dcache.overall_hits::total 26573200 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 521 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 521 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2910 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2910 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3430 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3430 # number of overall misses -system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40189000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40189000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 213917000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 213917000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 254106000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 254106000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 254106000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 254106000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20089619 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20089619 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3431 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3431 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3431 # number of overall misses +system.cpu.dcache.overall_misses::total 3431 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40212500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40212500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 214035000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 214035000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 254247500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 254247500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 254247500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 254247500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20075528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20075528 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26590722 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26590722 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26590722 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26590722 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26576631 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26576631 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26576631 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26576631 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77286.538462 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77286.538462 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73510.996564 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73510.996564 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74083.381924 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74083.381924 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74083.381924 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74083.381924 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.546392 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.546392 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74103.031186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74103.031186 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,14 +380,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1165 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1165 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1200 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1200 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1201 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1201 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1201 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1201 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36729500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36729500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 130660500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 130660500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167390000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 167390000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167390000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 167390000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37107000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37107000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131707500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 131707500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168814500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 168814500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168814500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 168814500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -412,69 +412,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75730.927835 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75730.927835 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74877.077364 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74877.077364 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75062.780269 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75062.780269 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75062.780269 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75062.780269 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75477.077364 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75477.077364 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13848 # number of replacements -system.cpu.icache.tags.tagsinuse 1641.495432 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23051532 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15813 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1457.758300 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13850 # number of replacements +system.cpu.icache.tags.tagsinuse 1640.456656 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22937703 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15815 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1450.376415 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1641.495432 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801511 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801511 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456656 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801004 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801004 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 668 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 950 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 671 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 946 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46150505 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46150505 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23051532 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23051532 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23051532 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23051532 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23051532 # number of overall hits -system.cpu.icache.overall_hits::total 23051532 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15814 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15814 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15814 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15814 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15814 # number of overall misses -system.cpu.icache.overall_misses::total 15814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 406574500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 406574500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 406574500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 406574500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 406574500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 406574500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23067346 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23067346 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23067346 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23067346 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23067346 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23067346 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25709.782471 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25709.782471 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25709.782471 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25709.782471 # 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average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82035.879630 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73928.526349 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75876.104138 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74715.977444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73928.526349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75876.104138 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74715.977444 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.294763 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74937.172775 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74937.172775 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74684.343434 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74684.343434 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82909.722222 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82909.722222 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74684.343434 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76538.354254 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75434.104155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74684.343434 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76538.354254 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75434.104155 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -616,106 +616,106 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3169 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3169 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3168 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3168 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 432 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 432 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3169 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3168 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5320 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5319 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5320 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110580000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110580000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 202589500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 202589500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31119500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31119500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202589500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 141699500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 344289000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202589500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 141699500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 344289000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 5319 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111627000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111627000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204920000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204920000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31497000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31497000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143124000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 348044000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143124000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 348044000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200405 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200316 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.890722 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.294851 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.294763 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.294851 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64328.097731 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64328.097731 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63928.526349 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63928.526349 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72035.879630 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72035.879630 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63928.526349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65876.104138 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64715.977444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63928.526349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65876.104138 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64715.977444 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.294763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64937.172775 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64937.172775 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64684.343434 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64684.343434 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 16298 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 13898 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 13900 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15813 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15815 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45474 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45480 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50091 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50097 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1161600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1161728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 32048 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 32052 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 32048 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 32052 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 32048 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 16131000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 32052 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 16133000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23719500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 23722500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3601 # Transaction distribution +system.membus.trans_dist::ReadResp 3600 # Transaction distribution system.membus.trans_dist::ReadExReq 1719 # Transaction distribution system.membus.trans_dist::ReadExResp 1719 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3601 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10640 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10640 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 340480 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3600 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10638 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10638 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 340416 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5320 # Request fanout histogram +system.membus.snoop_fanout::samples 5319 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5320 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5319 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5320 # Request fanout histogram -system.membus.reqLayer0.occupancy 6410500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5319 # Request fanout histogram +system.membus.reqLayer0.occupancy 6413000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28166750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28165750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |