stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

1 files changed, 5 insertions, 14 deletions

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 5ce51dae8..96bd3631d 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.021909                       # Nu
 sim_ticks                                 21909208500                       # Number of ticks simulated
 final_tick                                21909208500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 236201                       # Simulator instruction rate (inst/s)
-host_op_rate                                   236201                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               61475451                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 258056                       # Number of bytes of host memory used
-host_seconds                                   356.39                       # Real time elapsed on the host
+host_inst_rate                                 220296                       # Simulator instruction rate (inst/s)
+host_op_rate                                   220296                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               57335863                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 258312                       # Number of bytes of host memory used
+host_seconds                                   382.12                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -672,8 +672,6 @@ system.cpu.dcache.blocked::no_mshrs               392                       # nu
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    83.017857                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    63.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
 system.cpu.dcache.writebacks::total               108                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          559                       # number of ReadReq MSHR hits
@@ -724,7 +722,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              9515                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1600.928709                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            15918297                       # Total number of references to valid blocks.
@@ -785,8 +782,6 @@ system.cpu.icache.blocked::no_mshrs                 4                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          159                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         9515                       # number of writebacks
 system.cpu.icache.writebacks::total              9515                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2951                       # number of ReadReq MSHR hits
@@ -819,7 +814,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29396.018858
 system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         2407.364249                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              18027                       # Total number of references to valid blocks.
@@ -928,8 +922,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1703                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1703                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3062                       # number of ReadCleanReq MSHR misses
@@ -978,7 +970,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67000.095657
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65472.566950                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69160.508083                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67000.095657                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        23372                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         9673                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.