diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/70.twolf/ref/alpha/tru64/o3-timing | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/o3-timing')
3 files changed, 290 insertions, 196 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index a6f9e5430..10359186b 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -497,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 9901dc40b..f5b2c31fd 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 06:08:28 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:45:24 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 55d9dc21f..221154573 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.029167 # Nu sim_ticks 29167093500 # Number of ticks simulated final_tick 29167093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155660 # Simulator instruction rate (inst/s) -host_tick_rate 53933893 # Simulator tick rate (ticks/s) -host_mem_usage 212576 # Number of bytes of host memory used -host_seconds 540.79 # Real time elapsed on the host +host_inst_rate 198361 # Simulator instruction rate (inst/s) +host_op_rate 198361 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68729352 # Simulator tick rate (ticks/s) +host_mem_usage 214912 # Number of bytes of host memory used +host_seconds 424.38 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated +sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read 332416 # Number of bytes read from this memory system.physmem.bytes_inst_read 193856 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -271,6 +273,7 @@ system.cpu.iew.wb_rate 1.710877 # in system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted @@ -291,7 +294,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle -system.cpu.commit.count 91903055 # Number of instructions committed +system.cpu.commit.committedInsts 91903055 # Number of instructions committed +system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 26497301 # Number of memory references committed system.cpu.commit.loads 19996198 # Number of loads committed @@ -307,6 +311,7 @@ system.cpu.rob.rob_writes 271380444 # Th system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated +system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads @@ -324,26 +329,39 @@ system.cpu.icache.total_refs 18592194 # To system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1593.002324 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.777833 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 18592194 # number of ReadReq hits -system.cpu.icache.demand_hits 18592194 # number of demand (read+write) hits -system.cpu.icache.overall_hits 18592194 # number of overall hits -system.cpu.icache.ReadReq_misses 11853 # number of ReadReq misses -system.cpu.icache.demand_misses 11853 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11853 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 188036500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 188036500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 188036500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 18604047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 18604047 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 18604047 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000637 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000637 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000637 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15864.042858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15864.042858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15864.042858 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1593.002324 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777833 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777833 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 18592194 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18592194 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18592194 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18592194 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18592194 # number of overall hits +system.cpu.icache.overall_hits::total 18592194 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11853 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11853 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11853 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11853 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11853 # number of overall misses +system.cpu.icache.overall_misses::total 11853 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188036500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188036500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188036500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188036500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188036500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188036500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 18604047 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 18604047 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 18604047 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 18604047 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 18604047 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 18604047 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000637 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000637 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000637 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15864.042858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,27 +370,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1225 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1225 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1225 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 124769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 124769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 124769000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000571 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000571 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000571 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11739.649981 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1225 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1225 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1225 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1225 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1225 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1225 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10628 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10628 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10628 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10628 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10628 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10628 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 124769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 124769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124769000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 124769000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11739.649981 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 159 # number of replacements system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use @@ -380,38 +401,59 @@ system.cpu.dcache.total_refs 30399158 # To system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1462.507461 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.357057 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 23906051 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6493055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 52 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 30399106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 30399106 # number of overall hits -system.cpu.dcache.ReadReq_misses 938 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8048 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 8986 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 8986 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28163500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 289889000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 318052500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 318052500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 23906989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30408092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30408092 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.018868 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000296 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000296 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 30025.053305 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 36020.004970 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35394.224349 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35394.224349 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1462.507461 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.357057 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.357057 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23906051 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23906051 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493055 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 30399106 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 30399106 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 30399106 # number of overall hits +system.cpu.dcache.overall_hits::total 30399106 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8048 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8048 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 8986 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8986 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8986 # number of overall misses +system.cpu.dcache.overall_misses::total 8986 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28163500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28163500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289889000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289889000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 38000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 38000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 318052500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 318052500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 318052500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 318052500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23906989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23906989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 30408092 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 30408092 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 30408092 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 30408092 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000039 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001238 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018868 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000296 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000296 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30025.053305 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36020.004970 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -420,36 +462,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 424 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6317 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 78124500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.018868 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000074 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000074 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32041.828794 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35618.139804 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 108 # number of writebacks +system.cpu.dcache.writebacks::total 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6317 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6317 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6741 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6741 # 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number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16469500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16469500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61655000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61655000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78124500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78124500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78124500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78124500 # 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average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2400.275766 # Cycle average of tags in use @@ -457,36 +509,75 @@ system.cpu.l2cache.total_refs 7666 # To system.cpu.l2cache.sampled_refs 3556 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.155793 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2382.642182 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.633584 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000538 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 7655 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 25 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 382.154472 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000538 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.061050 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011662 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.073251 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7599 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 56 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7655 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 25 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 25 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7599 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 12874 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10628 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2246 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 12874 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.285002 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.891262 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985557 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.285002 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963936 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.285002 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963936 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34334.103665 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34410.675381 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34726.846424 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,30 +586,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3488 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5194 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5194 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 108490000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53828000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 162318000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 162318000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313022 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.403449 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.403449 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.784404 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31552.168816 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 459 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3488 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5194 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5194 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 94144500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14345500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108490000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53828000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53828000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 94144500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68173500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 162318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 94144500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68173500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 162318000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.891262 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985557 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.049851 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31253.812636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31552.168816 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |