diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/long/se/70.twolf/ref/alpha/tru64/o3-timing | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/o3-timing')
3 files changed, 687 insertions, 677 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 78509c3e8..104ffdb52 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -599,7 +601,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -628,9 +630,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -641,27 +643,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index c12c73ccb..2cc52ce3f 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 19:15:16 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 12:55:52 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 23461709500 because target called exit() +122 123 124 Exiting @ tick 23058360500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index a6580fdc8..22a3b525f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023496 # Number of seconds simulated -sim_ticks 23495860500 # Number of ticks simulated -final_tick 23495860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023058 # Number of seconds simulated +sim_ticks 23058360500 # Number of ticks simulated +final_tick 23058360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162171 # Simulator instruction rate (inst/s) -host_op_rate 162171 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45264552 # Simulator tick rate (ticks/s) -host_mem_usage 273204 # Number of bytes of host memory used -host_seconds 519.08 # Real time elapsed on the host +host_inst_rate 185322 # Simulator instruction rate (inst/s) +host_op_rate 185322 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50763012 # Simulator tick rate (ticks/s) +host_mem_usage 226392 # Number of bytes of host memory used +host_seconds 454.24 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 196416 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory -system.physmem.bytes_read::total 334528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3064 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 334848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196416 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3069 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8345981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5891761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14237742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8345981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8345981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8345981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5891761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14237742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5227 # Number of read requests accepted +system.physmem.num_reads::total 5232 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8518212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6003549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14521761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8518212 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8518212 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8518212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6003549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14521761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5232 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5232 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334848 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334848 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 469 # Per bank write bursts +system.physmem.perBankRdBursts::0 471 # Per bank write bursts system.physmem.perBankRdBursts::1 291 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts system.physmem.perBankRdBursts::3 524 # Per bank write bursts system.physmem.perBankRdBursts::4 220 # Per bank write bursts -system.physmem.perBankRdBursts::5 226 # Per bank write bursts -system.physmem.perBankRdBursts::6 220 # Per bank write bursts -system.physmem.perBankRdBursts::7 285 # Per bank write bursts -system.physmem.perBankRdBursts::8 236 # Per bank write bursts -system.physmem.perBankRdBursts::9 280 # Per bank write bursts +system.physmem.perBankRdBursts::5 225 # Per bank write bursts +system.physmem.perBankRdBursts::6 219 # Per bank write bursts +system.physmem.perBankRdBursts::7 286 # Per bank write bursts +system.physmem.perBankRdBursts::8 240 # Per bank write bursts +system.physmem.perBankRdBursts::9 278 # Per bank write bursts system.physmem.perBankRdBursts::10 248 # Per bank write bursts -system.physmem.perBankRdBursts::11 254 # Per bank write bursts +system.physmem.perBankRdBursts::11 253 # Per bank write bursts system.physmem.perBankRdBursts::12 398 # Per bank write bursts -system.physmem.perBankRdBursts::13 336 # Per bank write bursts +system.physmem.perBankRdBursts::13 338 # Per bank write bursts system.physmem.perBankRdBursts::14 491 # Per bank write bursts -system.physmem.perBankRdBursts::15 447 # Per bank write bursts +system.physmem.perBankRdBursts::15 448 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23495733500 # Total gap between requests +system.physmem.totGap 23058233500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5227 # Read request sizes (log2) +system.physmem.readPktSize::6 5232 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 383.188005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 230.923786 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 354.572905 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 252 29.07% 29.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 197 22.72% 51.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 79 9.11% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 6.57% 67.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 42 4.84% 72.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 41 4.73% 77.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 51 5.88% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 24 2.77% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 124 14.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 867 # Bytes accessed per row activation -system.physmem.totQLat 41053500 # Total ticks spent queuing -system.physmem.totMemAccLat 139059750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7854.12 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 871 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 381.722158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.044875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.837953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 257 29.51% 29.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 194 22.27% 51.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 9.64% 61.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 7.46% 68.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 4.02% 72.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 4.13% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 31 3.56% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 43 4.94% 85.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 126 14.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 871 # Bytes accessed per row activation +system.physmem.totQLat 38517250 # Total ticks spent queuing +system.physmem.totMemAccLat 136617250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7361.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26604.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26111.86 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.11 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4351 # Number of row buffer hits during reads +system.physmem.readRowHits 4353 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4495070.50 # Average gap between requests -system.physmem.pageHitRate 83.24 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 21787630000 # Time in different power states -system.physmem.memoryStateTime::REF 784420000 # Time in different power states +system.physmem.avgGap 4407154.72 # Average gap between requests +system.physmem.pageHitRate 83.20 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 21416461750 # Time in different power states +system.physmem.memoryStateTime::REF 769860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 919340000 # Time in different power states +system.physmem.memoryStateTime::ACT 869038750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 14237742 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3522 # Transaction distribution -system.membus.trans_dist::ReadResp 3522 # Transaction distribution -system.membus.trans_dist::ReadExReq 1705 # Transaction distribution -system.membus.trans_dist::ReadExResp 1705 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10454 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 334528 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 334528 # Total data (bytes) +system.membus.throughput 14521761 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3525 # Transaction distribution +system.membus.trans_dist::ReadResp 3525 # Transaction distribution +system.membus.trans_dist::ReadExReq 1707 # Transaction distribution +system.membus.trans_dist::ReadExResp 1707 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 334848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6755000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6496500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48973500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 48985000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14867597 # Number of BP lookups -system.cpu.branchPred.condPredicted 10786733 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 927657 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8507235 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6975722 # Number of BTB hits +system.cpu.branchPred.lookups 15361032 # Number of BP lookups +system.cpu.branchPred.condPredicted 11166301 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 940671 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8650721 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7195754 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.997523 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1468896 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3134 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.180974 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1505004 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3205 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23141508 # DTB read hits -system.cpu.dtb.read_misses 194908 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23336416 # DTB read accesses -system.cpu.dtb.write_hits 7073051 # DTB write hits -system.cpu.dtb.write_misses 1111 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 7074162 # DTB write accesses -system.cpu.dtb.data_hits 30214559 # DTB hits -system.cpu.dtb.data_misses 196019 # DTB misses -system.cpu.dtb.data_acv 3 # DTB access violations -system.cpu.dtb.data_accesses 30410578 # DTB accesses -system.cpu.itb.fetch_hits 14761442 # ITB hits -system.cpu.itb.fetch_misses 106 # ITB misses +system.cpu.dtb.read_hits 23573955 # DTB read hits +system.cpu.dtb.read_misses 207074 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 23781029 # DTB read accesses +system.cpu.dtb.write_hits 7120317 # DTB write hits +system.cpu.dtb.write_misses 1134 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7121451 # DTB write accesses +system.cpu.dtb.data_hits 30694272 # DTB hits +system.cpu.dtb.data_misses 208208 # DTB misses +system.cpu.dtb.data_acv 8 # DTB access violations +system.cpu.dtb.data_accesses 30902480 # DTB accesses +system.cpu.itb.fetch_hits 15234213 # ITB hits +system.cpu.itb.fetch_misses 102 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14761548 # ITB accesses +system.cpu.itb.fetch_accesses 15234315 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,238 +285,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46991722 # number of cpu cycles simulated +system.cpu.numCycles 46116722 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15493602 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127144789 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14867597 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8444618 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22164191 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4494518 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5543985 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 114 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2326 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 15940932 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 131589057 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15361032 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8700758 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22892353 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5007718 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2994752 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2134 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14761442 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 326314 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46736650 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.720451 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.375825 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 15234213 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 364576 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 45860852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.869311 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.407633 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24572459 52.58% 52.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2364267 5.06% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1190852 2.55% 60.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1750659 3.75% 63.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2760354 5.91% 69.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1155374 2.47% 72.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1219764 2.61% 74.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 773397 1.65% 76.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10949524 23.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22968499 50.08% 50.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2435887 5.31% 55.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1214898 2.65% 58.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1783514 3.89% 61.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2844070 6.20% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1193047 2.60% 70.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1264346 2.76% 73.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 807487 1.76% 75.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11349104 24.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46736650 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316388 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.705685 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17320813 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4244089 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20558459 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1092640 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3520649 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2518881 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12242 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 124135665 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32164 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3520649 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18467014 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 956444 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7682 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20482522 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3302339 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121292511 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 405307 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2418029 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89077183 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157604141 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150534696 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7069444 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 45860852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.333090 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.853391 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16942268 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2554020 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21969696 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 376134 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4018734 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2597948 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12434 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 128314772 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 36360 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4018734 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17696753 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 830389 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7936 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21575239 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1731801 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 125347310 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9609 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 982853 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 675750 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22720 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 92019426 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 162776933 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 155390791 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7386141 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20649822 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 718 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 707 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8775432 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25394818 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8253633 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2570331 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 907077 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105549830 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2075 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96657653 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 179218 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20902238 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15662437 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1686 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46736650 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.068134 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.876130 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 23592065 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 733 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 723 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3333773 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26203423 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8541215 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2901793 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1268500 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 108868755 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1841 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 97966771 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 305092 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24205687 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18927840 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1452 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 45860852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.136174 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.932064 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12165151 26.03% 26.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9350062 20.01% 46.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8404811 17.98% 64.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6298333 13.48% 77.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4922419 10.53% 88.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2869013 6.14% 94.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1725015 3.69% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 796629 1.70% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 205217 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12004778 26.18% 26.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8735781 19.05% 45.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7795942 17.00% 62.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6187579 13.49% 75.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4939987 10.77% 86.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3238381 7.06% 93.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1831298 3.99% 97.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 880120 1.92% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 246986 0.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46736650 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 45860852 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 189767 12.10% 12.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 186 0.01% 12.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7209 0.46% 12.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5897 0.38% 12.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843167 53.74% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 445094 28.37% 95.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77619 4.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 202355 11.05% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 107 0.01% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 8618 0.47% 11.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 9498 0.52% 12.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 955023 52.14% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 532552 29.07% 93.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 123630 6.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58783696 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479813 0.50% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2802274 2.90% 64.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115457 0.12% 64.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2387860 2.47% 66.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311147 0.32% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760157 0.79% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23859982 24.69% 92.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7156941 7.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59518834 60.75% 60.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 484423 0.49% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2816502 2.87% 64.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115449 0.12% 64.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2407923 2.46% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 312382 0.32% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 763359 0.78% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24335343 24.84% 92.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7212230 7.36% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96657653 # Type of FU issued -system.cpu.iq.rate 2.056908 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1568939 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226667825 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117702286 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87133167 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15132288 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8786528 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7070448 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90230128 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7996457 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1520956 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 97966771 # Type of FU issued +system.cpu.iq.rate 2.124322 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1831783 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018698 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 228533724 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 123769088 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 88239146 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15397545 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9344200 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7119957 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 91612691 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8185856 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1667830 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5398620 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18484 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34785 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1752530 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6207225 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 16318 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 37199 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2040112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10530 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2127 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 40236 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2728 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3520649 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 133897 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18217 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115793083 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 374761 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25394818 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8253633 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2932 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 43 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34785 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 541104 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 495336 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1036440 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95417746 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23336859 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1239907 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4018734 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 14986 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 580703 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119442937 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 327587 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26203423 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8541215 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1841 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 22416 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 558101 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 37199 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 549687 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 504581 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1054268 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 96742235 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23781507 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1224536 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10241178 # number of nop insts executed -system.cpu.iew.exec_refs 30411225 # number of memory reference insts executed -system.cpu.iew.exec_branches 12030179 # Number of branches executed -system.cpu.iew.exec_stores 7074366 # Number of stores executed -system.cpu.iew.exec_rate 2.030522 # Inst execution rate -system.cpu.iew.wb_sent 94727613 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94203615 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64511907 # num instructions producing a value -system.cpu.iew.wb_consumers 89904657 # num instructions consuming a value +system.cpu.iew.exec_nop 10572341 # number of nop insts executed +system.cpu.iew.exec_refs 30903185 # number of memory reference insts executed +system.cpu.iew.exec_branches 12219901 # Number of branches executed +system.cpu.iew.exec_stores 7121678 # Number of stores executed +system.cpu.iew.exec_rate 2.097769 # Inst execution rate +system.cpu.iew.wb_sent 95961828 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 95359103 # cumulative count of insts written-back +system.cpu.iew.wb_producers 65705546 # num instructions producing a value +system.cpu.iew.wb_consumers 92226364 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.004685 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717559 # average fanout of values written-back +system.cpu.iew.wb_rate 2.067777 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.712438 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23891142 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 27540320 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 915882 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43216001 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.126598 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.743951 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 928822 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 41842118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.196425 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.812600 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16755601 38.77% 38.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9919008 22.95% 61.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4484606 10.38% 72.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2269127 5.25% 77.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1610437 3.73% 81.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1128955 2.61% 83.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722092 1.67% 85.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 821021 1.90% 87.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5505154 12.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16239554 38.81% 38.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9401519 22.47% 61.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4137637 9.89% 71.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2136234 5.11% 76.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1534088 3.67% 79.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1088589 2.60% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 699410 1.67% 84.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 798893 1.91% 86.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5806194 13.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43216001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 41842118 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -562,228 +563,229 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 5505154 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5806194 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153504004 # The number of ROB reads -system.cpu.rob.rob_writes 235133069 # The number of ROB writes -system.cpu.timesIdled 5418 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 255072 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 155478259 # The number of ROB reads +system.cpu.rob.rob_writes 242937786 # The number of ROB writes +system.cpu.timesIdled 5286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 255870 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.558231 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.558231 # CPI: Total CPI of All Threads -system.cpu.ipc 1.791373 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.791373 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129151691 # number of integer regfile reads -system.cpu.int_regfile_writes 70572840 # number of integer regfile writes -system.cpu.fp_regfile_reads 6193374 # number of floating regfile reads -system.cpu.fp_regfile_writes 6052358 # number of floating regfile writes -system.cpu.misc_regfile_reads 714605 # number of misc regfile reads +system.cpu.cpi 0.547837 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.547837 # CPI: Total CPI of All Threads +system.cpu.ipc 1.825362 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.825362 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 130779467 # number of integer regfile reads +system.cpu.int_regfile_writes 71543363 # number of integer regfile writes +system.cpu.fp_regfile_reads 6233836 # number of floating regfile reads +system.cpu.fp_regfile_writes 6101151 # number of floating regfile writes +system.cpu.misc_regfile_reads 718857 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 37684936 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 11995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 11995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22964 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4597 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27561 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 885440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 885440 # Total data (bytes) +system.cpu.toL2Bus.throughput 37986395 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 11847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 11847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1732 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4591 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 725568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 875904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 875904 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 7026500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17802750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17583000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3545000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3542750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9548 # number of replacements -system.cpu.icache.tags.tagsinuse 1597.278061 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14747183 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11482 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1284.374064 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9401 # number of replacements +system.cpu.icache.tags.tagsinuse 1598.407560 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15220036 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11337 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1342.510011 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1597.278061 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.779921 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.779921 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1934 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 760 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 930 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.944336 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 29534364 # Number of tag accesses -system.cpu.icache.tags.data_accesses 29534364 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 14747183 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14747183 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14747183 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14747183 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14747183 # number of overall hits -system.cpu.icache.overall_hits::total 14747183 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14258 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14258 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14258 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14258 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14258 # number of overall misses -system.cpu.icache.overall_misses::total 14258 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 414157250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 414157250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 414157250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 414157250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 414157250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 414157250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14761441 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14761441 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14761441 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14761441 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14761441 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14761441 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000966 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000966 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000966 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000966 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000966 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000966 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29047.359377 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29047.359377 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29047.359377 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29047.359377 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29047.359377 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29047.359377 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1598.407560 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.780472 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.780472 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 931 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 30479761 # Number of tag accesses +system.cpu.icache.tags.data_accesses 30479761 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 15220036 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15220036 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15220036 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15220036 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15220036 # number of overall hits +system.cpu.icache.overall_hits::total 15220036 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14176 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14176 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14176 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14176 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14176 # number of overall misses +system.cpu.icache.overall_misses::total 14176 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 411369250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 411369250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 411369250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 411369250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 411369250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 411369250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15234212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15234212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15234212 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15234212 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15234212 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15234212 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000931 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000931 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000931 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000931 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000931 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000931 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29018.711202 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29018.711202 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29018.711202 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29018.711202 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 61.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2776 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2776 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2776 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2776 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2776 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2776 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11482 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11482 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11482 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11482 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11482 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11482 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306274750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 306274750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306274750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 306274750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306274750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 306274750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000778 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000778 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000778 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26674.338094 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26674.338094 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26674.338094 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26674.338094 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26674.338094 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26674.338094 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2839 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2839 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2839 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2839 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2839 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2839 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11337 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11337 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11337 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11337 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11337 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11337 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302662500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 302662500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302662500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 302662500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302662500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 302662500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000744 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000744 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000744 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26696.877481 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26696.877481 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26696.877481 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26696.877481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26696.877481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26696.877481 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2409.001155 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8488 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3589 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.365004 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2409.556828 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8337 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.321637 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.673690 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2011.868133 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 379.459331 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061397 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011580 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073517 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3589 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 17.688406 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2013.956930 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 377.911492 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061461 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011533 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.073534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3591 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 909 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 116000 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 116000 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8418 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8473 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8418 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 81 # 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Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 114811 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114811 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 8268 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8322 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 25 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 25 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8268 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 8347 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8268 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # 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Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2242 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12647.512935 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1456.991941 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355711 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355711 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1456.621503 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355620 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355620 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 56220748 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 56220748 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21606921 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21606921 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492872 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492872 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 225 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 225 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28099793 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28099793 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28099793 # number of overall hits -system.cpu.dcache.overall_hits::total 28099793 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1002 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1002 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8231 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8231 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 56732342 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 56732342 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21862715 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21862715 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492763 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492763 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 246 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 246 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28355478 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28355478 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28355478 # number of overall hits +system.cpu.dcache.overall_hits::total 28355478 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 985 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 985 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8340 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8340 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9233 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9233 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9233 # number of overall misses -system.cpu.dcache.overall_misses::total 9233 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 62924000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 62924000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 508720531 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 508720531 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9325 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9325 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9325 # number of overall misses +system.cpu.dcache.overall_misses::total 9325 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 61174750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 61174750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 507348010 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 507348010 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 571644531 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 571644531 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 571644531 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 571644531 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21607923 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21607923 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 568522760 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 568522760 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 568522760 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 568522760 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21863700 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21863700 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 226 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 226 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28109026 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28109026 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28109026 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28109026 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001266 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001266 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004425 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004425 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62798.403194 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62798.403194 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61805.434455 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61805.434455 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28364803 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28364803 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28364803 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28364803 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001283 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001283 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004049 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004049 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000329 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000329 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000329 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000329 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62106.345178 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62106.345178 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60833.094724 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60833.094724 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61913.195170 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61913.195170 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23691 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60967.588204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60967.588204 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 27950 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 343 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.069971 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.942857 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109 # number of writebacks -system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 490 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 490 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6500 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6500 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6990 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6990 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6990 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6990 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 476 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 476 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6608 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6608 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7084 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7084 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7084 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7084 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 509 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 509 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2243 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36779750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36779750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124808747 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 124808747 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2241 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2241 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2241 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2241 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36463750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36463750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124994997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 124994997 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161588497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161588497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161588497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161588497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161458747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161458747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161458747 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161458747 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004425 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004425 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71835.449219 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71835.449219 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72102.106875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72102.106875 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004049 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004049 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71638.015717 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71638.015717 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72168.012125 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72168.012125 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |