stats: Cumulative stats update

This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.

1 files changed, 47 insertions, 46 deletions

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index b5b638e61..b7d057d9f 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.023492                       # Nu
 sim_ticks                                 23492267500                       # Number of ticks simulated
 final_tick                                23492267500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 122951                       # Simulator instruction rate (inst/s)
-host_op_rate                                   122951                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               34312389                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231868                       # Number of bytes of host memory used
-host_seconds                                   684.66                       # Real time elapsed on the host
+host_inst_rate                                 120531                       # Simulator instruction rate (inst/s)
+host_op_rate                                   120531                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               33636905                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231740                       # Number of bytes of host memory used
+host_seconds                                   698.41                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            195904                       # Number of bytes read from this memory
@@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total            8339084                       # In
 system.physmem.bw_total::cpu.inst             8339084                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data             5898111                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               14237195                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5226                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                           5226                       # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs                          5226                       # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs                            0                       # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts                        5226                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts                          0                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
 system.physmem.bytesRead                       334464                       # Total number of bytes read from memory
 system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
 system.physmem.bytesConsumedRd                 334464                       # bytesRead derated as per pkt->getSize()
 system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by write Q
 system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
 system.physmem.perBankRdReqs::0                   469                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::1                   291                       # Track reads on a per bank basis
@@ -239,10 +240,10 @@ system.membus.trans_dist::ReadReq                3520                       # Tr
 system.membus.trans_dist::ReadResp               3520                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1706                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1706                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side        10452                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                         10452                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side       334464                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                     334464                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10452                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10452                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334464                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              334464                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 334464                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy             6824500                       # Layer occupancy (ticks)
@@ -557,12 +558,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp         12006                       # Tr
 system.cpu.toL2Bus.trans_dist::Writeback          108                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1731                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1731                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side        22984                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side         4598                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                    27582                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side       735488                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side       150592                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size                886080                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        22984                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4598                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             27582                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       735488                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         886080                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.data_through_bus            886080                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy        7030500                       # Layer occupancy (ticks)
@@ -571,15 +572,15 @@ system.cpu.toL2Bus.respLayer0.occupancy      17871250                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       3590750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                   9559                       # number of replacements
-system.cpu.icache.tags.tagsinuse               1595.799290                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 14741729                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                  11492                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                1282.781848                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst    1595.799290                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.779199                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.779199                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements              9559                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1595.799290                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            14741729                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             11492                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1282.781848                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1595.799290                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.779199                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.779199                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst     14741729                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        14741729                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      14741729                       # number of demand (read+write) hits
@@ -655,19 +656,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 25714.605813
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25714.605813                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 25714.605813                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse              2404.485668                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                    8502                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                  3587                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  2.370226                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse         2404.485668                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               8502                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3587                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.370226                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks    17.679636                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   2007.666457                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    379.139575                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2007.666457                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   379.139575                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000540                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061269                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.011570                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.073379                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.073379                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst         8431                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           55                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           8486                       # number of ReadReq hits
@@ -791,15 +792,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52525.726887
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56117.436490                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54013.681592                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                    158                       # number of replacements
-system.cpu.dcache.tags.tagsinuse               1457.925933                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 28096273                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                   2245                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs               12515.043653                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    1457.925933                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.355939                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.355939                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements               158                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1457.925933                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28096273                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2245                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          12515.043653                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  1457.925933                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.355939                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.355939                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     21603146                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        21603146                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      6492891                       # number of WriteReq hits