diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:33 -0600 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:33 -0600 |
commit | f3585c841e964c98911784a187fc4f081a02a0a6 (patch) | |
tree | 2a5a3edeaeb0ffe37ca3a04b884f8f66c7538bbf /tests/long/se/70.twolf/ref/alpha/tru64/o3-timing | |
parent | cfc4a999828a5b51f4c514e3a7c47b4eebc450b9 (diff) | |
download | gem5-f3585c841e964c98911784a187fc4f081a02a0a6.tar.xz |
stats: update stats for cache occupancy and clock domain changes
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/o3-timing')
4 files changed, 48 insertions, 11 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 201e62f46..78509c3e8 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -504,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -520,6 +523,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -529,6 +533,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -550,6 +555,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -566,6 +572,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -592,7 +599,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 2fe61da2d..c12c73ccb 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 16 2013 01:34:33 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 19:15:16 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 23492267500 because target called exit() +122 123 124 Exiting @ tick 23461709500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 445692444..b0acaf58e 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.023462 # Nu sim_ticks 23461709500 # Number of ticks simulated final_tick 23461709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127245 # Simulator instruction rate (inst/s) -host_op_rate 127245 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35464472 # Simulator tick rate (ticks/s) -host_mem_usage 280732 # Number of bytes of host memory used -host_seconds 661.56 # Real time elapsed on the host +host_inst_rate 186682 # Simulator instruction rate (inst/s) +host_op_rate 186682 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52030153 # Simulator tick rate (ticks/s) +host_mem_usage 235304 # Number of bytes of host memory used +host_seconds 450.93 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory system.physmem.bytes_read::total 334592 # Number of bytes read from this memory @@ -244,6 +246,7 @@ system.membus.reqLayer0.occupancy 6831000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 49012250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 14847721 # Number of BP lookups system.cpu.branchPred.condPredicted 10774921 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 922205 # Number of conditional branches incorrect @@ -576,6 +579,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482984 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.779533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.779533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1934 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 766 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 924 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.944336 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 29479830 # Number of tag accesses +system.cpu.icache.tags.data_accesses 29479830 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 14719872 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14719872 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14719872 # number of demand (read+write) hits @@ -664,6 +676,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061354 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.011641 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.073535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3590 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 910 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109558 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 116249 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 116249 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 8448 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 8503 # number of ReadReq hits @@ -796,6 +817,14 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152638 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.356238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.356238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 56179001 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 56179001 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 21586035 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21586035 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6492869 # number of WriteReq hits |