regressions: update stats due to branch predictor changes

The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.

3 files changed, 24 insertions, 15 deletions

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 418ddecee..27f048879 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 boot_osflags=a
+clock=1000
 init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=atomic
+mem_ranges=
 memories=system.physmem
 num_work_ids=16
 readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
 checker=Null
 clock=500
 cpu_id=0
-defer_registration=false
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -42,17 +44,18 @@ fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
+isa=system.cpu.isa
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
-phase=0
 profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
+switched_out=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -67,6 +70,9 @@ size=64
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
+[system.cpu.isa]
+type=AlphaISA
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -82,7 +88,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -99,14 +105,15 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=SimpleMemory
+bandwidth=73.000000
+clock=1000
 conf_table_reported=false
-file=
 in_addr_map=true
 latency=30000
 latency_var=0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
index fbcfa0aae..b0e6a9854 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 11:50:11
-gem5 started Jun  4 2012 13:46:55
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:46:14
+gem5 executing on ribera.cs.wisc.edu
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
 Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav
 Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index 4c4ae20f6..e64f41702 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.045952                       # Nu
 sim_ticks                                 45951567500                       # Number of ticks simulated
 final_tick                                45951567500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3561938                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3561935                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1780967913                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 209744                       # Number of bytes of host memory used
-host_seconds                                    25.80                       # Real time elapsed on the host
+host_inst_rate                                1141309                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1141309                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              570654979                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267644                       # Number of bytes of host memory used
+host_seconds                                    80.52                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst         367612356                       # Number of bytes read from this memory