stats: Update the stats to reflect bus and memory changes

This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.

1 files changed, 40 insertions, 5 deletions

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index aead393ef..b57d95ab0 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.118729                       # Nu
 sim_ticks                                118729316000                       # Number of ticks simulated
 final_tick                               118729316000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1044383                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1044383                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1349235521                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 276220                       # Number of bytes of host memory used
-host_seconds                                    88.00                       # Real time elapsed on the host
+host_inst_rate                                 852211                       # Simulator instruction rate (inst/s)
+host_op_rate                                   852211                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1100968725                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228676                       # Number of bytes of host memory used
+host_seconds                                   107.84                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            167744                       # Number of bytes read from this memory
@@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total            1412827                       # In
 system.physmem.bw_total::cpu.inst             1412827                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data             1155704                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                2568532                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                      2568532                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                3043                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3043                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1722                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1722                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side         9530                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count                          9530                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side       304960                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size                     304960                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 304960                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy             4765000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           42885000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -396,5 +411,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput                 5843207                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           8985                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          8985                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          107                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1748                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1748                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side        17020                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side         4553                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count                    21573                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side       544640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side       149120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size                693760                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            693760                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy        5527000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      12765000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy       3334500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------