Stats: Update stats for RAS and LRU fixes.

3 files changed, 11 insertions, 13 deletions

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 39023eb08..7fbc3a2c7 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -158,7 +158,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
index 3fe1e7489..0bb9be5b6 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -1,12 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 11:50:11
-gem5 started Jun  4 2012 14:18:52
+gem5 compiled Jun 28 2012 22:05:18
+gem5 started Jun 28 2012 22:47:30
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index 5d71f2054..b947ca514 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.118740                       # Nu
 sim_ticks                                118740049000                       # Number of ticks simulated
 final_tick                               118740049000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1590844                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1590843                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2055391195                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218628                       # Number of bytes of host memory used
-host_seconds                                    57.77                       # Real time elapsed on the host
+host_inst_rate                                2205371                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2205370                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2849367775                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222752                       # Number of bytes of host memory used
+host_seconds                                    41.67                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            167744                       # Number of bytes read from this memory
@@ -262,9 +262,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse              2074.048594                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    5951                       # Total number of references to valid blocks.
+system.cpu.l2cache.total_refs                    5956                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                  3109                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  1.914120                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.915729                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.occ_blocks::writebacks    17.795183                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_blocks::cpu.inst   1704.999565                       # Average occupied blocks per requestor