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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-02-16 11:40:34 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-02-16 11:40:34 -0600 |
| commit | 5abbb84f02d4688956a6a042eca2fc0c02f60ae7 (patch) | |
| tree | 7c3373d68f29cb80e6378e3f0c5b3a6513d73d71 /tests/long/se/70.twolf/ref/alpha/tru64 | |
| parent | 0a44e16948fa7274a7890a2bb8710473122f5eca (diff) | |
| download | gem5-5abbb84f02d4688956a6a042eca2fc0c02f60ae7.tar.xz | |
stats: updates due to branch predictor warming
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64')
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt | 11 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt | 1 |
2 files changed, 7 insertions, 5 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 69d43d9de..632b87104 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2604589 # Simulator instruction rate (inst/s) -host_op_rate 2604587 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1302294342 # Simulator tick rate (ticks/s) -host_mem_usage 224388 # Number of bytes of host memory used -host_seconds 35.29 # Real time elapsed on the host +host_inst_rate 1649677 # Simulator instruction rate (inst/s) +host_op_rate 1649676 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 824838449 # Simulator tick rate (ticks/s) +host_mem_usage 275016 # Number of bytes of host memory used +host_seconds 55.71 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -94,5 +94,6 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 91903136 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 10240685 # Number of branches fetched ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index d8a9ee89f..bb6abdd34 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -100,6 +100,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 237458632 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 10240685 # Number of branches fetched system.cpu.icache.tags.replacements 6681 # number of replacements system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. |