diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2015-04-22 20:22:29 -0700 |
---|---|---|
committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2015-04-22 20:22:29 -0700 |
commit | 0cf36d94095aedef3c51447243c5a3cc14dd5d56 (patch) | |
tree | c0ed9e35fbbc5512f7fedf2947d4ae2702214f8e /tests/long/se/70.twolf/ref/alpha/tru64 | |
parent | a70a83155bfe4c3877894c29f9dea720beb40f9c (diff) | |
download | gem5-0cf36d94095aedef3c51447243c5a3cc14dd5d56.tar.xz |
stats: update for previous changeset
Very small differences in IQ-specific O3 stats.
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64')
4 files changed, 28 insertions, 18 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index ca02b53f3..aa4b312c2 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -133,7 +134,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -147,7 +148,6 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu.dcache] type=BaseCache @@ -587,8 +587,11 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 @@ -609,7 +612,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin kvmInSE=false @@ -642,11 +645,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -677,7 +683,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr index de77515a1..f0a9a7c93 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr @@ -1,3 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index f7d4d117a..462b428af 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2014 12:27:06 -gem5 started Jul 19 2014 12:27:28 +gem5 compiled Apr 22 2015 07:55:25 +gem5 started Apr 22 2015 08:19:48 gem5 executing on phenom command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing + +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +24,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 23058360500 because target called exit() +122 123 124 Exiting @ tick 22228749500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 3087f396d..f5ac38df0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.022229 # Nu sim_ticks 22228749500 # Number of ticks simulated final_tick 22228749500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212613 # Simulator instruction rate (inst/s) -host_op_rate 212613 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56143360 # Simulator tick rate (ticks/s) -host_mem_usage 300388 # Number of bytes of host memory used -host_seconds 395.93 # Real time elapsed on the host +host_inst_rate 192800 # Simulator instruction rate (inst/s) +host_op_rate 192800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50911418 # Simulator tick rate (ticks/s) +host_mem_usage 230228 # Number of bytes of host memory used +host_seconds 436.62 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -364,7 +364,7 @@ system.cpu.iq.iqInstsAdded 112744524 # Nu system.cpu.iq.iqNonSpecInstsAdded 2237 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 100145020 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 122649 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 28075682 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 28567051 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 21979359 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1848 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 44211553 # Number of insts issued each cycle @@ -457,10 +457,10 @@ system.cpu.iq.rate 2.252601 # In system.cpu.iq.fu_busy_cnt 2379738 # FU busy when requested system.cpu.iq.fu_busy_rate 0.023763 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 231363005 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131215529 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_writes 131706335 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 90039702 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 15640975 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9648680 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 9649243 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 7175345 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 94170320 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 8354431 # Number of floating point alu accesses |