diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/70.twolf/ref/alpha/tru64 | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64')
12 files changed, 846 insertions, 579 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 64fd65cd8..1763cd3d7 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -202,7 +194,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index ab1cbef0e..ddac6bec8 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:57:18 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:36:18 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index db43e1bd8..7525585e3 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.041834 # Nu sim_ticks 41833966000 # Number of ticks simulated final_tick 41833966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111295 # Simulator instruction rate (inst/s) -host_tick_rate 50660994 # Simulator tick rate (ticks/s) -host_mem_usage 211656 # Number of bytes of host memory used -host_seconds 825.76 # Real time elapsed on the host +host_inst_rate 151560 # Simulator instruction rate (inst/s) +host_op_rate 151560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68989742 # Simulator tick rate (ticks/s) +host_mem_usage 213560 # Number of bytes of host memory used +host_seconds 606.38 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated +sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 316032 # Number of bytes read from this memory system.physmem.bytes_inst_read 178816 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -68,9 +70,10 @@ system.cpu.comNops 7723346 # Nu system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed system.cpu.comInts 43665352 # Number of Integer instructions committed system.cpu.comFloats 3775974 # Number of Floating Point instructions committed -system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads @@ -124,26 +127,39 @@ system.cpu.icache.total_refs 9979713 # To system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1491.782957 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.728410 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 9979713 # number of ReadReq hits -system.cpu.icache.demand_hits 9979713 # number of demand (read+write) hits -system.cpu.icache.overall_hits 9979713 # number of overall hits -system.cpu.icache.ReadReq_misses 11486 # number of ReadReq misses -system.cpu.icache.demand_misses 11486 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11486 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 291407500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 291407500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 291407500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 9991199 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 9991199 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 9991199 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 25370.668640 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 25370.668640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 25370.668640 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1491.782957 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728410 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728410 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 9979713 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 9979713 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 9979713 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 9979713 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 9979713 # number of overall hits +system.cpu.icache.overall_hits::total 9979713 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11486 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11486 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11486 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11486 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11486 # number of overall misses +system.cpu.icache.overall_misses::total 11486 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 291407500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 291407500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 291407500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 291407500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 291407500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 291407500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9991199 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9991199 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9991199 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9991199 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9991199 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9991199 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001150 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001150 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001150 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25370.668640 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -152,27 +168,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2050 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2050 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2050 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 9436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 9436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 9436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 222700000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 222700000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 222700000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000944 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000944 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000944 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23601.102162 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2050 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2050 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2050 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2050 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2050 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2050 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9436 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9436 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9436 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9436 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9436 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9436 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 222700000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 222700000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 222700000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 222700000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 222700000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 222700000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23601.102162 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use @@ -180,32 +199,49 @@ system.cpu.dcache.total_refs 26491206 # To system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1441.532122 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.351937 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 19995645 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6495561 # number of WriteReq hits -system.cpu.dcache.demand_hits 26491206 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 26491206 # number of overall hits -system.cpu.dcache.ReadReq_misses 553 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 5542 # number of WriteReq misses -system.cpu.dcache.demand_misses 6095 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 6095 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28393500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 303801000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 332194500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 332194500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000852 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 51344.484629 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54817.935763 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54502.789171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54502.789171 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1441.532122 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351937 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351937 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995645 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995645 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6495561 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6495561 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26491206 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491206 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491206 # number of overall hits +system.cpu.dcache.overall_hits::total 26491206 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 553 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 553 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5542 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5542 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6095 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6095 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6095 # number of overall misses +system.cpu.dcache.overall_misses::total 6095 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28393500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28393500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 303801000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 303801000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 332194500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 332194500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 332194500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 332194500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000852 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000230 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000230 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51344.484629 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54817.935763 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 41047000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -214,32 +250,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 78 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3794 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3872 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3872 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 92997500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 116210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 116210500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48869.473684 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53202.231121 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3794 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3794 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3872 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3872 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3872 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3872 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23213000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23213000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92997500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92997500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116210500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 116210500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116210500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 116210500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48869.473684 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53202.231121 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2189.253602 # Cycle average of tags in use @@ -247,36 +291,75 @@ system.cpu.l2cache.total_refs 6704 # To system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.042657 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2171.415543 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.838059 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.066266 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 6695 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6721 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6721 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3216 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4938 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 168327500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 90565000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 258892500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 258892500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 9911 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 11659 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 11659 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.324488 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.423535 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.423535 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52340.640547 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52592.915215 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52428.614824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52428.614824 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 17.838059 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.375269 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.040274 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055553 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066811 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 6642 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6695 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 6642 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6721 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 6642 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits +system.cpu.l2cache.overall_hits::total 6721 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2794 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4938 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses +system.cpu.l2cache.overall_misses::total 4938 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146193000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22134500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 168327500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90565000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 90565000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 146193000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112699500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 258892500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 146193000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112699500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 258892500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 9436 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 9911 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 9436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 11659 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 11659 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.296100 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.296100 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.296100 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52323.908375 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52451.421801 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52592.915215 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -285,30 +368,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3216 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4938 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4938 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 129053500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 69344000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 198397500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 198397500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.324488 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.423535 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.423535 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40128.575871 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.454123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2794 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3216 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2794 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4938 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112072000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129053500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69344000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69344000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112072000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86325500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 198397500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112072000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86325500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 198397500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40111.667860 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40240.521327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40269.454123 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index a6f9e5430..10359186b 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -497,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 9901dc40b..f5b2c31fd 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 06:08:28 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:45:24 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 55d9dc21f..221154573 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.029167 # Nu sim_ticks 29167093500 # Number of ticks simulated final_tick 29167093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155660 # Simulator instruction rate (inst/s) -host_tick_rate 53933893 # Simulator tick rate (ticks/s) -host_mem_usage 212576 # Number of bytes of host memory used -host_seconds 540.79 # Real time elapsed on the host +host_inst_rate 198361 # Simulator instruction rate (inst/s) +host_op_rate 198361 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68729352 # Simulator tick rate (ticks/s) +host_mem_usage 214912 # Number of bytes of host memory used +host_seconds 424.38 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated +sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read 332416 # Number of bytes read from this memory system.physmem.bytes_inst_read 193856 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -271,6 +273,7 @@ system.cpu.iew.wb_rate 1.710877 # in system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted @@ -291,7 +294,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle -system.cpu.commit.count 91903055 # Number of instructions committed +system.cpu.commit.committedInsts 91903055 # Number of instructions committed +system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 26497301 # Number of memory references committed system.cpu.commit.loads 19996198 # Number of loads committed @@ -307,6 +311,7 @@ system.cpu.rob.rob_writes 271380444 # Th system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated +system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads @@ -324,26 +329,39 @@ system.cpu.icache.total_refs 18592194 # To system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1593.002324 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.777833 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 18592194 # number of ReadReq hits -system.cpu.icache.demand_hits 18592194 # number of demand (read+write) hits -system.cpu.icache.overall_hits 18592194 # number of overall hits -system.cpu.icache.ReadReq_misses 11853 # number of ReadReq misses -system.cpu.icache.demand_misses 11853 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11853 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 188036500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 188036500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 188036500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 18604047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 18604047 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 18604047 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000637 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000637 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000637 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15864.042858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15864.042858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15864.042858 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1593.002324 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777833 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777833 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 18592194 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18592194 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18592194 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18592194 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18592194 # number of overall hits +system.cpu.icache.overall_hits::total 18592194 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11853 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11853 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11853 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11853 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11853 # number of overall misses +system.cpu.icache.overall_misses::total 11853 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188036500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188036500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188036500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188036500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188036500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188036500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 18604047 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 18604047 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 18604047 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 18604047 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 18604047 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 18604047 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000637 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000637 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000637 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15864.042858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,27 +370,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1225 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1225 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1225 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 124769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 124769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 124769000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000571 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000571 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000571 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11739.649981 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1225 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1225 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1225 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1225 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1225 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1225 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10628 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10628 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10628 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10628 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10628 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10628 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 124769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 124769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124769000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 124769000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11739.649981 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 159 # number of replacements system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use @@ -380,38 +401,59 @@ system.cpu.dcache.total_refs 30399158 # To system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1462.507461 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.357057 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 23906051 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6493055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 52 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 30399106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 30399106 # number of overall hits -system.cpu.dcache.ReadReq_misses 938 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8048 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 8986 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 8986 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28163500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 289889000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 318052500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 318052500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 23906989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30408092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30408092 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.018868 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000296 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000296 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 30025.053305 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 36020.004970 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35394.224349 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35394.224349 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1462.507461 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.357057 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.357057 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23906051 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23906051 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493055 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 30399106 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 30399106 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 30399106 # number of overall hits +system.cpu.dcache.overall_hits::total 30399106 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8048 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8048 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 8986 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8986 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8986 # number of overall misses +system.cpu.dcache.overall_misses::total 8986 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28163500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28163500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289889000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289889000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 38000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 38000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 318052500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 318052500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 318052500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 318052500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23906989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23906989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 30408092 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 30408092 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 30408092 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 30408092 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000039 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001238 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018868 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000296 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000296 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30025.053305 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36020.004970 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -420,36 +462,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 424 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6317 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6741 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6741 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1731 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2245 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16469500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61655000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 78124500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 78124500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.018868 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000074 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000074 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32041.828794 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35618.139804 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 108 # number of writebacks +system.cpu.dcache.writebacks::total 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6317 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6317 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6741 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6741 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6741 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6741 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 514 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2245 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2245 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16469500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16469500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61655000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61655000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78124500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78124500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78124500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78124500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018868 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32041.828794 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35618.139804 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34799.331849 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34799.331849 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2400.275766 # Cycle average of tags in use @@ -457,36 +509,75 @@ system.cpu.l2cache.total_refs 7666 # To system.cpu.l2cache.sampled_refs 3556 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.155793 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2382.642182 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.633584 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000538 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 7655 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 25 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 382.154472 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000538 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.061050 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011662 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.073251 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7599 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 56 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7655 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 25 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 25 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7599 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 75038500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 179036500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10628 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 515 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11143 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 108 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1731 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1731 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10628 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2246 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 12874 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10628 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2246 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 12874 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.285002 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.891262 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985557 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.285002 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963936 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.285002 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963936 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34334.103665 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34410.675381 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34726.846424 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,30 +586,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3488 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5194 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5194 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 108490000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53828000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 162318000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 162318000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313022 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.403449 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.403449 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.784404 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31552.168816 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 459 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3488 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5194 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5194 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 94144500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14345500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108490000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53828000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53828000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 94144500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68173500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 162318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 94144500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68173500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 162318000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.891262 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985557 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.049851 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31253.812636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31552.168816 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index c3b5c0104..452e0175b 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout index 887ca3f4e..b6a6db444 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 06:10:21 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:46:35 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index af93195e1..defa21ce1 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4191883 # Simulator instruction rate (inst/s) -host_tick_rate 2095941744 # Simulator tick rate (ticks/s) -host_mem_usage 202544 # Number of bytes of host memory used -host_seconds 21.92 # Real time elapsed on the host +host_inst_rate 5286635 # Simulator instruction rate (inst/s) +host_op_rate 5286630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2643314521 # Simulator tick rate (ticks/s) +host_mem_usage 204308 # Number of bytes of host memory used +host_seconds 17.38 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated +sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 475949877 # Number of bytes read from this memory system.physmem.bytes_inst_read 367612356 # Number of instructions bytes read from this memory system.physmem.bytes_written 30920974 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 91903136 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 91903056 # Number of instructions executed +system.cpu.committedInsts 91903056 # Number of instructions committed +system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses system.cpu.num_func_calls 2059216 # number of times a function call or return occured diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 2fe44f969..16b0989b3 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout index 84097b1db..1373e7148 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 06:10:54 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:47:03 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index ba87aad33..244f3ca51 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.118740 # Nu sim_ticks 118740049000 # Number of ticks simulated final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2095418 # Simulator instruction rate (inst/s) -host_tick_rate 2707308980 # Simulator tick rate (ticks/s) -host_mem_usage 211256 # Number of bytes of host memory used -host_seconds 43.86 # Real time elapsed on the host +host_inst_rate 2598987 # Simulator instruction rate (inst/s) +host_op_rate 2598985 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3357924345 # Simulator tick rate (ticks/s) +host_mem_usage 213168 # Number of bytes of host memory used +host_seconds 35.36 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated +sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 304960 # Number of bytes read from this memory system.physmem.bytes_inst_read 167744 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -54,7 +56,8 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 237480098 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 91903056 # Number of instructions executed +system.cpu.committedInsts 91903056 # Number of instructions committed +system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses system.cpu.num_func_calls 2059216 # number of times a function call or return occured @@ -78,26 +81,39 @@ system.cpu.icache.total_refs 91894580 # To system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits -system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits -system.cpu.icache.overall_hits 91894580 # number of overall hits -system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses -system.cpu.icache.overall_misses 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1418.037996 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.692401 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.692401 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits +system.cpu.icache.overall_hits::total 91894580 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses +system.cpu.icache.overall_misses::total 8510 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 229222000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 229222000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 229222000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 229222000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 229222000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 229222000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26935.605170 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -106,26 +122,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use @@ -133,32 +147,49 @@ system.cpu.dcache.total_refs 26495078 # To system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits -system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 26495078 # number of overall hits -system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses -system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1442.028823 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352058 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352058 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits +system.cpu.dcache.overall_hits::total 26495078 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses +system.cpu.dcache.overall_misses::total 2223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24374000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24374000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 96796000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 96796000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121170000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121170000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121170000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121170000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51313.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -167,30 +198,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use @@ -198,36 +231,75 @@ system.cpu.l2cache.total_refs 5951 # To system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 5968 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4765 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4765 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 247780000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 247780000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.443958 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 17.795183 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1704.999565 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.253845 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052032 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.063295 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits +system.cpu.l2cache.overall_hits::total 5968 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2621 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3043 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4765 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses +system.cpu.l2cache.overall_misses::total 4765 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 136292000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21944000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 158236000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 89544000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 89544000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 136292000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 111488000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 247780000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 136292000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 111488000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 247780000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,30 +308,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4765 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4765 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 190600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 190600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.443958 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2621 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3043 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104840000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 121720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68880000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68880000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85760000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 190600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |